JPS5591028A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5591028A
JPS5591028A JP16230178A JP16230178A JPS5591028A JP S5591028 A JPS5591028 A JP S5591028A JP 16230178 A JP16230178 A JP 16230178A JP 16230178 A JP16230178 A JP 16230178A JP S5591028 A JPS5591028 A JP S5591028A
Authority
JP
Japan
Prior art keywords
microorder
contents
register
address
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16230178A
Other languages
Japanese (ja)
Other versions
JPS6053334B2 (en
Inventor
Ryushi Hiroya
Sotoji Osada
Kazuhiko Goukon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16230178A priority Critical patent/JPS6053334B2/en
Publication of JPS5591028A publication Critical patent/JPS5591028A/en
Publication of JPS6053334B2 publication Critical patent/JPS6053334B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To give the inversion or noninversion to the contents of the sequential field of the microorder in accordance with the result of the branch test designated by the microorder and then giving the address control to the next microorder according to the inverted or noninverted contents.
CONSTITUTION: The microorder which performs the conditional branching via control memory 10 is read out to register 12, and the test result is applied to line 15. Selector 14 applies the contents or inverted contents of the sequential field of register 12 to decoder 16 of address control circuit 11 according to the test result. Thus decoder 16 gives the control to selection gate 17 to select one of address register 22, head address register 18, jumping destination address register 19 and stack address register 20 each. And control memory 10 receives an access via the selected address.
COPYRIGHT: (C)1980,JPO&Japio
JP16230178A 1978-12-29 1978-12-29 Microprogram control method Expired JPS6053334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16230178A JPS6053334B2 (en) 1978-12-29 1978-12-29 Microprogram control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16230178A JPS6053334B2 (en) 1978-12-29 1978-12-29 Microprogram control method

Publications (2)

Publication Number Publication Date
JPS5591028A true JPS5591028A (en) 1980-07-10
JPS6053334B2 JPS6053334B2 (en) 1985-11-25

Family

ID=15751889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16230178A Expired JPS6053334B2 (en) 1978-12-29 1978-12-29 Microprogram control method

Country Status (1)

Country Link
JP (1) JPS6053334B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166131A (en) * 1987-11-05 1989-06-30 Raytheon Co Next micro-command generator of micro-program controller
JPH01251233A (en) * 1988-03-31 1989-10-06 Toshiba Corp Processor
JPH0243625A (en) * 1988-08-04 1990-02-14 Nec Corp Microprogram control device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01166131A (en) * 1987-11-05 1989-06-30 Raytheon Co Next micro-command generator of micro-program controller
JPH01251233A (en) * 1988-03-31 1989-10-06 Toshiba Corp Processor
JPH0243625A (en) * 1988-08-04 1990-02-14 Nec Corp Microprogram control device

Also Published As

Publication number Publication date
JPS6053334B2 (en) 1985-11-25

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