JPS55131851A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS55131851A
JPS55131851A JP3916179A JP3916179A JPS55131851A JP S55131851 A JPS55131851 A JP S55131851A JP 3916179 A JP3916179 A JP 3916179A JP 3916179 A JP3916179 A JP 3916179A JP S55131851 A JPS55131851 A JP S55131851A
Authority
JP
Japan
Prior art keywords
branch
address
register
destination
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3916179A
Other languages
Japanese (ja)
Inventor
Hisao Takane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3916179A priority Critical patent/JPS55131851A/en
Publication of JPS55131851A publication Critical patent/JPS55131851A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To attain multi-destination branching without imposing a restriction on branch-destination addresses by proviously generating and holding branch address from a branch address in a microinstruction and by selecting one of them as a branch address according to branch conditions.
CONSTITUTION: A microinstruction read out from microinstruction memory unit 10 is stored in control register 20 and at the same time, "+1" is added to an address to unit 10 by "+1" adding circuit 80, whose output is stored in address register 90. Then, arithmetic unit 100 is brought under the control of high-order instructioms stored in register 20 to put arithmetic into effect. Further, branch destination register 30 is stored with branch-destination addresses in instructions and "+1" from "+1" adder 40 is added to each branch destination address to store the results in buffer registers 50W52; and selecting circuit 60 selects according to the test result of test circuit 110 either one of contents of registers 50W52 or that of register 30 and supplies it to selecting circuit 70, which brings multi-destination branching to effect.
COPYRIGHT: (C)1980,JPO&Japio
JP3916179A 1979-03-30 1979-03-30 Microprogram controller Pending JPS55131851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3916179A JPS55131851A (en) 1979-03-30 1979-03-30 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3916179A JPS55131851A (en) 1979-03-30 1979-03-30 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS55131851A true JPS55131851A (en) 1980-10-14

Family

ID=12545387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3916179A Pending JPS55131851A (en) 1979-03-30 1979-03-30 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS55131851A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007237767A (en) * 2006-03-06 2007-09-20 Sekisui Plastics Co Ltd Core material of bumper for vehicle body and bumper using the core material
JP2008149759A (en) * 2006-12-14 2008-07-03 Toyota Motor Corp Bumper structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007237767A (en) * 2006-03-06 2007-09-20 Sekisui Plastics Co Ltd Core material of bumper for vehicle body and bumper using the core material
JP2008149759A (en) * 2006-12-14 2008-07-03 Toyota Motor Corp Bumper structure

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