JPS54129846A - Emulator system - Google Patents
Emulator systemInfo
- Publication number
- JPS54129846A JPS54129846A JP3680078A JP3680078A JPS54129846A JP S54129846 A JPS54129846 A JP S54129846A JP 3680078 A JP3680078 A JP 3680078A JP 3680078 A JP3680078 A JP 3680078A JP S54129846 A JPS54129846 A JP S54129846A
- Authority
- JP
- Japan
- Prior art keywords
- register
- address
- relocation
- emulation
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To substantially zero the time required for the address addition for relocation, by providing the control FF and the specific register to perform the relocation for emulation together with the address operation.
CONSTITUTION: The control FF4 and the specific register 5 are provided. When the system is in emulation mode and FF4 is set, one of the base registers 3 is selected with the instruction set at the instruction register 1, then the content B of the register 3 selected is left output of the adder 6. Further, as the right input of the adder 6, the content LR of the register 5 is inputted to the upper rank 12-bit and the displacement D of the register 1 is inputted to the lower rank 12-bit, and the result of addition B+LR+D is set to the memory address register 7, being the address information of the main memory unit 8. That is, in executing the emulation, the relocation is added together with the address addition effectively one cycle.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3680078A JPS54129846A (en) | 1978-03-31 | 1978-03-31 | Emulator system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3680078A JPS54129846A (en) | 1978-03-31 | 1978-03-31 | Emulator system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54129846A true JPS54129846A (en) | 1979-10-08 |
Family
ID=12479854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3680078A Pending JPS54129846A (en) | 1978-03-31 | 1978-03-31 | Emulator system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54129846A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS626331A (en) * | 1985-07-03 | 1987-01-13 | Nec Corp | Program interface system |
JPS62133533A (en) * | 1985-12-05 | 1987-06-16 | Nec Corp | Switching system for os in electronic computer system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4874942A (en) * | 1971-12-30 | 1973-10-09 | ||
JPS5057348A (en) * | 1973-09-19 | 1975-05-19 |
-
1978
- 1978-03-31 JP JP3680078A patent/JPS54129846A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4874942A (en) * | 1971-12-30 | 1973-10-09 | ||
JPS5057348A (en) * | 1973-09-19 | 1975-05-19 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS626331A (en) * | 1985-07-03 | 1987-01-13 | Nec Corp | Program interface system |
JPS62133533A (en) * | 1985-12-05 | 1987-06-16 | Nec Corp | Switching system for os in electronic computer system |
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