JPS57114945A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS57114945A
JPS57114945A JP116481A JP116481A JPS57114945A JP S57114945 A JPS57114945 A JP S57114945A JP 116481 A JP116481 A JP 116481A JP 116481 A JP116481 A JP 116481A JP S57114945 A JPS57114945 A JP S57114945A
Authority
JP
Japan
Prior art keywords
operation instruction
mua
mub
decoder
interpreted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP116481A
Other languages
Japanese (ja)
Inventor
Kyoichi Tabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP116481A priority Critical patent/JPS57114945A/en
Publication of JPS57114945A publication Critical patent/JPS57114945A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To achieve the execution of two microinstruction words at a time, by adding a memory sufficient for the storage of a simultaneous operation instruction bits, simultaneous operation instruction circuit, two microinstruction registers and decoder. CONSTITUTION:Simultaneous operation instruction bits of microinstruction words muA-muC stored in a control memory 2 are set with 1, 0. The instruction word muA read out through the designation of a control memory address register 1 is stored in registers 3, 4 and an FF7 is set to 1 with the simultaneous operation instruction bits, the instruction word muA from the registers 3, 4 is not interpreted at decoders 5, 6 and no operation instruction is made. Next, the instruction word muB is read out and since the instruction bit is 0, the FF7 is 0, the register 3 stores muB but stores the muA, and the register 4 stores the muB unconditionally. The muA is interpreted at the decoder 5 by making the FF7 zero, an operation instruction signal A is given via a gate 8, the muB is interpreted from the decoder 6 and an operation instruction signal B is given via a gate 9.
JP116481A 1981-01-09 1981-01-09 Microprogram controller Pending JPS57114945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP116481A JPS57114945A (en) 1981-01-09 1981-01-09 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP116481A JPS57114945A (en) 1981-01-09 1981-01-09 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS57114945A true JPS57114945A (en) 1982-07-17

Family

ID=11493792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP116481A Pending JPS57114945A (en) 1981-01-09 1981-01-09 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS57114945A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0107952A2 (en) * 1982-10-18 1984-05-09 Nec Corporation Information processing apparatus and its instruction control system
JPS59128644A (en) * 1983-01-14 1984-07-24 Fuji Xerox Co Ltd Sequence control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0107952A2 (en) * 1982-10-18 1984-05-09 Nec Corporation Information processing apparatus and its instruction control system
JPS59128644A (en) * 1983-01-14 1984-07-24 Fuji Xerox Co Ltd Sequence control circuit

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