JPS56152047A - Microprogram controller - Google Patents
Microprogram controllerInfo
- Publication number
- JPS56152047A JPS56152047A JP5457380A JP5457380A JPS56152047A JP S56152047 A JPS56152047 A JP S56152047A JP 5457380 A JP5457380 A JP 5457380A JP 5457380 A JP5457380 A JP 5457380A JP S56152047 A JPS56152047 A JP S56152047A
- Authority
- JP
- Japan
- Prior art keywords
- register
- address
- circuit
- contents
- held
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To shorten the processing time of instructions by providing a circuit which modifies an address, decoded by an instruction decoder, according to the output of a decision conditioning circuit, by holding the output of the circuit in an instruction address register and by reading the contents of a control storage according to the contents of the register. CONSTITUTION:Data obtained by decoding the contents of instruction register 1 by instruction decoder 2 is inputted to logic circuit 7, whose output is held in microinstruction address register 3. At this time, when a signal inputted from decision conditioning circuit 6 to circuit 7 satisfies the condition with ''1'', address (b) is held as an input address in register 3 and if the condition is not established, address C is held with input signal ''0''. According to the contents of register 3, control memory 4 is controlled to shorten the processing time of instructions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5457380A JPS56152047A (en) | 1980-04-24 | 1980-04-24 | Microprogram controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5457380A JPS56152047A (en) | 1980-04-24 | 1980-04-24 | Microprogram controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56152047A true JPS56152047A (en) | 1981-11-25 |
Family
ID=12974428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5457380A Pending JPS56152047A (en) | 1980-04-24 | 1980-04-24 | Microprogram controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56152047A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6089249A (en) * | 1982-12-23 | 1985-05-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Microword generation mechanism |
-
1980
- 1980-04-24 JP JP5457380A patent/JPS56152047A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6089249A (en) * | 1982-12-23 | 1985-05-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Microword generation mechanism |
JPS6323585B2 (en) * | 1982-12-23 | 1988-05-17 | Intaanashonaru Bijinesu Mashiinzu Corp |
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