JPS56164445A - Information processing device of microprogram control type - Google Patents
Information processing device of microprogram control typeInfo
- Publication number
- JPS56164445A JPS56164445A JP6663280A JP6663280A JPS56164445A JP S56164445 A JPS56164445 A JP S56164445A JP 6663280 A JP6663280 A JP 6663280A JP 6663280 A JP6663280 A JP 6663280A JP S56164445 A JPS56164445 A JP S56164445A
- Authority
- JP
- Japan
- Prior art keywords
- established
- branch instruction
- branch
- conditional
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To execute complementary instructions to one conditional branch simply, by providing a means which inverts a conditional signal in a conditional branch instruction. CONSTITUTION:In a decoder 20 which interpretes a field other than branch instruction fields of a micro-instruction word register 2, a suitable combination of bits not used conventionally is selected, and it is used as the microinstruction to designate the inversion of the branch instruction. When an instrution to designate the inversion of the branch instruction is inputted, since one input of an exclusive logical sum circuit 21 is made to ''1'', the branch condition signal fed to another input is inverted for the logical level to be appeared at the output. As a result, the signal which has been hitherto branched to X when the condition has been established and to Y when not established, is branched to Y when established and to X when not established.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6663280A JPS56164445A (en) | 1980-05-20 | 1980-05-20 | Information processing device of microprogram control type |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6663280A JPS56164445A (en) | 1980-05-20 | 1980-05-20 | Information processing device of microprogram control type |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56164445A true JPS56164445A (en) | 1981-12-17 |
Family
ID=13321452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6663280A Pending JPS56164445A (en) | 1980-05-20 | 1980-05-20 | Information processing device of microprogram control type |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56164445A (en) |
-
1980
- 1980-05-20 JP JP6663280A patent/JPS56164445A/en active Pending
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