JPS5682947A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5682947A
JPS5682947A JP16114279A JP16114279A JPS5682947A JP S5682947 A JPS5682947 A JP S5682947A JP 16114279 A JP16114279 A JP 16114279A JP 16114279 A JP16114279 A JP 16114279A JP S5682947 A JPS5682947 A JP S5682947A
Authority
JP
Japan
Prior art keywords
field
zero
arithmetic
logic
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16114279A
Other languages
Japanese (ja)
Inventor
Hiroshi Nishikawa
Shigeo Shimazaki
Katsura Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16114279A priority Critical patent/JPS5682947A/en
Publication of JPS5682947A publication Critical patent/JPS5682947A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it simple to set information on an arithmetic result state by a double-precision arithmetic instruction in a data processor on a microprogram control system, by providing microinstructions with a field wherein a control bit position is indicated.
CONSTITUTION: For arithmetic between high-priority works, the output of AND gate 316 is selected between zero flag 306 and state signal 307 by selector 315 when microinstructions are executed while field 308 is assigned to addition, field 310 to register C, field 312 to register D, and field 314 to logic "1". Since this means that zero information on a high-priority word arithmetic result and that on a low-priority word arithmetic result are ANDed, zero flag 306 is set to logic "1" and arithmetic results are zero only when the both are zero at logic "1", so that a zero flag can be set by a double-precision addition instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP16114279A 1979-12-11 1979-12-11 Data processor Pending JPS5682947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16114279A JPS5682947A (en) 1979-12-11 1979-12-11 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16114279A JPS5682947A (en) 1979-12-11 1979-12-11 Data processor

Publications (1)

Publication Number Publication Date
JPS5682947A true JPS5682947A (en) 1981-07-07

Family

ID=15729384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16114279A Pending JPS5682947A (en) 1979-12-11 1979-12-11 Data processor

Country Status (1)

Country Link
JP (1) JPS5682947A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276892A (en) * 1987-02-24 1994-01-04 Digital Equipment Corporation Destination control logic for arithmetic and logic unit for digital data processor
EP0418220B1 (en) * 1987-02-24 1996-01-17 Digital Equipment Corporation Destination control logic for arithmetic and logic unit for digital data processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276892A (en) * 1987-02-24 1994-01-04 Digital Equipment Corporation Destination control logic for arithmetic and logic unit for digital data processor
EP0418220B1 (en) * 1987-02-24 1996-01-17 Digital Equipment Corporation Destination control logic for arithmetic and logic unit for digital data processor

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