JPS55121542A - Arithmetic control system - Google Patents

Arithmetic control system

Info

Publication number
JPS55121542A
JPS55121542A JP2950379A JP2950379A JPS55121542A JP S55121542 A JPS55121542 A JP S55121542A JP 2950379 A JP2950379 A JP 2950379A JP 2950379 A JP2950379 A JP 2950379A JP S55121542 A JPS55121542 A JP S55121542A
Authority
JP
Japan
Prior art keywords
byte
flag
alu1
registers
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2950379A
Other languages
Japanese (ja)
Other versions
JPS616410B2 (en
Inventor
Akira Hitomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2950379A priority Critical patent/JPS55121542A/en
Publication of JPS55121542A publication Critical patent/JPS55121542A/en
Publication of JPS616410B2 publication Critical patent/JPS616410B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To reduce flag registers by increasing a processing rate by providing instruction assignment area of a microprocessor for every byte, and also by providing flag registers, stored with flag states of arithmetic results, for every byte.
CONSTITUTION: Arithmetic controller ALU1 performing the logical operation of one lower byte and ALU2 for that of one higher byte are connected to ALU output bus 3 for one lower byte and ALU output bus 4 for one higher byte. External operation mode indication signals 5 and 6 for one lower byte and one higher byte are inputted to ALU1 and ALU2. Flag registers 7 and 8 are stored with flag states of the arithmetic result of ALU1 for one lower byte and one higher byte, respectively. According to the content of the instruction assignment area for microinstructions, corresponding microprocessors are given independent operation indications to update the contents of registers 7 and 8 separately.
COPYRIGHT: (C)1980,JPO&Japio
JP2950379A 1979-03-14 1979-03-14 Arithmetic control system Granted JPS55121542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2950379A JPS55121542A (en) 1979-03-14 1979-03-14 Arithmetic control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2950379A JPS55121542A (en) 1979-03-14 1979-03-14 Arithmetic control system

Publications (2)

Publication Number Publication Date
JPS55121542A true JPS55121542A (en) 1980-09-18
JPS616410B2 JPS616410B2 (en) 1986-02-26

Family

ID=12277880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2950379A Granted JPS55121542A (en) 1979-03-14 1979-03-14 Arithmetic control system

Country Status (1)

Country Link
JP (1) JPS55121542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191964A (en) * 1994-08-05 1995-07-28 Sanyo Electric Co Ltd Digital signal processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191964A (en) * 1994-08-05 1995-07-28 Sanyo Electric Co Ltd Digital signal processor

Also Published As

Publication number Publication date
JPS616410B2 (en) 1986-02-26

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