JPS55134423A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS55134423A
JPS55134423A JP4049979A JP4049979A JPS55134423A JP S55134423 A JPS55134423 A JP S55134423A JP 4049979 A JP4049979 A JP 4049979A JP 4049979 A JP4049979 A JP 4049979A JP S55134423 A JPS55134423 A JP S55134423A
Authority
JP
Japan
Prior art keywords
cpu2
register
channel number
contents
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4049979A
Other languages
Japanese (ja)
Inventor
Hiroaki Yokomichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4049979A priority Critical patent/JPS55134423A/en
Publication of JPS55134423A publication Critical patent/JPS55134423A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To perform I/O control of multiprocessors with a simple circuit constitution, by providing a register, which stores the channel number of a CPU each time the I/O instruction from plural CPUs is accepted, in every I/O device.
CONSTITUTION: CPU2 reads out the value of the register in RAM14 assigned for an I/O device; and if its contents are the channel number of CPU2 itself and CPU2 needs to instruct the I/O device, CPU2 issues an instruction to the I/O device. The I/O device after use interrupts CPU2 of the storage channel number of register 5 for itself. Then, the value of register 5 is rewritten for the channel number of another CPU2. Meanwhile, if CPU2 need not issue an instruction to the I/O device, the value of register 5 is rewritten for the channel of another CPU3. When CPU2 reads out contents of register 5 and its contents indicate another channel number, instructions to the I/O device are inhibited, and it is unnecessary to rewrite contents of register 5.
COPYRIGHT: (C)1980,JPO&Japio
JP4049979A 1979-04-04 1979-04-04 Input/output control system Pending JPS55134423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4049979A JPS55134423A (en) 1979-04-04 1979-04-04 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4049979A JPS55134423A (en) 1979-04-04 1979-04-04 Input/output control system

Publications (1)

Publication Number Publication Date
JPS55134423A true JPS55134423A (en) 1980-10-20

Family

ID=12582248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4049979A Pending JPS55134423A (en) 1979-04-04 1979-04-04 Input/output control system

Country Status (1)

Country Link
JP (1) JPS55134423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180347A (en) * 1984-09-26 1986-04-23 Fujitsu Ltd Control system of input/output device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180347A (en) * 1984-09-26 1986-04-23 Fujitsu Ltd Control system of input/output device

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