JPS55115146A - Program trace unit - Google Patents

Program trace unit

Info

Publication number
JPS55115146A
JPS55115146A JP2131879A JP2131879A JPS55115146A JP S55115146 A JPS55115146 A JP S55115146A JP 2131879 A JP2131879 A JP 2131879A JP 2131879 A JP2131879 A JP 2131879A JP S55115146 A JPS55115146 A JP S55115146A
Authority
JP
Japan
Prior art keywords
memory
trace information
cpu1
program
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2131879A
Other languages
Japanese (ja)
Inventor
Nobuhiro Unosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2131879A priority Critical patent/JPS55115146A/en
Publication of JPS55115146A publication Critical patent/JPS55115146A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To realize the pickup of trace information with minimum load, by enabling it at the occurrence of branch instruction or interruption automatically without indication of it with the software.
CONSTITUTION: The program trace unit is constituted with the memory 2 executing the operational processing at CPU1, memory 4 to store the trace information and external memory unit 5 to store the trace information for a long period. Further, when the program in a certain part of the memory 2 is executed at CPU1, and every time when internal and external interruption is caused to the branch instruction area, CPU1 writes in the memory content designated, IC counter and each register as the trace information to the memory 4 in predetermined form sequentially and primarily stores them. Further, the processor 3 connected to CPU1 writes in the trace information to the external memory unit 5 when the trace information written in the memory 4 is a given amount for secondary storage and feeds it to the line printer 6 with the instruction by the operator.
COPYRIGHT: (C)1980,JPO&Japio
JP2131879A 1979-02-27 1979-02-27 Program trace unit Pending JPS55115146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2131879A JPS55115146A (en) 1979-02-27 1979-02-27 Program trace unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2131879A JPS55115146A (en) 1979-02-27 1979-02-27 Program trace unit

Publications (1)

Publication Number Publication Date
JPS55115146A true JPS55115146A (en) 1980-09-04

Family

ID=12051798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2131879A Pending JPS55115146A (en) 1979-02-27 1979-02-27 Program trace unit

Country Status (1)

Country Link
JP (1) JPS55115146A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181154A (en) * 1982-04-16 1983-10-22 Nec Corp Microprogram tracing device
JPH06259282A (en) * 1993-03-10 1994-09-16 Nec Corp Debugging interruption processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58181154A (en) * 1982-04-16 1983-10-22 Nec Corp Microprogram tracing device
JPH046024B2 (en) * 1982-04-16 1992-02-04 Nippon Electric Co
JPH06259282A (en) * 1993-03-10 1994-09-16 Nec Corp Debugging interruption processor

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