JPH06259282A - Debugging interruption processor - Google Patents

Abstract

PURPOSE:To reduce the performance drop of debugging interruption processing in comparison with the case of sampling trace information with the software of debugging interruption processing. CONSTITUTION:A stack pointer 2 is incremented or decremented corresponding to an interrupting instruction from a debugging interruption generating part 1 and when interruption is generated and incremented by inputting an interruption processing end instruction, it is decremented or when the interruption is decremented, it is incremented. A trace information storage pointer 4 is incremented by the interrupting instruction from the debugging interruption generating part 1. A main storage part 3 stores internal information 100 at the time of interruption generation respectively with the interrupting instruction of the debugging interruption generating part 1 as a write instruction B and with the values of the stack pointer 2 and trace information storage pointer 4 as write addresses A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug interrupt processing device, and more particularly to a method for collecting information for analyzing a software instruction sequence using a debug interrupt.

[0002]

2. Description of the Related Art Conventionally, as a method of collecting trace information by utilizing a debug interrupt, there is a method of collecting trace information by software for debug interrupt processing.

Usually, many information processing apparatuses have a mechanism called a debug interrupt, and this mechanism enables a debug interrupt to be generated for each instruction, for example. When a debug interrupt occurs, the internal state is stored in a stack area or the like so that the state of the information processing device before the debug interrupt can be reproduced in order to find the cause of the debug interrupt.

That is, as shown in FIG. 7, when the debug interrupt generation unit 1 generates a debug interrupt, the internal information 100 of the information processing apparatus is stored in the stack area of the main storage unit 3 indicated by the stack pointer 2. .

The debug interrupt generator 1 has one or more debug interrupt factors 1a-1 to 1a-n, and depending on the result of the OR gate 1b which takes the OR of these debug interrupt factors 1a-1 to 1a-n. To generate an interrupt instruction.

The stack pointer 2 increments or decrements the value of the register 2a by the adder 2b or the subtractor 2c according to an interrupt instruction from the debug interrupt generator 1. When the interrupt processing end instruction 101 is input, the stack pointer 2 decrements the value of the register 2a if it is incremented when an interrupt occurs, and increments the value of the register 2a if it is decremented. ing.

The main storage unit 3 stores the programs and data of the information processing device, and the interrupt instruction from the debug interrupt generation unit 1 is used as a write instruction, and the value of the stack pointer 2 is used as a write address, and an internal state at the time of an interrupt is generated. Information 10
It also stores 0.

The process of storing the internal information 100 in the main memory 3 when a debug interrupt occurs is performed as shown in FIG. That is, when the debug interrupt generation unit 1 generates a debug interrupt, the internal state of the main storage unit 3 changes from state 1 to state 6.

Here, the IC in FIG. 8 is an address indicated by the value of an instruction counter (not shown), and indicates the position of the instruction executed by the information processing device. Further, SP is an address indicated by the value of the stack pointer 2 and indicates a position where the internal information 100 is stored when the debug interrupt generation unit 1 generates a debug interrupt.

Further, A, B, and C respectively indicate the instructions executed by the information processing apparatus, and A ', B', and C'are stored when an interrupt occurs after the execution of the instructions A, B, and C, respectively. It shows internal information. 8 shows the stack pointer 2
Is decremented when an interrupt occurs and incremented when the interrupt process ends.

First, in the state 1, the IC shows the state before the instruction A, and shows the state immediately before the execution of the instruction A. When the debug interrupt generation unit 1 generates a debug interrupt after the instruction A is executed in this state, the IC position moves to the interrupt processing position and the stack pointer 2 is decremented to the SP position after execution of the instruction A. Internal information A ′ is stored (see state 2 in FIG. 8).

Next, when returning to the original program by the interrupt processing end instruction 101, a command A is given to the inside of the information processing apparatus based on the internal information A'stored in the SP position of state 2.
Set to the state after execution. At this time, the value of IC is the instruction A
The position after execution is set, and the stack pointer 2 is incremented to return the position of SP to the position before the occurrence of the debug interrupt (see state 3 in FIG. 8).

When the instructions B and C are executed and the debug interrupt generation unit 1 subsequently generates a debug interrupt in the same manner as the above-described operation, the internal state of the main memory unit 3 changes from state 4 to state 6. . In this case, the internal information B ′ and C ′ after the execution of the instructions B and C are sequentially overwritten in the stack area of the main storage unit 3 where the internal information A ′ was stored after the execution of the instruction A.

During the above interrupt processing period, each instruction A,
The internal information A ′, B ′, C ′ after execution of B, C is stored in the SP position, and it is possible to know what instruction was executed before entering the interrupt processing.

Therefore, the operation of the information processing apparatus for each instruction is confirmed by generating a debug interrupt for each instruction and looking at the internal information stored in the stack area at that time. It is possible to collect trace information.

However, as shown in states 4 and 6,
The internal information stored in the stack area is destroyed every time an instruction is executed. Therefore, when trying to collect trace information, it is necessary to store the internal information stored in the stack area or the like in another area by software during interrupt processing for each debug interrupt.

[0017]

In the above-described conventional trace information collection method using debug interrupts, when attempting to collect trace information using debug interrupts, the processing amount of software for interrupt processing increases. However, there is a problem that the execution performance is reduced.

Therefore, an object of the present invention is to solve the above problems and to reduce the performance degradation of debug interrupt processing as compared with the case where trace information is collected by software for debug interrupt processing. To provide.

[0019]

A debug interrupt processing apparatus according to the present invention has a function of storing an internal state of the apparatus in a main memory designated by a stack pointer in response to an interrupt when an interrupt occurs according to the operation of software. A debug interrupt processing device for storing an internal state at the time of a debug interrupt by using a storage area for storing the internal state, which is provided outside the area on the main memory designated by the stack pointer, and the debug state. There is provided a generation means for sequentially generating addresses of the storage area in response to an interrupt, and a means for storing the internal state in the area on the main memory and the storage area in response to the debug interrupt.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the debug interrupt generator 1 is 1
Or, it has a plurality of debug interrupt factors 1a-1 to 1a-n, and these debug interrupt factors 1a-1 to 1a-n are included.
The interrupt instruction is generated in accordance with the result of the OR gate 1b which takes the OR of.

The stack pointer 2 increments or decrements the value of the register 2a by the adder 2b or the subtractor 2c according to an interrupt instruction from the debug interrupt generator 1. When the interrupt processing end instruction 101 is input, the stack pointer 2 decrements the value of the register 2a if it is incremented when an interrupt occurs, and increments the value of the register 2a if it is decremented. ing.

The main memory 3 stores programs and data of the information processing device, and the interrupt instruction of the debug interrupt generator 1 is used as a write instruction, and the value of the stack pointer 2 is used as a write address, so that the internal memory at the time of the interrupt is generated. The information 100 is also stored.

The trace information storage pointer 4 increments the value of the register 4a by the adder 4b in response to an interrupt instruction from the debug interrupt generator 1. Here, the value of the trace information storage pointer 4 specifies the address at which the internal information 100 is stored by the interrupt instruction from the debug interrupt generation unit 1, independently of the address of the main storage unit 3 specified by the stack pointer 2. .

In the figure, the interrupt instruction from the debug interrupt generation unit 1 is doubly input to the write instruction of the main storage unit 3 because the internal information 100 is the address indicated by the stack pointer 2 and the trace information storage pointer 4. Indicates that writing is performed at the address indicated by.

FIG. 2 is a diagram showing a process of storing the internal information 100 in the main memory 3 of FIG. 1 when a debug interrupt occurs.
In the figure, the internal states of the main memory unit 3 when the debug interrupt generation unit 1 generates a debug interrupt for each instruction are shown in order from state 1 to state 6.

Here, the IC in the figure is an address indicated by the value of an instruction counter (not shown), and indicates the position of the instruction executed by the information processing apparatus. SP is an address indicated by the value of the stack pointer 2, and indicates a position where the internal information 100 is stored when the debug interrupt generation unit 1 generates a debug interrupt.

TP is an address indicated by the value of the trace information storage pointer 4, and indicates the position where the internal information 100 is stored when the debug interrupt generation unit 1 generates a debug interrupt.

A, B, and C respectively indicate the instructions executed by the information processing apparatus, and A ', B', and C'indicate the instructions A and B, respectively.
The internal information stored when an interrupt occurs after executing B and C is shown. FIG. 2 shows an example in which the stack pointer 2 is decremented when an interrupt occurs and incremented when the interrupt process ends.

The operation of storing the internal information 100 according to the embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

First, in state 1, the IC shows the state before the instruction A, and shows the state immediately before the execution of the instruction A. When the debug interrupt generating unit 1 generates a debug interrupt after the instruction A is executed in this state, the IC position moves to the interrupt processing position.

At this time, the stack pointer 2 is decremented and the internal information A'after execution of the instruction A is stored in the position of SP. At the same time, the internal information A ′ after the execution of the instruction A is stored in the position of TP, and the trace information storage pointer 4 is incremented (see state 2 in FIG. 2).

Next, when returning to the original program by the interrupt processing end instruction 101, the instruction A is given to the inside of the information processing apparatus based on the internal information A'stored in the SP position of state 2.
Set to the state after execution. At this time, the value of IC is the instruction A
The position after execution is set, and the stack pointer 2 is incremented to return the position of SP to the position before the occurrence of the debug interrupt. However, when returning to the original program from the interrupt processing, the position of TP is not updated (see state 3 in FIG. 2).

Similar to the storage operation of the internal information 100 described above, after the instruction B is executed, the debug interrupt generation unit 1
Generates a debug interrupt, the IC position moves to the interrupt processing position.

At this time, the stack pointer 2 is decremented and the internal information B'after execution of the instruction B is stored at the SP position. At the same time, the internal information B ′ after execution of the instruction B is stored in the position of TP and the trace information storage pointer 4 is incremented (see state 4 in FIG. 2).

In this case, at the position designated by the SP, the instruction B is stored in the area where the internal information A'after execution of the instruction A is stored.
The internal information B ′ after execution is overwritten. On the other hand, the trace information storage pointer 4 is not updated by the interrupt processing end instruction 101 at the position designated by TP. Therefore, 1 is set at the position indicated by TP in the main storage unit 3.
The internal information B ′ after the execution of the instruction B is stored next to the internal information A ′ after the execution of the instruction A before the instruction.

When returning to the original program by the interrupt processing end instruction 101, the inside of the information processing apparatus is set to the state after the execution of the instruction B based on the internal information B ′ stored in the SP position of state 2.

At this time, the value of IC is set to the position after execution of the instruction B, the stack pointer 2 is incremented, and the position of SP returns to the position before the occurrence of the debug interrupt. However, when returning from the interrupt processing to the original program, the position of TP is not updated (see state 5 in FIG. 2).

Subsequently, when the debug interrupt generator 1 generates a debug interrupt after the instruction C is executed, the IC position moves to the interrupt processing position. At this time, the stack pointer 2 is decremented and the internal information C ′ after the execution of the instruction C is stored in the position of SP. At the same time, the internal information C ′ after execution of the instruction C is stored in the position of TP, and the trace information storage pointer 4 is incremented (see state 6 in FIG. 2).

In this case, at the position designated by the SP, the instruction C is stored in the area where the internal information B'after execution of the instruction B is stored.
The internal information C ′ after execution is overwritten. On the other hand, the trace information storage pointer 4 is not updated by the interrupt processing end instruction 101 at the position designated by TP. Therefore, 1 is set at the position indicated by TP in the main storage unit 3.
The internal information C ′ after the execution of the instruction C is stored next to the internal information B ′ after the execution of the instruction B before the instruction.

Therefore, after execution of all the instructions A, B, C, internal information A ', B', for each instruction execution from the initial value of TP to the position of TP after completion of execution of the last instruction.
C'is stored, and these internal information A ',
Trace information can be collected by analyzing B ′ and C ′.

As described above, in one embodiment of the present invention, the internal information A ',
Since it is not necessary to store B'and C'in another area,
The performance degradation of debug interrupt processing can be reduced as compared with the case of collecting trace information only by software.

However, the trace information is not always necessary when the debug interrupt occurs, and when the trace information is unnecessary, writing the internal information to the area designated by the trace information storage pointer 4 is a wasteful process. This useless processing also causes the performance of debug interrupt processing to deteriorate.

Therefore, in another embodiment of the present invention, a flag for designating whether or not the internal information is written to the area designated by the trace information storage pointer 4 when a debug interrupt occurs is provided. Therefore, by writing the internal information, the performance degradation of the debug interrupt processing when the trace information is unnecessary is suppressed.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a debug interrupt processing apparatus according to another embodiment of the present invention uses internal information 1 to an area designated by a trace information storage pointer 4 when a debug interrupt occurs.
The configuration is the same as that of the embodiment of the present invention shown in FIG. 1 except that a trace collection flag (F) 5 for designating whether to write 00 is provided. Is attached. Further, the operation of the same component is the same as that of the embodiment of the present invention, and thus the description of the operation will be omitted.

The trace collection flag 5 is a flag for designating whether or not the internal information 100 is stored at the address designated by the trace information storage pointer 4 by the interrupt instruction. The trace collection instruction unit 6 outputs a write instruction to the main storage unit 3 according to the interrupt instruction from the debug interrupt generation unit 1 and the content of the trace collection flag 5.

That is, the trace collection instruction unit 6 outputs the interrupt instruction from the debug interrupt generation unit 1 to the write instruction in the main storage unit 3 when the trace collection flag 5 is valid, and is designated by the trace information storage pointer 4. The internal information 100 is written in the address of the main storage unit 3. At the same time, the trace collection instruction unit 6 instructs the trace information storage pointer 4 to increment.

Further, the trace collection instruction unit 6 suppresses outputting the interrupt instruction from the debug interrupt generation unit 1 to the write instruction of the main storage unit 3 when the trace collection flag 5 is invalid. At the same time, the trace collection instruction unit 6 suppresses the increment instruction to the trace information storage pointer 4. Therefore, the internal information 100 is not written to the address of the main memory 3 designated by the trace information storage pointer 4.

FIG. 4 is a diagram showing a process of storing the internal information 100 in the main memory 3 of FIG. 3 when a debug interrupt occurs.
In the figure, the internal states of the main memory unit 3 when the debug interrupt generation unit 1 generates a debug interrupt for each instruction are shown in order from state 1 to state 6. Here, the trace collection flag 5 is valid before the execution of the instructions A and C,
It is invalid before the execution of instruction B.

A storage operation of the internal information 100 according to another embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

First, in state 1, the IC shows the state before the instruction A, and shows the state immediately before the execution of the instruction A. When the debug interrupt generating unit 1 generates a debug interrupt after the instruction A is executed in this state, the IC position moves to the interrupt processing position.

At this time, the stack pointer 2 is decremented and the internal information A'after execution of the instruction A is stored at the SP position. In this case, since the trace collection flag 5 is valid, the trace collection instruction unit 6 outputs the interrupt instruction from the debug interrupt generation unit 1 to the write instruction of the main storage unit 3. Therefore, the internal information A ′ after execution of the instruction A is stored at the position of TP, and the trace information storage pointer 4 is incremented (see state 2 in FIG. 4).

Next, when returning to the original program by the interrupt processing end instruction 101, a command A is given to the inside of the information processing apparatus based on the internal information A'stored in the SP position of state 2.
Set to the state after execution.

At this time, the value of IC is set to the position after execution of the instruction A, the stack pointer 2 is incremented, and the position of SP returns to the position before the occurrence of the debug interrupt. However, when returning to the original program from the interrupt processing, the position of TP is not updated (see state 3 in FIG. 4).

After that, when the debug interrupt generation unit 1 generates a debug interrupt after the instruction B is executed, the IC position moves to the interrupt processing position. At this time, the stack pointer 2 is decremented and the internal information B ′ after the execution of the instruction B is stored at the SP position.

On the other hand, in this case, since the trace collection flag 5 is invalid, the trace collection instruction unit 6
Is an interrupt instruction from the debug interrupt generator 1 to the main memory 3
Suppress output to the writing instruction of. Therefore, the internal information B ′ after execution of the instruction B is not stored in the position of TP, and the trace information storage pointer 4 is not incremented (see state 4 in FIG. 4).

When returning to the original program by the interrupt processing end instruction 101, the inside of the information processing apparatus is set to the state after the execution of the instruction B based on the internal information B'stored in the SP position of the state 2. At this time, the value of IC is set to the position after the execution of instruction B, the stack pointer 2 is incremented, and the position of SP returns to the position before the occurrence of the debug interrupt (see state 5 in FIG. 4).

Then, when the debug interrupt generation unit 1 generates a debug interrupt after the instruction C is executed, the IC position moves to the interrupt processing position. At this time, the stack pointer 2 is decremented and the internal information C ′ after the execution of the instruction C is stored in the position of SP.

In this case, since the trace collection flag 5 is valid, the trace collection instruction unit 6 outputs the interrupt instruction from the debug interrupt generation unit 1 to the write instruction of the main storage unit 3. Therefore, the internal information C ′ after execution of the instruction C is stored at the position of TP, and the trace information storage pointer 4 is incremented (see state 6 in FIG. 4).

At the position indicated by SP in this state 6, the internal information C'after execution of the instruction C is overwritten in the area where the internal information B'after execution of the instruction B is stored. On the other hand, at the position designated by TP, the trace information storage pointer 4 is not updated by the interrupt processing end instruction 101, and the trace collection flag 5 is invalid before the execution of the instruction B. Therefore, the internal information C ′ after the execution of the instruction C is stored next to the internal information A ′ after the execution of the instruction A two instructions before in the position indicated by TP in the main storage unit 3.

As described above, by providing the trace collection flag 5 and the trace collection instruction section 6, the writing of the internal information to the area designated by the trace information storage pointer 4 can be suppressed when the trace information is unnecessary. it can. As a result, it is possible to prevent the performance of debug interrupt processing from being degraded due to the writing of internal information to the area designated by the trace information storage pointer 4.

By the way, in one embodiment and another embodiment of the present invention, the trace information is stored in the main memory 3. Therefore, in the interrupt process at the time of collecting trace information, the main storage unit 3
Since more write instructions are output than normal debug interrupts, the performance degradation of debug interrupt processing when collecting trace information cannot be made zero.

Therefore, in another embodiment of the present invention, a dedicated storage device for collecting the trace information is provided, and the output of the write instruction to the main storage unit 3 in the interrupt processing at the time of collecting the trace information is reduced to reduce the debug interrupt. It suppresses the deterioration of processing performance.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a debug interrupt processing apparatus according to another embodiment of the present invention is provided with a dedicated trace information storage unit 7 for collecting trace information, and outputs the trace information storage pointer 4 and the trace collection instruction unit 6 as trace information storage. The configuration is the same as that of the other embodiment of the present invention in FIG. 3 except that the input is made to the section 7, and the same components are designated by the same reference numerals. Also, the operation of the same component is the same as that of the other embodiments of the present invention, and thus the description of the operation is omitted.

The trace information storage unit 7 uses the output of the trace collection instruction unit 6 as a write instruction, and stores the internal information 100 when a debug interrupt occurs with the value of the trace information storage pointer 4 as a write address.

FIG. 6 is a diagram showing a process of storing the internal information 100 in the main storage unit 3 and the trace information storage unit 7 of FIG. 5 when a debug interrupt occurs. In the figure, the internal states of the main storage unit 3 and the trace information storage unit 7 when the debug interrupt generation unit 1 generates a debug interrupt for each instruction are shown in order from state 1 to state 6. Here, the trace collection flag 5 is valid before the instructions A and C are executed, and is invalid before the instruction B is executed.

A storage operation of the internal information 100 according to another embodiment of the present invention will be described below with reference to FIGS. 5 and 6.

First, in state 1, the IC shows the state before the instruction A, and shows the state immediately before the execution of the instruction A. When the debug interrupt generating unit 1 generates a debug interrupt after the instruction A is executed in this state, the IC position moves to the interrupt processing position.

At this time, the stack pointer 2 is decremented and the internal information A'after execution of the instruction A is stored in the position of SP. In this case, since the trace collection flag 5 is valid, the trace collection instruction unit 6 outputs the interrupt instruction from the debug interrupt generation unit 1 to the write instruction of the trace information storage unit 7. Therefore, the internal information A ′ after execution of the instruction A is stored in the position TP of the trace information storage unit 7 and the trace information storage pointer 4 is incremented (see state 2 in FIG. 6).

Next, when returning to the original program by the interrupt processing end instruction 101, the instruction A is given to the inside of the information processing apparatus based on the internal information A'stored in the SP position of state 2.
Set to the state after execution.

At this time, the value of IC is set to the position after the execution of the instruction A, the stack pointer 2 is incremented, and the position of SP returns to the position before the occurrence of the debug interrupt. However, when returning to the original program from the interrupt processing, the position of TP is not updated (see state 3 in FIG. 6).

After that, when the debug interrupt generator 1 generates a debug interrupt after the instruction B is executed, the IC position moves to the interrupt processing position. At this time, the stack pointer 2 is decremented and the internal information B ′ after the execution of the instruction B is stored at the SP position.

On the other hand, in this case, since the trace collection flag 5 is invalid, the trace collection instruction unit 6
Suppresses outputting the interrupt instruction from the debug interrupt generating section 1 to the write instruction of the trace information storage section 7. Therefore, the internal information B ′ after execution of the instruction B is not stored in the position TP of the trace information storage unit 7, and the trace information storage pointer 4 is not incremented (see state 4 in FIG. 6).

When returning to the original program by the interrupt processing end instruction 101, the inside of the information processing apparatus is set to the state after the execution of the instruction B based on the internal information B ′ stored in the SP position of the state 2. At this time, the value of IC is set to the position after the execution of the instruction B, the stack pointer 2 is incremented, and the position of SP returns to the position before the occurrence of the debug interrupt (see state 5 in FIG. 6).

Subsequently, when the debug interrupt generator 1 generates a debug interrupt after the instruction C is executed, the IC position moves to the interrupt processing position. At this time, the stack pointer 2 is decremented and the internal information C ′ after the execution of the instruction C is stored in the position of SP.

In this case, since the trace collection flag 5 is valid, the trace collection instruction unit 6 outputs the interrupt instruction from the debug interrupt generation unit 1 to the write instruction of the trace information storage unit 7. Therefore, the internal information C ′ after execution of the instruction C is stored in the position of TP of the trace information storage unit 7 and the trace information storage pointer 4 is incremented (see state 6 in FIG. 6).

At the position designated by SP in this state 6, the internal information C ′ after execution of the instruction C is overwritten in the area where the internal information B ′ after execution of the instruction B is stored. On the other hand, at the position indicated by TP in the trace information storage unit 7, the trace information storage pointer 4 indicates the interrupt processing end instruction 1
01 is not updated, and the trace collection flag 5 is invalid before the instruction B is executed. Therefore, the internal information C ′ after the execution of the instruction C is stored next to the internal information A ′ after the execution of the instruction A two instructions before at the position indicated by TP in the trace information storage unit 7.

As described above, since the main storage unit 3 and the trace information storage unit 7 can be operated completely independently, the storage of internal information should be performed in parallel in the main storage unit 3 and the trace information storage unit 7. You can

Therefore, when viewed from the main storage unit 3, the storage condition of the internal information becomes equal when the trace information is collected and when the trace information is not collected. This means that it is possible to prevent the performance deterioration due to the increase in the writing amount of the internal information due to the collection of the trace information.

Therefore, by providing the trace information storage unit 7, it is possible to prevent the performance degradation of the debug interrupt processing when executing the debug interrupt processing at the time of collecting the trace information.

As described above, when the debug interrupt occurs, the internal information A ', B', and C'stored in the main storage unit 3 designated by the stack pointer 2 is sequentially designated by the trace information storage pointer 4 or by the main storage unit 3. By storing the trace information in the trace information storage unit 7, it is possible to reduce the performance degradation of the debug interrupt processing as compared with the case where the trace information is collected by the software for the debug interrupt processing.

Further, by providing the trace collection flag 5 and the trace collection instruction section 6, it is possible to suppress the writing of the internal information to the area designated by the trace information storage pointer 4 when the trace information is unnecessary. It is possible to suppress the performance degradation of the debug interrupt processing due to the writing of the internal information to the area.

Furthermore, by providing the trace information storage unit 7 dedicated to collecting trace information, it is possible to collect trace information without degrading the performance of debug interrupt processing.

[0084]

As described above, according to the present invention, the storage area for storing the internal state of the apparatus is provided outside the area on the main memory designated by the stack pointer and is sequentially generated in response to the debug interrupt. By storing the internal state of the device in the area designated by the address, it is possible to reduce the performance degradation of the debug interrupt processing as compared with the case where the trace information is collected by the software for the debug interrupt processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a process of storing internal information in the main memory unit of FIG. 1 when a debug interrupt occurs.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 4 is a diagram showing a process of storing internal information in the main storage unit of FIG. 3 when a debug interrupt occurs.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention.

6 is a diagram showing a process of storing internal information when a debug interrupt occurs in the main storage unit and the trace information storage unit of FIG. 5;

FIG. 7 is a block diagram showing a configuration of a conventional example.

8 is a diagram showing a process of storing internal information in the main storage unit of FIG. 7 when a debug interrupt occurs.

[Explanation of symbols]

 1 debug interrupt generation unit 2 stack pointer 3 main storage unit 4 trace information storage pointer 5 trace collection flag 6 trace collection instruction unit 7 trace information storage unit A, B, C instructions A ', B', C'internal information

Claims (3)

[Claims] 1. The internal state at the time of a debug interrupt is stored by using the function of storing the internal state of the device in the main memory designated by the stack pointer in response to the interrupt at the time of an interrupt according to the operation of software. A debug interrupt processing device, which is provided outside the area on the main memory designated by the stack pointer and stores the internal state, and sequentially generates addresses of the storage area in response to the debug interrupt. And a means for storing the internal states in the main memory area and the storage area in response to the debug interrupt, respectively. 2. A means for holding information indicating whether or not to store the internal state in the storage area when the debug interrupt occurs, and suppressing storage of the internal state in the storage area according to the information. The debug interrupt processing device according to claim 1, further comprising: 3. The debug interrupt processing device according to claim 1, wherein the storage area is provided in a storage device other than the main memory.