JPS5580163A - Calculation unit for appreciation of computer system - Google Patents

Calculation unit for appreciation of computer system

Info

Publication number
JPS5580163A
JPS5580163A JP15384978A JP15384978A JPS5580163A JP S5580163 A JPS5580163 A JP S5580163A JP 15384978 A JP15384978 A JP 15384978A JP 15384978 A JP15384978 A JP 15384978A JP S5580163 A JPS5580163 A JP S5580163A
Authority
JP
Japan
Prior art keywords
software
computer
appreciation
memory
counter group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15384978A
Other languages
Japanese (ja)
Inventor
Katsumi Muraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15384978A priority Critical patent/JPS5580163A/en
Publication of JPS5580163A publication Critical patent/JPS5580163A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To improve effectively software performance by measuring the operation of software in a computer without logic addition to software and using this data.
CONSTITUTION: Operation unit 3 and main memory 1 are provided in computer A, and various instructions designated by addresses and data of instructions are stored in memory 1. Counter unit B provided with counter group 2 which counts read or write frequency of addresses from memory 1 is connected to this computer A. Then, states of read/write signal 5 and address signal 4 are discriminated without interfering with execution of software by counter group 2, and use frequency of any instruction at any address is measured by the measured value in counter group 2, and appreciation of computer A is performed to improve performance of software.
COPYRIGHT: (C)1980,JPO&Japio
JP15384978A 1978-12-13 1978-12-13 Calculation unit for appreciation of computer system Pending JPS5580163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15384978A JPS5580163A (en) 1978-12-13 1978-12-13 Calculation unit for appreciation of computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15384978A JPS5580163A (en) 1978-12-13 1978-12-13 Calculation unit for appreciation of computer system

Publications (1)

Publication Number Publication Date
JPS5580163A true JPS5580163A (en) 1980-06-17

Family

ID=15571437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15384978A Pending JPS5580163A (en) 1978-12-13 1978-12-13 Calculation unit for appreciation of computer system

Country Status (1)

Country Link
JP (1) JPS5580163A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59148962A (en) * 1983-02-14 1984-08-25 Hitachi Denshi Ltd Monitoring device of memory data
JPS61112253A (en) * 1984-10-12 1986-05-30 Fujitsu Ltd Analyzer for performance of electronic computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59148962A (en) * 1983-02-14 1984-08-25 Hitachi Denshi Ltd Monitoring device of memory data
JPS61112253A (en) * 1984-10-12 1986-05-30 Fujitsu Ltd Analyzer for performance of electronic computer

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