JPS5454545A - Register readout system - Google Patents

Register readout system

Info

Publication number
JPS5454545A
JPS5454545A JP12115277A JP12115277A JPS5454545A JP S5454545 A JPS5454545 A JP S5454545A JP 12115277 A JP12115277 A JP 12115277A JP 12115277 A JP12115277 A JP 12115277A JP S5454545 A JPS5454545 A JP S5454545A
Authority
JP
Japan
Prior art keywords
register
logical
output
address
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12115277A
Other languages
Japanese (ja)
Inventor
Akio Niimura
Hisashi Nishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
YUUZATSUKU DENSHI KOUGIYOU KK
Fujitsu Ltd
Usac Electronic Ind Co Ltd
Original Assignee
YUUZATSUKU DENSHI KOUGIYOU KK
Fujitsu Ltd
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by YUUZATSUKU DENSHI KOUGIYOU KK, Fujitsu Ltd, Usac Electronic Ind Co Ltd filed Critical YUUZATSUKU DENSHI KOUGIYOU KK
Priority to JP12115277A priority Critical patent/JPS5454545A/en
Publication of JPS5454545A publication Critical patent/JPS5454545A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To shorten the time required for production of the operand address, by constituting the readout output of register to a specific value, when the specific bit of instruction has a given value.
CONSTITUTION: The all zero described in the B and X field of the macroinstruction 50 represents the disuse of the field corresponded, then the logical 1 is written in the specific bit P of the microinstruction stored in the microinstruction storing register 8. When the entried values B and X are read out from the address designation register 1, the zero discriminating circuit 2 outputs logical 1 to the signal line 4, and AND circuit 10 outputs 11 entirely logical 0. Further, the bit P is logical 0, then the output 7 of the conventional register 9 designated with the address information line 3 is appeared at the output line 11 as it is. Thus, when the register 9 is designated with the values B, X, the displacement D is added to the value obtained from the output 11, then the operand address is developed. Further, the time required for the production can be shortened
COPYRIGHT: (C)1979,JPO&Japio
JP12115277A 1977-10-08 1977-10-08 Register readout system Pending JPS5454545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12115277A JPS5454545A (en) 1977-10-08 1977-10-08 Register readout system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12115277A JPS5454545A (en) 1977-10-08 1977-10-08 Register readout system

Publications (1)

Publication Number Publication Date
JPS5454545A true JPS5454545A (en) 1979-04-28

Family

ID=14804125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12115277A Pending JPS5454545A (en) 1977-10-08 1977-10-08 Register readout system

Country Status (1)

Country Link
JP (1) JPS5454545A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114246A (en) * 1981-12-28 1983-07-07 Fujitsu Ltd Address qualifying system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114246A (en) * 1981-12-28 1983-07-07 Fujitsu Ltd Address qualifying system

Similar Documents

Publication Publication Date Title
JPS55154635A (en) Data processor
JPS5454545A (en) Register readout system
JPS5487130A (en) Conventional register access system
JPS54109728A (en) Memory device
JPS5423343A (en) Microprogram controller
JPS5247329A (en) Data processing unit
JPS5510673A (en) Microprogram control data processor
JPS5687142A (en) Sequence control system for rom address
JPS5467179A (en) Control system
JPS55134450A (en) Microprogram control unit
JPS5244535A (en) Information processing equipment
JPS5580163A (en) Calculation unit for appreciation of computer system
JPS5687153A (en) Controller for auxiliary memory
JPS5599652A (en) Microprogram control unit
JPS55157064A (en) Word memory system
JPS556650A (en) Control-memory access system with writing function
JPS5585965A (en) Microprogram branch system
JPS554668A (en) Computer
JPS522332A (en) Indication control system
JPS5543680A (en) Address designation system
JPS5614357A (en) Diagnostic control unit
JPS5532281A (en) Data write-in method to magnetic card
JPS5552986A (en) Calendar information calculating system
JPS5561852A (en) Microprogram control unit
JPS52103936A (en) Multiple data group read circuit