JPS5588123A - Channel control system - Google Patents
Channel control systemInfo
- Publication number
- JPS5588123A JPS5588123A JP15997178A JP15997178A JPS5588123A JP S5588123 A JPS5588123 A JP S5588123A JP 15997178 A JP15997178 A JP 15997178A JP 15997178 A JP15997178 A JP 15997178A JP S5588123 A JPS5588123 A JP S5588123A
- Authority
- JP
- Japan
- Prior art keywords
- unit
- control information
- channel instruction
- instruction
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To reduce software by setting control information to control registers of several input-output controller by a single channel instruction of CPU.
CONSTITUTION: By an instruction from CPU10, some of channel instruction words in main memory unit 11 are transferred as control information to input-output controller 13. In this case, an indication signal is provided in a specific area of channel instruction words in unit 11 and after control information is completely set in unit 13, the contents of the indication signal is checked. According to the check result, a following channel instruction word is directly extracted from unit 11 and an information instruction word is set to assigned unit 13. Consequently, control information can be set to control registers of several units 13 by a single channel instruction of CPU, thereby reducing software.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15997178A JPS5588123A (en) | 1978-12-27 | 1978-12-27 | Channel control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15997178A JPS5588123A (en) | 1978-12-27 | 1978-12-27 | Channel control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5588123A true JPS5588123A (en) | 1980-07-03 |
JPS6113617B2 JPS6113617B2 (en) | 1986-04-14 |
Family
ID=15705163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15997178A Granted JPS5588123A (en) | 1978-12-27 | 1978-12-27 | Channel control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5588123A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60101660A (en) * | 1983-11-08 | 1985-06-05 | Usac Electronics Ind Co Ltd | Input/output controlling system |
-
1978
- 1978-12-27 JP JP15997178A patent/JPS5588123A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60101660A (en) * | 1983-11-08 | 1985-06-05 | Usac Electronics Ind Co Ltd | Input/output controlling system |
JPH0219498B2 (en) * | 1983-11-08 | 1990-05-02 | Pfu Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS6113617B2 (en) | 1986-04-14 |
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