JPS57204935A - Dynamic address conversion system for channel device - Google Patents

Dynamic address conversion system for channel device

Info

Publication number
JPS57204935A
JPS57204935A JP56090619A JP9061981A JPS57204935A JP S57204935 A JPS57204935 A JP S57204935A JP 56090619 A JP56090619 A JP 56090619A JP 9061981 A JP9061981 A JP 9061981A JP S57204935 A JPS57204935 A JP S57204935A
Authority
JP
Japan
Prior art keywords
cpu
main storage
address
address conversion
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56090619A
Other languages
Japanese (ja)
Inventor
Seiichi Shimizu
Masao Koyabu
Kazumi Yotsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56090619A priority Critical patent/JPS57204935A/en
Publication of JPS57204935A publication Critical patent/JPS57204935A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To execute a series of processings as one operation to shorten the execution time, by executing the channel dynamic address conversion and using the actual address of the execution result to access a main storage. CONSTITUTION:The request signal from a channel device CHP to a CPU or a main storage controller SCU is defined as a request signal RQ for the access to a main storage after dynamic address conversion; and when the signal RQ is received in the CPU, the first selecting signal SEL is returned to the device CHP of the request source, and a logical address and control information are given to the CPU through an address bus AB. The CPU converts the logical address to an actual address by the dynamic address conversion function and enters into the access to the main storage. When the CPU reads out data 1 and 2 from the main storage, the CPU transmits the next selecting signal SEL to the device CHP and writes the actual address and data 1 and 2 through a data bus DB. Thus, a series of processings is executed as one operation to shorten the execution time.
JP56090619A 1981-06-12 1981-06-12 Dynamic address conversion system for channel device Pending JPS57204935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56090619A JPS57204935A (en) 1981-06-12 1981-06-12 Dynamic address conversion system for channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56090619A JPS57204935A (en) 1981-06-12 1981-06-12 Dynamic address conversion system for channel device

Publications (1)

Publication Number Publication Date
JPS57204935A true JPS57204935A (en) 1982-12-15

Family

ID=14003498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56090619A Pending JPS57204935A (en) 1981-06-12 1981-06-12 Dynamic address conversion system for channel device

Country Status (1)

Country Link
JP (1) JPS57204935A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173828A (en) * 1983-03-23 1984-10-02 Nec Corp Data processing system
JP2015130133A (en) * 2014-01-09 2015-07-16 日本電気株式会社 Input-output processing apparatus, input-output processing method, and input-output processing program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59173828A (en) * 1983-03-23 1984-10-02 Nec Corp Data processing system
JP2015130133A (en) * 2014-01-09 2015-07-16 日本電気株式会社 Input-output processing apparatus, input-output processing method, and input-output processing program

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