JPS5463635A - Processing system for data buffer area management - Google Patents

Processing system for data buffer area management

Info

Publication number
JPS5463635A
JPS5463635A JP12949377A JP12949377A JPS5463635A JP S5463635 A JPS5463635 A JP S5463635A JP 12949377 A JP12949377 A JP 12949377A JP 12949377 A JP12949377 A JP 12949377A JP S5463635 A JPS5463635 A JP S5463635A
Authority
JP
Japan
Prior art keywords
data buffer
main memory
area
unit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12949377A
Other languages
Japanese (ja)
Other versions
JPS5841527B2 (en
Inventor
Tomohito Shibata
Noboru Yamamoto
Kazuo Shimomichi
Kanzo Noda
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52129493A priority Critical patent/JPS5841527B2/en
Publication of JPS5463635A publication Critical patent/JPS5463635A/en
Publication of JPS5841527B2 publication Critical patent/JPS5841527B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To improve system processing efficiency by performing the management of the whole of the memory area on the main memory by CPU and performing the management of use conditions by indicating the area, which can be used as a data buffer area, to channel units from CPU.
CONSTITUTION: In the data processing system where CPUl, main memory 2, channel unit 4 and one or plural sub-channel units 5-0 to 5-n connected to unit 4 are provided and unit 4 transmits and receives data by the direct memory access for the data buffer area prepared on main memory 2, unit 4 is provided with data buffer stack area 14 which stores address information of data buffer areas 16-0, 16-1... on main memory 2. Furthr, microprocessor 6, control memory 7 and common bus interface part 9 which manage buffer areas 16-0, 16-1... existing on main memory 2 are provided to manage the use conditions of buffer areas 16-0, 16-1... by the instruction of CPU1.
COPYRIGHT: (C)1979,JPO&Japio
JP52129493A 1977-10-28 1977-10-28 Data buffer area management processing method Expired JPS5841527B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52129493A JPS5841527B2 (en) 1977-10-28 1977-10-28 Data buffer area management processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52129493A JPS5841527B2 (en) 1977-10-28 1977-10-28 Data buffer area management processing method

Publications (2)

Publication Number Publication Date
JPS5463635A true JPS5463635A (en) 1979-05-22
JPS5841527B2 JPS5841527B2 (en) 1983-09-13

Family

ID=15010833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52129493A Expired JPS5841527B2 (en) 1977-10-28 1977-10-28 Data buffer area management processing method

Country Status (1)

Country Link
JP (1) JPS5841527B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3949742A4 (en) 2019-03-28 2022-12-07 Morinaga Milk Industry Co., Ltd. Heat-resistant bacterium composition

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177102A (en) * 1974-12-27 1976-07-03 Nippon Electric Co
JPS545637A (en) * 1977-06-15 1979-01-17 Hitachi Ltd Communication control unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177102A (en) * 1974-12-27 1976-07-03 Nippon Electric Co
JPS545637A (en) * 1977-06-15 1979-01-17 Hitachi Ltd Communication control unit

Also Published As

Publication number Publication date
JPS5841527B2 (en) 1983-09-13

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