JPS5585941A - Dma system for data transmission and reception unit - Google Patents

Dma system for data transmission and reception unit

Info

Publication number
JPS5585941A
JPS5585941A JP15952778A JP15952778A JPS5585941A JP S5585941 A JPS5585941 A JP S5585941A JP 15952778 A JP15952778 A JP 15952778A JP 15952778 A JP15952778 A JP 15952778A JP S5585941 A JPS5585941 A JP S5585941A
Authority
JP
Japan
Prior art keywords
selection circuit
dmac
reception
data
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15952778A
Other languages
Japanese (ja)
Inventor
Tamio Ito
Yoshihiro Yoshioka
Shigehiko Matsushita
Yukio Kirihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15952778A priority Critical patent/JPS5585941A/en
Publication of JPS5585941A publication Critical patent/JPS5585941A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to control the data transmission and reception easily and efficiently, by selecting a plurality of direct memory access controllers for exclusive use of transmission and reception with the selection circuit every data frame of HDLC procedure.
CONSTITUTION: The bus 9 is connected to the processor MPU1 controlling the entire system and each block constitution as well as the memory MM2 is connected to the bus 9. At the transmission side, the selection circuit SSW5 selects the direct memory access controller DMAC every data block and alternately uses S#1DMAC3 and S#2DMAC4. At the reception side, the selection circuit RSW8 selects DMAC every data frame and alternately uses R#1DMAC6 and R#2DMAC7. As the data line is in high speed, it can be sufficiently applied by adding DMAC.
COPYRIGHT: (C)1980,JPO&Japio
JP15952778A 1978-12-21 1978-12-21 Dma system for data transmission and reception unit Pending JPS5585941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15952778A JPS5585941A (en) 1978-12-21 1978-12-21 Dma system for data transmission and reception unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15952778A JPS5585941A (en) 1978-12-21 1978-12-21 Dma system for data transmission and reception unit

Publications (1)

Publication Number Publication Date
JPS5585941A true JPS5585941A (en) 1980-06-28

Family

ID=15695708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15952778A Pending JPS5585941A (en) 1978-12-21 1978-12-21 Dma system for data transmission and reception unit

Country Status (1)

Country Link
JP (1) JPS5585941A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114629A (en) * 1982-12-21 1984-07-02 Nec Corp Chain data controlling system
JPS61271556A (en) * 1985-05-28 1986-12-01 Oki Electric Ind Co Ltd Direct memory access system
JPS62274955A (en) * 1986-05-23 1987-11-28 Oki Electric Ind Co Ltd Hdlc line control system
JP2000315186A (en) * 1999-05-06 2000-11-14 Hitachi Ltd Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114629A (en) * 1982-12-21 1984-07-02 Nec Corp Chain data controlling system
JPS61271556A (en) * 1985-05-28 1986-12-01 Oki Electric Ind Co Ltd Direct memory access system
JPS62274955A (en) * 1986-05-23 1987-11-28 Oki Electric Ind Co Ltd Hdlc line control system
JP2000315186A (en) * 1999-05-06 2000-11-14 Hitachi Ltd Semiconductor device

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