JPS62274955A - Hdlc line control system - Google Patents

Abstract

PURPOSE:To reduce the burden of a main processor and attain a small scale hardware constitution by switching two DMA (direct memory access) control circuits alternately for each frame to transfer continuously sent reception data. CONSTITUTION:After assembling reception data to character units, a high level data link (HDLC) receiving circuit 1 sends a DMA transfer request signal s1 and reception data D to a reception waiting circuit, for example, a control circuit 5 out of DMA control circuits 5 and 6 through a switching circuit 3. Data D is transferred to a memory 8 through the control circuit 5. When a detecting circuit 2 detects an end flag pattern in reception data to output a signal s2 or a signal s3 indicating the completion of data transfer of transfer bytes whose number is set to the control circuit 5 is outputted, a switching control circuit 4 sends a switching signal s6 to the switching circuit 3 to send the signal s1 and data D to the control circuit 6 and switches operation states of control circuits 5 and 6. While the switched control circuit 6 per forms the transfer operation, a main processor 7 sets trans fer instruction information of the transfer address and the number of transfer bytes of following reception data to the control circuit 5.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention provides high-level data link control (1-1DLC
) This relates to a reception control method that controls the line.

(Prior art) Conventionally, when controlling the transmission and reception operations of a high-speed DLC line, a high-speed processor was used as a dedicated processor for line control and was placed separately from the main processors. The HDLG receiving circuit and direct memory access (D
MA) Between the control circuit or +1D LC reception line and H
A multi-stage buffer circuit for temporarily storing received data was provided between the DLC receiving circuit and the received data to prevent collision.

(Problem to be Solved by the Invention) However, in the above configuration, the built-in processor of the main processor []
The problem was that not only did the amount of RAM become enormous, which increased the burden, but also the hardware configuration became complex and the amount of hardware increased.

The present invention eliminates the above-mentioned problems and provides a method for controlling multiple high-speed HDl-C lines. Minimize the burden on the handle as much as possible, and use a small-scale hardware configuration with no 1q
The purpose of this invention is to provide a control method for an l-I DLC line.

(Means for Solving the Problems) The present invention solves the above-mentioned problems.
In the L-C line control system, two DMA control circuits are arranged in parallel between the receiving circuit and the memory, means for detecting an end flag pattern from received data, and when the end flag pattern is detected, Or, when receiving a processing completion signal from the DMA control circuit, the operating DMA control circuit is disabled and the received data etc. are transferred to the other DM.
Means for switching to the A control circuit and transmitting
Set new transfer instruction information for the 1MA control circuit,
A means for making this operational is provided.

(Function) According to the present invention, received data is transferred to the memory via one of the DMA control circuits, and during this time, transfer instruction information such as transfer numbers related to the data of the next frame is transferred. is set in the other DMA control circuit, and when the end flag pattern of one frame of data is detected, or when the transfer of the transfer pie 1 to number set in the one DMA control circuit is completed, the other l) M The control circuit is switched to the A control circuit, and data transfer for the next frame is performed.

(Example) Figure 1 shows an example of the method of the present invention.
is l-I DLC receiving circuit, 2 is l-I D L
C end flag detection circuit; 3 is a DMA transfer request switching circuit;
4 is a switching control circuit, 5.6 is a DMA control circuit, 7 is a main processor υ, 8 is a memory, 9 is a 1-IDLC receiving line, and 10 is a bus.

In addition, Fig. 2 shows the l-I DLC receiving line 9 ().
5. Receive data and DMA 11160 circuit.
The timing with operation 6 is shown below.

)-I D I-C receiving circuit 1 is l-I D I-C
The data received on the receiving line 9 is assembled into characters (8 bits), and after the assembly is completed, l') M△ transfer request signal @S1
I') is sent to the MA transfer request switching circuit 3, and further the assembled received data 1] is sent out.

1” DIc end flag detection circuit 2 is 1-1D L C
The end flag pattern in the received data of the receiving line 9 is detected and a detection signal S2 is output to the switching control circuit 4.

The DMA transfer request switching circuit 3 sends the DMA transfer request signal S1 and the received data D from the HDIC receiving circuit 1 to either one of the DMA control circuits 5 and 6 under the control of the switching control circuit 4.

The switching control circuit 4 receives the detection signal S2, the DMA processing completion signal S3□64 from the DMA control circuits 5 and 6, and the DMA operation prohibition release command $5 from the main processor 7, and requests l) M A transfer request. Switching signal S to switching circuit 3
6 and instructs the DMA control circuits 5 and 6 to prohibit their operations. Send s8.

Only one of the DMA Will Till 1 circuits 5 and 6 operates at a time to control data transfer between the 1-I DLC receiving circuit 1 and the memory 8. The DM
The A1II11 control circuit 5.6 sends a DMA processing completion signal @ when the data transfer processing for one frame set in advance is completed.
Output S3°S4.

The main processor 7 sends transfer instruction information such as a transfer address and the number of bytes to be transferred to the DMA control circuits 5 and 6, and
It manages the procedures of the LC line 9, controls the HDLC receiving circuit 1, etc., and also controls the DMA control circuits 5 and 6.
Cancel the operation prohibition of J゛ruDM△Operation prohibition release command S
5 to the switching control circuit 4. Note that here, since the number of transferred bytes of received data cannot be known in advance, the maximum value is set.

The memory 8 stores received data D received by the 1'' DLC receiving circuit 1 and assembled.

Next, the operation will be explained.

The received data is 1 from l-I DLC reception line 9.
- IDL C reception circuit 1 takes in the character unit (8bit
t). When the assembly is completed, the HDL
The C receiving circuit 1, via the DMA transfer request switching circuit 3,
A DMA transfer request signal S1 is sent to a circuit waiting for reception among the DMA control circuits 5 and 6, for example, the DMA control circuit 5, and further the received data 1] is sent out. The received data D is transferred to the memory 8 via I) the MA control circuit 5; Thereafter, similar processing is continued for one predetermined frame.

Next, the l-I DLC end flag detection circuit 2 detects the end flag pattern in the received data on the HD LC reception line 9, and outputs the end flag detection signal S2, or the DMA control circuit 5 DMA processing completion signal S indicating that data transfer of the number of transfer bytes set in
3 is output, the switching control circuit 4 sends the switching signal S6 to the DMA transfer request switching circuit 3, and the DMA transfer request signal S1. The DMA transfer request switching circuit 3 is switched to send the received data D to the DMA control circuit 6, and the DMA
Switch the operating state of the A control circuit 5.6.

Here, the number of bytes of actual received data is DMA mi
If it is smaller than the value set in the control circuit 5, the end flag detection signal S2 is output before the DMA processing completion signal S3.

Since transfer instruction information has been sent to the DMA control circuit 6 in advance during operation of the DMA control circuit 5, the same data transfer as described above is immediately started from the next received data. In addition, the DMA control circuit 5 that has been operating until now
The operation is prohibited by the DMA operation prohibition control signal 87.

Furthermore, during the transfer operation of the switched DMA control circuit 6,
The main processor 7G sends the next received data transfer address, transfer instruction information such as the number of transfer bytes, etc. to DMA l1ill 1
Set to 10 circuits 5.

When this setting is completed, the main processor 7 sends a DMA operation prohibition release command S5, cancels the DMA operation inhibition state of the DMA control circuit 5, and prepares for the next data reception operation.

In this way, the M A control circuits 5.6 are operated alternately, and while one DMA control circuit is in operation, a new transfer instruction is issued to the other DMA control circuit.
Reception operations can be performed continuously.

(Effects of the Invention) As explained above, according to the present invention, continuously transmitted received data is transferred by switching the two DMA control circuits to alternating current for each frame. The processor can send out transfer instruction information by accessing a DMA control circuit that is not performing a transfer operation, that is, it has time to spare, and therefore the processing speed of the main processor itself does not have to be very high. , a processor with low processing power can be used, a buffer circuit is not required, and it can be configured with less hardware.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the HDLC line control method of the present invention, and FIG. 2 is an explanatory diagram showing the timing of received data on the HDLC receiving line and the operation of the DMA control circuit. DESCRIPTION OF SYMBOLS 1... HD LC reception circuit, 2... End flag detection circuit, 3... DMA transfer request switching circuit, 4... Switching side control circuit, 5.6... DMA III m circuit , 7... Main processor, 8... Memory, 9... l
-IDLC reception line. Patent applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] In an HDLC line control system that receives data signals sent sequentially via a high-level data link control (HDLC) line, there is a direct memory access (HDLC) system in which two direct memory access circuits are arranged in parallel between the receiving circuit and the memory. a DMA) control circuit; a means for detecting an end flag pattern from received data; and when detecting the end flag pattern or receiving a processing completion signal from the DMA control circuit, operating a DMA control circuit that is currently in operation. means for setting the DMA control circuit in a prohibited state and switching the received data etc. to the other DMA control circuit and transmitting it; and means for setting new transfer instruction information to the DMA control circuit that is not in operation to enable it. An HDLC line control method characterized by the provision of.