JPH0496852A - Buffer memory connection control circuit - Google Patents

Abstract

PURPOSE:To eliminate a need to confirm the validity of transfer data after expansion and to shorten the time required for data expansion by providing a transfer data preparation buffer memory besides a transfer buffer memory and substituting the transfer buffer memory and the transfer data preparation buffer memory. CONSTITUTION:A central processing unit 1 sends a buffer memory connection control indication to a buffer memory group substitution indicating circuit 6 through an internal bus 2 to exclusively substitute buffer memory select signals to be given to transfer data preparation buffer memories (1) 4-1 and (2) 4-2 and transfer buffer memories (1) 5-1 and (2) 5-2 by a transfer data preparation buffer memory switching discrimination circuit 7 and a transfer buffer memory switching discrimination circuit 8. Thus, address mapping of transfer data preparation buffer memories (1) 4-1 and (2) 4-2 and transfer buffer memories (1) 5-1 and (2) 5-2 is switched to switch the connection state of buffer memories.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a buffer memory connection control circuit, in particular, a transfer data preparation buffer memory is provided in addition to the transfer buffer memory, and the transfer buffer memory and the transfer data preparation buffer memory are replaced. The present invention relates to a control circuit that eliminates the need for data transfer between buffer memories.

[Conventional technology]

Conventionally, this type of data transfer method between buffer memories is
The control system used a microprogram to exchange transfer data between the transfer data preparation buffer memory area and the transfer buffer memory area.

[Problem to be solved by the invention]

In the case of data transfer from the central processing unit to the external interface control unit, the conventional technology described above sets the transfer data in the transfer data preparation buffer memory under the control of a microprogram, and then develops the transfer data in the transfer buffer memory. do. Furthermore, in the case of data transfer from the external interface control unit to the central processing unit, the transfer data is expanded from the transfer buffer memory to the transfer data preparation buffer memory under the control of the microprogram. Therefore, it is necessary to confirm whether the transferred data is correctly expanded into the buffer memory, and it also has the disadvantage that it takes a lot of time to expand the transferred data into the buffer memory using a microprogram. be.

[Means to solve the problem]

The buffer memory connection control circuit of the present invention includes a transfer buffer memory for an external interface control unit divided into a large group of RAM memories whose addresses are mapped continuously, a transfer data preparation buffer memory for a central processing unit, A transfer buffer memory selection circuit that generates a selection signal for the transfer buffer/sofa memory from address information sent from the central processing unit, and a transfer data preparation buffer that generates a selection signal for the transfer data preparation buffer from address information sent from the central processing unit. a memory selection circuit;
A buffer memory group exchange instruction circuit instructs to exchange the transfer buffer memory and transfer data preparation buffer memory according to an instruction from the central processing unit, and a buffer memory group exchange instruction circuit that instructs the transfer data preparation buffer memory and transfer data preparation buffer memory to be exchanged according to an instruction signal from the buffer memory group exchange instruction circuit. A transfer buffer memory selection judgment circuit that determines which memory selection signal to be given to the transfer buffer memory to be replaced, the transfer buffer memory selection circuit or the transfer data preparation buffer memory selection circuit, and the buffer memory group replacement. Depending on the instruction signal of the instruction circuit, which memory selection signal to be applied to the transfer data preparation buffer memory to be replaced with the transfer buffer memory is determined by the transfer buffer memory selection circuit or the transfer data preparation buffer memory selection circuit. and a transfer data preparation buffer memory division determination circuit for dividing the transfer data preparation buffer memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a process diagram showing an embodiment of the present invention, and Fig. 2 is a memory mapping showing the memory configuration state before/after execution of buffer memory switching by the buffer memory connection control circuit shown in Fig. 1. It is a diagram.

The transfer data preparation buffer memory (1) 4-1 and the transfer data preparation buffer memory (2) 4-2 are controlled by the central processing unit 1 via the external interface control unit 3 when transmitting and receiving transfer data with an external device. As a preparation buffer memory for the transfer data to be transferred, there are buffer memories whose addresses are mapped consecutively.Transfer buffer memory (1) 5-1, transfer buffer memory (2) 5-2
In order to send and receive transfer data to and from an external device via the external interface control unit 3, the transfer data preparation buffer memory (1) l-1, transfer data preparation buffer memory (2) l-2 are exclusive. This is a buffer memory whose addresses are mapped continuously.

When the central processing unit 1 accesses the transfer data preparation buffer memory (1) 4-1 and transfer data preparation buffer memory (2) 4-2 via the internal bus 2, the transfer data preparation buffer memory (1) 4 The transfer data preparation buffer memory selection circuit 9 selects and determines which of the transfer data preparation buffer memory (2) l-1 and transfer data preparation buffer memory (2) l-2 is to be accessed from the address information.

Similarly, transfer buffer memory (1) 5-1. Transfer buffer memory (
2) In the buffer memory access of 5-2, transfer buffer memory (1) 5-1, transfer buffer memory (2>
The transfer buffer memory selection circuit 10 selects and determines which of 5-2 to access from the address information.

The central processing unit 1 has a transfer data preparation buffer memory (1
) 411, transfer data preparation buffer memory (2) 4-2
When switching buffer memory access to transfer buffer memory (1) 5-1 and transfer buffer memory (2) 5-2, a buffer memory connection control instruction is sent to buffer memory group replacement instruction circuit 6 via internal bus 2.

The buffer memory group replacement instruction circuit 6 is the central processing bag W1.
Based on the instruction, a buffer memory replacement instruction signal is sent to the transfer data preparation bus/sofa memory division determination circuit 7 and the transfer bus/sofa memory division determination circuit 8.

The transfer data preparation buffer memory division determination circuit 7
Transfer data preparation buffer memory (1,) sent from transfer data preparation buffer memory selection circuit 9 4-1
, transfer data preparation buffer memory selection signal to sofa memory (2) 4-2 or transfer buffer memory (1) 5- sent from transfer buffer memory selection circuit 10
1. Transfer Ba-Nfa Memo! The buffer memory selection signal to J(2) 5-2 is switched by the buffer memory replacement instruction signal from the buffer memory group replacement instruction circuit 6, and the transfer data preparation buffer memory (1) 4-1,
Transfer data preparation buffer memory (2>4-2) Sends buffer memory selection signal.

The transfer buffer memory division determination circuit 8 selects the transfer buffer memories (1) 5-1 . A buffer memory selection signal to the transfer buffer memory (2) 5-2 or a transfer data preparation buffer memory (1) sent from the transfer data preparation buffer memory selection circuit 9 to the transfer data preparation buffer memory (1) 4-1, transfer data preparation buffer memory (2) The buffer memory selection signal to transfer buffer memory (1) 5-1 and the transfer buffer memory (2) 52 are switched by the buffer memory exchange instruction signal from the buffer memory group exchange instruction circuit 6. 9 transfer data preparation buffer memory for sending signals (1) 4-1. Transfer data preparation buffer memory (2>4-2 and transfer buffer memory (1) 5-1,
Transfer buffer memory (2) The buffer memory selection signal to be given to 5-2 is transferred to the transfer data preparation buffer memory division judgment port li! 87 and the transfer buffer memory division determination circuit 8, the second
Transfer data preparation buffer memory (1) 4-1 as shown in the diagram
, transfer data preparation buffer memory<2)4. -2 and transfer buffer memory (1) 5-1, transfer buffer memory (2
) It is possible to change the address pin pink in 5-2 and change the connection state of the buffer memory.

〔Effect of the invention〕

As explained above, the present invention eliminates the need to confirm the validity of the transfer data after it is expanded into the buffer memory by switching the connection method between the transfer data preparation buffer memory area and the transfer buffer memory area. At the same time, it has the effect of significantly reducing the time spent on data deployment.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a memory mapping diagram showing the buffer memory configuration state of the buffer memory connection control circuit shown in FIG. 1. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Internal bus, 3...External interface control unit, 4-1...Transfer data preparation buffer memory (1), 4-2...Transfer data preparation buffer memory (2), 5-1... Transfer buffer memory (1), 5-2... Transfer buffer memory (2),
6... Buffer memory group replacement instruction circuit, 7...
Transfer data preparation buffer memory division judgment circuit, 8.
. . . Transfer buffer memory division circuit, 9 . . . Transfer data preparation buffer memory selection circuit, 10 . . . Transfer buffer memory selection circuit.

Claims (1)

[Claims] In an information processing device including an external interface control unit that controls an external device, and a central processing unit that controls the external interface control unit via an internal bus, a large-capacity In the buffer memory connection control circuit for controlling transfer data exchange, a large number of RAs whose addresses are continuously mapped
A transfer buffer memory for an external interface control unit divided in the M memory group, a transfer data preparation buffer memory for the central processing unit, and a selection signal for the transfer buffer memory are generated from address information sent from the central processing unit. a transfer buffer memory selection circuit; a transfer data preparation buffer memory selection circuit that generates a selection signal for the transfer data preparation buffer from address information sent from the central processing unit; a buffer memory group replacement instructing circuit that instructs to replace and exchange the transfer data preparation buffer memory; and a buffer memory group replacement instruction circuit that instructs the transfer data preparation buffer memory to be replaced with the transfer data preparation buffer memory by an instruction signal from the buffer memory group replacement instruction circuit. A transfer buffer memory selection determination circuit that determines which memory selection signal to use, either the transfer buffer memory selection circuit or the transfer data preparation buffer memory selection circuit, and instructions for the buffer memory group replacement instruction circuit. A signal determines which memory selection signal to be applied to the transfer data preparation buffer memory to be replaced with the transfer buffer memory by the transfer buffer memory selection circuit or the transfer data preparation buffer memory selection circuit. 1. A buffer memory connection control circuit comprising a transfer data preparation buffer memory division determination circuit.