JPH03167648A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To extend an input/output device without increasing the number of control signal lines by providing an address storage register, a decoder, and a direct memory access DMA device. CONSTITUTION:A CPU 1 sends the addresses of a memory 2 and an input/output device 3 of the transfer destination to an address storage register 13. At the same time, the CPU 1 sends the information to a counter 10 of a DMA controller 9A and sets the information number to an address counter 11 of the memory 2. The controller 9A actuates a buffer 14 with a command of the CPU 1 to cut off an address bus 6 and transmits the memory read and input/output write signals to transfer the DMA data on the memory 2 and the register 13 to the device 3. A decoder 15 transmits a chip selection signal CS1 to the device 3, and the memory 2 sends the data designated by a bus 6A and the read signal to a data bus 5. Then the device 3 reads the data and updates the counter 10 with both inputs to repetitively subtract the counter 11 down to zero. In such a constitution, the device 3 can be extended without increasing the number of control signal lines.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a direct memory access control device that uses a DMA (direct memory access) controller and transfers data between a memory and an input/output device. be.

[Conventional technology] The configuration of a conventional example will be explained with reference to FIG.

FIG. 3 is a block diagram showing a conventional direct memory access control device disclosed in, for example, Japanese Unexamined Patent Publication No. 1-114960.

In FIG. 3, the conventional direct memory access control device includes a CPU (1), a memory (2), an input/output device (3), an input/output device (4), and these CPUs (1).
, memory (2), data bus (5) connected to input/output devices (3) and (4), CPU (1) and memory (2).
The address bus (6) connected to the CPU and the memory READ/WRITE line (2) connected to the
7) and the input/output READ/WRITE &! connected to the CPU (1), input/output devices (3) and (4). (8) is connected to the CPU (1), input/output devices (3) and (4) via control signal lines, and is connected to the address bus (6), memory READ/WRITE line (7) and input/output READ
The DMA controller (9) connected to the /WRITE line (8>) is also connected.

The DMA controller (9) also has an address bus (6
) connected to counter {10} and this counter (1
counter (11) connected to counter (0) and counter (10
) is connected to a signal generator (12). Next, the operation of the above-mentioned conventional example will be explained.

Data transfer using the DMA controller (9) is performed between the input/output device (3) and the memory 2, or between areas within the memory (2). DMA controller (9
> has a circuit configuration suitable for data transfer, so the CPU (1
) allows for faster data transfer than with the program. When sending data from the input/output device (3) to the memory (2>), set the address of the memory (2) where the data will be written in the first hundred counter (IO) of the DMA controller (9>), and Set the number of transfer data in the counter (11). In this state, when the DMAREQ1 signal requesting DMA operation is input from the input/output device (3), the DMA controller <9> sends the address bus to the CPU (1). (6) outputs a HOLDREQ signal requesting the use of HOLDA.
Returns the CK signal and stops. Then, the DMA controller (9) outputs the DMAACKI signal to the input/output device (3) and enters the DMA data transfer state. Here, the signal generator (12) of the DMA controller (9)
Data is read out from the input/output device (3) onto the data bus (5) by the read signal outputted by the input/output device (3). This data is written to the address of the memory (2>) specified by the counter (11) by the write signal output from the signal generator (12).Synchronized with these read/write signals, the first counter (10) is updated and outputs a new address.The second counter (l1) is also decremented at the same time.When this counter reaches zero, a signal indicating that the set number of data transfers has been completed is output, and the DMA data transfer starts. [Problems to be Solved by the Invention] In the conventional direct memory access control device as described above, when adding memory and input/output devices for data transfer, it is difficult to transmit DMAREQ signals, DMAACK signals, etc. This invention was made to solve the above-mentioned problem, and it is possible to add input/output devices without increasing the number of control signal lines. , it is an object of the present invention to obtain a direct memory access control device that can perform the following:
It is equipped with the means described below. (i). Address storage register that stores the address of the input/output device. (ii). An address decoder that decodes the address output from the address storage register and specifies the input/output device.

(ii). A DMA controller that controls data transfer between the memory and the above input/output device.

[Operation] In this invention, the address storage register allows
The address of the input/output device is stored.

Further, the address output from the address storage register is decoded by the address decoder to designate the input/output device.

The DMA controller controls data transfer between the memory and the input/output device.

[Embodiment] The configuration of an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention, including a CPU (1) to a data path (5), a memory READ/
WRITE line (7) and input/output READ/WRITE &
! (8) is exactly the same as that of the conventional device described above.

In FIG. 1, one embodiment of the present invention has exactly the same components as those of the conventional device described above, a CPU (1), an address bus (6^) connected to a memory (2), and a CPU
(1) via a control signal line, and is connected to the data path (5), address bus (6^), and memory READ/WR.
ITEtl (7) and input/output READ/WRIT
Connect the DMA controller (9^) connected to the E line (8), the address bus (6B) connected to this DMA controller (9^), and the address bus (6^) and the address bus <6B>. Shikatsu DMA controller (9^)
an address decoder (15) whose input side is connected to the address bus (6B) and whose output side is connected to the input/output device (3); and an address decoder (15) whose input side is connected to the address bus (6B). And the output side is an input/output device《
4) and the address decoder (16) connected to the address decoder (16). In addition, the DMA controller (98) has a counter (lO
> and (11), a signal generator (12), and an input/output device address storage register (13).

Next, the operation of the above-mentioned embodiment will be explained. For example, DMA data transfer from the memory (2) to the input/output device (3>) is performed as follows.

From CPU (1) to input/output device address storage register <1
3) to the memory (2) and the address of the output device (3) that transfers DMA data, and also to the DMA controller (9).
Data is transferred to the counter (io) of ^). memory<
Set the address of 2> to the counter (11>) to set the number of data to be transferred.
When the REQ signal is output, the DMA controller (9^>
outputs the DMAACK signal, and the buffer (14> is the DM
When the AACK signal is input, address buses (6^) and (6B) are cut off. The DMA controller (9^) outputs the memory READ signal and the input/output WRITE signal, and also outputs the address hash (6^
), and the address of the input/output device (3), which is the content of the input/output device address storage register (13), is output to the address bus (6B). ), the address decoder (15) outputs a chip select signal CSI to the input/output device (3).The memory (2) is connected to the address bus (6^) and the memory READ.
The data at the address specified by the signal input is output to the data bus (5), and at this time, the input/output device (3>) takes in the data by inputting the chip select signal CSI and the input/output WR ITE signal.

In synchronization with these READ/WRITE signals, the counter (lO) is updated, the counter (11>) is decremented, and the DMA data transfer is repeated until it becomes zero.

One embodiment of the present invention, as described above, includes a memory (2)
By outputting the addresses of the input/output devices (3) and (4) that perform data transfer to the address bus <5>, the input/output devices can be selected, so the input/output devices can be selected without increasing the number of control signal lines. This has the effect that output devices can be added and a highly expandable system can be constructed at low cost.

In the above embodiment, the input/output devices (3) and (4) and the address decoders (15> and <16>) are provided on the same board, but they can be installed on another board via the system bus. Similar operation can be expected even if the address decoder (
It goes without saying that even if 15^) is capable of outputting select signals to all input/output devices, the intended purpose can be achieved.

[Effects of the Invention] As explained above, the present invention includes an address storage register that stores the address of an input/output device, an address decoder that decodes the address output from the address storage register and specifies the input/output device, Since it includes a DMA controller that controls data transfer between the memory and the input/output device, it is possible to add more input/output devices without increasing the number of control signal lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a second embodiment of the invention, and FIG. 3 is a block diagram showing a conventional direct memory access control device. In the figure, 〈]-)... CPLJ, (2)... Memory, (3)... Input/output device, (4>... Input/output device, (5>... Data path, < 6＾), (6B) ... A dress bus, (7
) ... Memory READ/WRITE line, (8)
... Input/output READ/WR ITE line, (9^)
... DMA controller, <10) ... Counter, (11) ... Counter, (12> ... Signal generator, (13) ... I/O device address storage register, (14) ...・Buffer, (15) ...Address decoder, (16)
... It is an address decoder. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An address storage register that stores the address of the input/output device, an address decoder that decodes the address output from the address storage register and specifies the input/output device, and a DMA controller that controls data transfer between the memory and the input/output device. A direct memory access control device comprising: