JP2002007362A - Information processor and extension method for arithmetic processor to be used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of easily extending an arithmetic processor. SOLUTION: A local bus 100 connected to CPU 11 and 12 and a system bus adapter 2, a local bus 101 connected to CPU 13 and 14 and a system bus adapter 3 and a system bus 200 are constituted on the same interface conditions. Therefore, the CPU 11-14 can be connected directly to the system bus 200 and can be connected through the system bus adapters 2 and 3 as well. By selecting the number of the system bus adapters 2 and 3, a required number of the CPU 11-14 can be extended.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a method for adding an arithmetic processing apparatus used therein, and more particularly to an arithmetic processing in an information processing apparatus comprising an arithmetic processing apparatus, a storage device, an input / output device, and a system bus connecting them. The present invention relates to a method for adding devices.

[0002]

2. Description of the Related Art Conventionally, as an extension method of this kind, an interface condition on an arithmetic processing unit side and an interface condition on a memory access control unit side are the same as the interface conditions between the arithmetic processing unit and the memory access control unit. A processor expansion method has been proposed in which an arithmetic processing device and a memory access control device are connected via a processor expansion adapter described above to increase the number of connected arithmetic processing devices. This processor extension method is disclosed in
060748.

FIG. 5 shows an information processing apparatus to which the above-described processor extension method is applied. In this information processing apparatus, four CPUs (arithmetic processing units) 11 to 14 and these four C
Two processor expansion adapters (ADP) 6, 7 for connecting two PUs 11 to 14 each, one memory access control unit (MCU) 8 for connecting these two processor expansion adapters 6, 7 and One memory device (MM) 51 connected to the memory access control device 8.

[0004] The request selection unit 61 of the processor expansion adapter 6 receives a request A from two CPUs 11 and 12.
1 and A2 are accepted, and either one of the requests is selected. The request selector 61 sends the selected request to the memory access controller 8.

[0005] The memory access control device 8 receives the request sent from the processor expansion adapter 6 by the request receiving unit 81 and sends it to the memory access control unit 82. The memory access control unit 82 is a request control unit 81
Storage device 51 according to the request sent from
, And reads or writes necessary information to the storage device 51 in response to the request, and sends a memory access end notification and necessary information to the reply control unit 83.

The reply control unit 83 sends necessary reply information to the processor extension adapter 6 based on the memory access end notification and the necessary information sent from the memory access control unit 82. In the processor expansion adapter 6, the adapter control unit 62 determines whether the reply information is to one of the CPUs 11 and 12 based on the sent reply information. Based on this judgment result,
The reply distribution unit 63 sends necessary reply information B1 and B2 to the CPUs 11 and 12.

In the above description, the processor expansion adapter 6
The operation on the side of the processor expansion adapter 7 has been described, but the operation on the side of the processor expansion adapter 7 is also the same as the operation on the side of the processor expansion adapter 6 described above, and a description thereof will be omitted.

[0008]

In the conventional processor diffusion adapter described above, the arithmetic processing unit and the memory access control unit are connected by unifying the interface of the arithmetic processing unit and the interface of the memory access control unit. For this purpose, the memory access control device has to prepare interfaces to the arithmetic processing device in the number of connections expected in advance, so that there is a problem that it is not easy to expand the system.

When the above-mentioned processor diffusion adapter is used, the information processing device does not have a function for performing communication between the processing devices, so that communication between the processing devices cannot be performed. There's a problem.

An object of the present invention is to solve the above-mentioned problems and to provide an information processing apparatus capable of easily adding an arithmetic processing unit and a method of adding an arithmetic processing unit used therefor.

[0011]

An information processing apparatus according to the present invention comprises an arithmetic processing unit, a storage device, an input / output device, and a system bus connecting the arithmetic processing device, the storage device, and the input / output device. An information processing apparatus comprising:
A local bus configured under the same interface conditions as the system bus and connected to the arithmetic processing unit; a system bus adapter including a unit that controls an interface with the local bus and a unit that controls an interface with the system bus; The system bus adapter is configured to connect the local bus to the system bus.

[0012] A method for adding an arithmetic processing unit according to the present invention is as follows.
An arithmetic processing device, a storage device, an input / output device, and a method of adding an arithmetic processing device of an information processing device including the arithmetic processing device, and a system bus connecting the storage device and the input / output device, A system bus adapter having a local bus configured with the same interface conditions as the system bus and connected to the arithmetic processing unit, and including a unit for controlling an interface with the local bus and a unit for controlling an interface with the system bus Connects the local bus to the system bus.

That is, the method for adding an arithmetic processing unit according to the present invention comprises the steps of: at least one arithmetic processing unit, at least one storage device, at least one input / output device, and at least one storage device and at least one input / output device. An information processing device comprising a system bus for connecting to an output device, wherein, instead of the arithmetic processing device connected to the system bus, one or more arithmetic processing devices having the same interface conditions as the system bus By connecting a system bus adapter having means for controlling an interface with a local bus connected to the system bus and means for controlling an interface with the system bus to the system bus, it is possible to easily add an additional processing unit. I have.

After acquiring the right to use the local bus, the arithmetic processing unit issues a request and data to the local bus. The request includes information indicating the source of the request and information indicating the destination of the request. The processing unit that has issued the request in the information indicating the source of the request and the device that receives the request in the information indicating the destination of the request. Write each.

The means for controlling the interface of the system bus adapter with the local bus receives the request and data with reference to the request, and sends the request and data to the means for controlling the interface with the system bus.

The means for controlling the interface of the system bus adapter with the system bus, when receiving the request and the data, issues a request for use of the system bus and obtains the right to use the system bus, and then transfers the request and data to the system. Issue to the bus.

The device corresponding to the information indicating the request issuing destination receives the request and the data by referring to the information indicating the request issuing destination, performs processing corresponding to the request, and then determines the request issuing source. The content of the indicated information is stored in the information indicating the reply issue destination as the reply issue destination device. Thereafter, the right to use the system bus is acquired, and a reply and data are issued.

The means for controlling the interface of the system bus adapter with the system bus receives the reply and the data with reference to the reply and sends it to the means for controlling the interface with the local bus. The means for controlling the interface with the local bus issues a reply and data after acquiring the right to use the local bus. The arithmetic processing device that has issued the request refers to the information indicating the device to which the reply is issued, and receives the reply and the data.

All arithmetic processing units connected to the local bus can process requests and replies in the same manner as the above processing. Further, all the system bus adapters are connected to the processing unit and the system bus in the same manner as the above configuration, and processing of each request and reply from the processing unit connected to each system bus adapter is performed. Can be similarly performed.

Here, the local bus connecting the arithmetic processing unit and the system bus adapter and the system bus have the same interface conditions. Therefore,
The arithmetic processing device can be directly connected to the system bus, or can be connected via a system bus adapter.

With the above configuration, it is possible to increase the required number of arithmetic processing units by connecting the system bus adapter to the system bus according to the number of connected arithmetic processing units.

That is, usually, the arithmetic processing unit is directly connected to the system bus without going through the system bus adapter. Depending on the number of arithmetic processing units to be added, some arithmetic processing units are connected directly to the system bus, and instead of the arithmetic processing units directly connected to the system bus, the arithmetic processing units are system-connected using a system bus adapter. By connecting to a system bus via a bus adapter, it is possible to add an additional processing unit.

It is also possible to use a system bus adapter instead of all the processing units directly connected to the system bus, and connect the processing unit to the system bus via the system bus adapter.

Further, since the storage device and the input / output device are directly connected to the system bus, it is not necessary to worry about the number of interfaces for connecting the storage device and the input / output device to the system bus adapter.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to one embodiment of the present invention. In FIG. 1, an information processing apparatus according to an embodiment of the present invention has four Cs.
PUs (arithmetic processing units) 11 to 14 and these four CPs
Two system bus adapters (SBAs) 2 and 3 for connecting two U11 to U14 and two storage devices (MM) 5
1, 52, two input / output devices (IO) 41, 42,
A local bus (LB) 100 connecting the CPUs 11 and 12 to the system bus adapter 2 and a local bus 101 connecting the CPUs 13 and 14 and the system bus adapter 3
, System bus adapters 2 and 3 and storage devices 51 and 52
Bus (S) connecting the I / O devices 41 and 42
B) 200.

The system bus adapters 2 and 3 are local bus control functions (LBC) 21 and 31 for controlling the interface with the local buses 100 and 101, and the system bus control function (SBC) 22 for controlling the interface with the system bus 200. , 32 and the local buses 100, 1
01 and local bus buffers (LBB) 23, 33 for storing the request and reply sent from
And a system bus buffer (S) for storing the request and reply sent from the system bus 200.
BB) 24 and 34 respectively. In this embodiment, system bus adapters 2 and 3 are connected to the system bus 200.

The operation of the information processing apparatus according to one embodiment of the present invention will be described with reference to FIG. First, CP
The operation at the time of writing from U11 to the storage device 51 will be described.

The CPU 11 issues a request for using the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 look at the use request of the local bus 100 and change the right to use the local bus 100 to the CPU 1.
Give to 1. C who has obtained the right to use the local bus 100
The PU 11 issues a write request and write data to the local bus 100. This write request includes information indicating the request issuing source and information indicating the request issuing destination. Here, the CPU 11 is written in the information indicating the request issuing source, and the storage device 51 is written in the information indicating the request issuing destination. Put in.

The local bus control function 21 refers to the write request and receives the write request and the write data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a request to use the local bus 100 to the local bus 100 in order to issue the next request or reply.

The local bus control function 21 sends the received write request and write data to the system bus control function 22. At this time, if the system bus control function 22 is processing the previously issued request or reply, the write request and the write data are stored in the local bus buffer 23, and the system bus control function 2
After the processing of step 2 is completed, it is sent to the system bus control function 22.

When receiving the write request and the write data, the system bus control function 22 adds the system bus adapter 2 to the information indicating the source of the request, and issues a use request of the system bus 200 to the system bus 200. System bus control functions 22, 32 and input / output device 4
1, 42 and the storage devices 51, 52 are connected to the system bus 200.
, The right to use the system bus 200 is given to the system bus control function 22.

The system bus control function 22 having acquired the right to use the system bus 200 issues a write request and write data to the system bus 200. Storage device 5
Reference numeral 1 refers to a write request, and receives a write request and write data. Thereafter, the system bus control functions 22, 32, the input / output devices 41, 42, and the storage devices 51, 5
No. 2 makes it possible to issue a use request of the system bus 200 to the system bus 200 in order to issue the next request or reply.

Upon receiving the write request and the write data, the storage device 51 performs a write process of the write data. After that, the content of the information indicating the source of the request included in the write request is stored in the information indicating the destination of the write reply. The storage device 51 issues a request for using the system bus 200 to the system bus 200. System bus control functions 22, 32 and input / output device 4
1, 42 and the storage devices 51, 52 are connected to the system bus 200.
The use right of the system bus 200 is given to the storage device 51 after seeing the use request of the storage device 51.

The storage device 51 that has acquired the right to use the system bus 200 issues a write reply to the system bus 200. The system bus control function 22 refers to the write reply and receives the write reply. Thereafter, the system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 are connected to the system bus 200 to issue the next request or reply.
0 can be issued.

The system bus control function 22 sends the received write reply to the local bus control function 21. At this time, if the local bus control function 21 is processing the previously issued request or reply, this write reply is stored in the system bus buffer 24, and after the processing of the local bus control function 21 is completed, Sent to control function 21.

When the local bus control function 21 receives the write reply, the local bus control function 21 deletes the system bus adapter 2 from the information indicating the issue destination of the reply, and issues a request to the local bus 100 to use the local bus 100. CPUs 11 and 12
The local bus control function 21 gives the use right of the local bus 100 to the local bus control function 21 upon seeing the use request of the local bus 100.

The local bus control function 21 having acquired the right to use the local bus 100 issues a write reply to the local bus 100. The CPU 11 refers to the write reply and receives the write reply.

Next, the operation of the CPU 11 when reading data from the storage device 51 will be described. In this case, CP
U11 issues a request to use the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 see the request to use the local bus 100 and give the right to use the local bus 100 to the CPU 11.

C that has acquired the right to use the local bus 100
The PU 11 issues a read request to the local bus 100. The read request includes information indicating a request issuing source and information indicating a request issuing destination,
Here, the information indicating the request issuing source is stored in the CPU 11.
Is written in the storage device 51 to the information indicating the destination of the request.

The local bus control function 21 refers to the read request and stores the read request. After this,
The CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

The local bus control function 21 sends the received read request to the system bus control function 22. At this time, if the system bus control function 22 is processing a previously issued request or reply, the read request is stored in the local bus buffer 23, and after the processing of the system bus control function 22 is completed, Sent to control function 22.

When receiving the read request, the system bus control function 22 adds the system bus adapter 2 to the information indicating the request issuing source, and
Issues a request to use the system bus 200. The system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200 and give the use right of the system bus 200 to the system bus control function 22.

The system bus control function 22 having acquired the right to use the system bus 200 issues a read request to the system bus 200. The storage device 51 refers to the read request and receives the read request. Thereafter, the system bus control functions 22, 32 and the input / output devices 41, 42
And the storage devices 51 and 52 can issue a use request of the system bus 200 to the system bus 200 to issue the next request or reply.

Upon receiving the read request, the storage device 51 performs read data read processing. After that, the content of the information indicating the issue source of the request included in the read request is stored in the information indicating the issue destination of the reply of the read reply. The storage device 51 is a system bus 200
Issues a request to use the system bus 200. The system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200 and give the use right of the system bus 200 to the storage device 51.

The storage device 51 that has acquired the right to use the system bus 200 issues a read reply and read data to the system bus 200. System bus control function 22
Refers to the read reply and receives the read reply and the read data. Thereafter, the system bus control function 22,
The input / output devices 32, the input / output devices 41 and 42, and the storage devices 51 and 52 can issue a use request of the system bus 200 to the system bus 200 in order to issue the next request or reply.

The system bus control function 22 transmits the received read reply and read data to the local bus control function 2.
Send to 1. At this time, if the local bus control function 21 is processing the previously issued request or reply, the read reply and the read data are stored in the system bus buffer 24, and the local bus control function 21
Is sent to the local bus control function 21.

When the local bus control function 21 receives the read reply and the read data, the local bus control function 21 deletes the system bus adapter 2 from the information indicating the issue destination of the reply, and issues a request for using the local bus 100 to the local bus 100. C
The PUs 11 and 12 and the local bus control function 21 see the request to use the local bus 100 and give the right to use the local bus 100 to the local bus control function 21.

The local bus control function 21 having acquired the right to use the local bus 100 issues a read reply and read data to the local bus 100. The CPU 11 refers to the read reply and receives the read reply and the read data.

The operation at the time of data output from the CPU 11 to the input / output device 41 is performed by the CPU 11 described above.
This is the same as the operation when writing to. The operation when data is input to the CPU 11 from the input / output device 41 is the same as the operation when data is read from the storage device 51 to the CPU 11 described above. Therefore, the input / output device 4
The description of the data output operation and the data input operation for 1 is omitted.

Next, the operation of inter-processor communication in the local bus 100 from the CPU 11 to the CPU 12 will be described. In this case, the CPU 11
To the local bus 100. CPU1
The local bus control function 21 gives the right to use the local bus 100 to the CPU 11 upon seeing the request to use the local bus 100.

C having acquired the right to use the local bus 100
The PU 11 issues an inter-processor communication request and data to the local bus 100. This inter-processor communication request includes information indicating the source of the request and information indicating the destination of the request. Here, the CPU 11 is written in the information indicating the source of the request, and the CPU 12 is written in the information indicating the destination of the request. Put in.

The CPU 12 refers to the inter-processor communication request and receives the inter-processor communication request and data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

Upon receiving the inter-processor communication request and the data, the CPU 12 performs a process corresponding to the inter-processor communication request. Then, the content of the information indicating the issue source of the request included in the inter-processor communication request is stored in the information indicating the issue destination of the reply of the inter-processor communication reply. CPU 12 is a local bus 100
To the local bus 100. CPU1
The local bus control function 21 determines whether to grant the right to use the local bus 100 to the CPU 12 by seeing the request to use the local bus 100.

C that has acquired the right to use the local bus 100
The PU 12 issues an inter-processor communication reply and data to the local bus 100. The CPU 11 refers to the inter-processor communication reply and receives the inter-processor communication reply and data.

Next, the operation of inter-processor communication from the CPU 11 to the CPU 13 via the system bus 200 will be described. In this case, the CPU 11
00, a request to use the local bus 100 is issued. CPU
The local bus control function 21 gives the right to use the local bus 100 to the CPU 11 upon seeing the request to use the local bus 100.

C having acquired the right to use the local bus 100
The PU 11 issues an inter-processor communication request and data to the local bus 100. The inter-processor communication request includes information indicating the request issuing source and information indicating the request issuing destination. Here, the CPU 11 is written in the information indicating the request issuing source, and the CPU 13 is written in the information indicating the request issuing destination. Put in.

The local bus control function 21 refers to the inter-processor communication request, and receives the inter-processor communication request and data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

The local bus control function 21 sends the received inter-processor communication request and data to the system bus control function 22. At this time, if the system bus control function 22 is processing the previously issued request or reply, the inter-processor communication request and data are stored in the local bus buffer 23, and the processing of the system bus control function 22 ends. After that, it is sent to the system bus control function 22.

When receiving the interprocessor communication request and the data, the system bus control function 22 adds the system bus adapter 2 to the information indicating the source of the request, and issues a use request of the system bus 200 to the system bus 200. System bus control functions 22, 32 and input / output device 4
1, 42 and the storage devices 51, 52 are connected to the system bus 200.
, The right to use the system bus 200 is given to the system bus control function 22.

The system bus control function 22 that has acquired the right to use the system bus 200 issues an inter-processor communication request and data to the system bus 200. The system bus control function 32 refers to the inter-processor communication request and receives the inter-processor communication request and data.
Thereafter, the system bus control functions 22, 32, the input / output devices 41, 42, and the storage devices 51, 52 communicate with the system bus 200 to issue the next request or reply.
, A request to use the system bus 200 can be issued.

The system bus control function 32 sends the received inter-processor communication request and data to the local bus control function 31. At this time, if the local bus control function 31 is processing a previously issued request or reply, the inter-processor communication request and data are stored in the system bus buffer 34, and the processing of the local bus control function 31 ends. After that, it is sent to the local bus control function 31.

When the local bus control function 31 receives the inter-processor communication request and the data, the local bus control function 31 adds the system bus adapter 3 to the information indicating the issue source of the request, and issues a request for using the local bus 101 to the local bus 101. The CPUs 13 and 14 and the local bus control function 31 see the request to use the local bus 101 and give the right to use the local bus 101 to the local bus control function 31.

The local bus control function 31 having acquired the right to use the local bus 101 issues an inter-processor communication request and data to the local bus 101. CPU1
Reference numeral 3 refers to the inter-processor communication request, and receives the inter-processor communication request and data.

Upon receiving the inter-processor communication request and the data, the CPU 13 performs a process corresponding to the inter-processor communication request. Then, the content of the information indicating the issue source of the request included in the inter-processor communication request is stored in the information indicating the issue destination of the reply of the inter-processor communication reply. The CPU 13 is a local bus 101
To the local bus 101. CPU1
The local bus control function 31 gives the right to use the local bus 101 to the CPU 13 upon seeing the request to use the local bus 101.

C that has acquired the right to use local bus 101
The PU 13 issues an inter-processor communication reply and data to the local bus 101. Local bus control function 31
Refers to the inter-processor communication reply, and receives the inter-processor communication reply and data. Thereafter, the CPU 13,
14 and the local bus control function 31 communicate with the local bus 101 to issue the next request or reply.
, A request to use the local bus 101 can be issued.

The local bus control function 31 sends the received inter-processor communication reply and data to the system bus control function 32. At this time, if the system bus control function 32 is processing a previously issued request or reply, the inter-processor communication reply and data are stored in the local bus buffer 33, and the processing of the system bus control function 32 ends. After that, the system bus control function 32
Sent to

When the system bus control function 32 receives the inter-processor communication reply and the data, the system bus control function 32 deletes the system bus adapter 3 from the information indicating the destination of the reply, and issues a use request of the system bus 200 to the system bus 200. System bus control functions 22, 32 and input / output device 4
1, 42 and the storage devices 51, 52 are connected to the system bus 200.
, The system bus control function 32 is given a right to use the system bus 200.

The system bus control function 32 having acquired the right to use the system bus 200 issues an inter-processor communication reply and data to the system bus 200. The system bus control function 22 refers to the inter-processor communication reply,
Receive inter-processor communication reply and data. Thereafter, the system bus control functions 22 and 32 and the input / output device 4
1, 42 and the storage devices 51, 52 are sent to the system bus 200 to issue the next request or reply.
A request to use the system bus 200 can be issued.

The system bus control function 22 sends the received inter-processor communication reply and data to the local bus control function 21. At this time, if the local bus control function 21 is processing the previously issued request or reply, the inter-processor communication reply and data are stored in the system bus buffer 24, and the processing of the local bus control function 21 ends. After that, the local bus control function 21
Sent to

When the local bus control function 21 receives the inter-processor communication reply and the data, the local bus control function 21 deletes the system bus adapter 2 from the information indicating the issue destination of the reply, and issues a request to the local bus 100 to use the local bus 100. The CPUs 11 and 12 and the local bus control function 21 see the use request of the local bus 100 and
The right to use 00 is given to the local bus control function 21.

The local bus control function 21 that has acquired the right to use the local bus 100 issues an inter-processor communication reply and data to the local bus 100. CPU1
Reference numeral 1 refers to the inter-processor communication reply, and receives the inter-processor communication reply and data.

The CPU 12 can process requests and replies in the same manner as the CPU 11 described above. The system bus adapter 3 is also connected to the CPUs 13 and 14 and the system bus 20 similarly to the system bus adapter 2.
0, and can perform processing of requests and replies from the CPUs 13 and 14, respectively.

Here, a local bus 100 connecting the CPUs 11 and 12 and the system bus adapter 2 and a CPU
The local bus 101 that connects the system bus adapters 13 and 14 with the system bus adapter 3 is configured under the same interface conditions. Therefore, the CPUs 11 to 14 can be directly connected to the local bus 101 or can be connected via the system bus adapters 2 and 3.

By configuring as described above, FIG.
As shown in (c), by connecting the system bus adapters 2 and 3 to the system bus 200 in accordance with the number of connected processing units, the required number of processing units can be increased.

That is, in the present embodiment, usually, in the case of two CPUs 11 and 12, the CPUs 11 and 12 are connected to the system bus 20 without the system bus adapters 2 and 3.
0 [see FIG. 2 (a)].

In the case of the CPUs 11 to 13, the CPU 11
Instead of CP via one system bus adapter 2
U11 and 12 are connected to the system bus 200, and the CPU 1
3 is directly connected to the system bus 200 (see FIG. 2B).

In the case of the CPUs 11 to 14, the CPU 1
The CPUs 11 and 12 are connected to the system bus 200 via the system bus adapter 2 by the two system bus adapters 2 and 3 instead of the CPU 13.
3 and 14 are connected to the system bus 200 via the system bus adapter 3 (see FIG. 2C).

The storage devices 51 and 52 and the input / output device 4
1 and 42 are connected to the system bus 200,
There is no need to worry about the number of interfaces for connecting to the system bus adapters 2 and 3.

FIG. 3 is a block diagram showing a configuration of an information processing apparatus according to another embodiment of the present invention. FIGS. 4A and 4B are diagrams of an information processing apparatus according to another embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration example of a TAG buffer table in a system bus adapter.

In FIG. 3, an information processing apparatus according to another embodiment of the present invention includes local bus buffers 23 and 33 in system bus adapters 2 and 3 and system bus buffer 2.
TAG buffer control unit (TBC) 2 instead of 4, 34
The configuration is the same as that of the information processing apparatus according to the embodiment of the present invention shown in FIG. 1 except that 5 and 35 are provided, and the same components are denoted by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The TAG buffer controllers 25 and 35 have TAG buffer tables 26 and 36, respectively (see FIGS. 4A and 4B). At the time of a request, the TAG buffer tables 26 and 36 hold the TAG included in the transmitted request and the information of the issuing device at a free address, and store the address in a new TAG of the request and the own device in the request. Replace with a new issuing device.

The TAG buffer tables 26 and 36
Is the TA included in the reply sent at the time of reply
The stored TAG and the issuing device are read from the address corresponding to G, and the stored TAG is read as a new TAG of the reply, and the stored issuing device is read as a new issuing device of the reply. replace. The address from which the TAG and the information of the issuing device are read is initialized.

The operation of the information processing apparatus according to another embodiment of the present invention will be described with reference to FIGS.
First, an operation at the time of writing from the CPU 11 to the storage device 51 will be described.

The CPU 11 issues a request for using the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 look at the use request of the local bus 100 and change the right to use the local bus 100 to the CPU 1.
Give to 1.

C that has acquired the right to use local bus 100
The PU 11 issues a write request and write data to the local bus 100. This write request is TA
G and the information of the issuing device, the information indicating the issuing source of the request and the information indicating the issuing destination of the request. Here, the request number 6 is added to the TAG of the information indicating the issuing source of the request. Of the request and the storage device 51 of the information indicating the destination of the request.

The local bus control function 21 refers to the write request and receives the write request and the write data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

The local bus control function 21 sends the received write request and write data to the TAG buffer control unit 25. When the TAG buffer control unit 25 receives the write request and the write data, the TAG buffer control unit 25 holds information indicating the issue source of the request included in the write request at an empty address 1 of the TAG buffer table 26.

The TAG buffer control unit 25 stores the TAG of the information indicating the issue source of the request included in the write request at the address 1 of the TAG buffer table 26,
The information of the issuing device is replaced by the system bus adapter 2 and a write request and write data are sent to the system bus control function 22. At this time, if the system bus control function 22 is processing the previously issued request or reply, the write request and the write data are stored in the TAG buffer control unit 25, and the processing of the system bus control function 22 ends. After that, it is sent to the system bus control function 22.

When the system bus control function 22 receives the write request and the write data, the system bus control function 22
Issues a request to use the system bus 200. The system bus control functions 22 and 23, the input / output devices 41 and 42, and the storage devices 51 and 52 see the use request of the system bus 200 and give the use right of the system bus 200 to the system bus control function 22.

The system bus control function 22 having acquired the right to use the system bus 200 issues a write request and write data to the system bus 200. Storage device 51
Refers to the write request and receives the write request and the write data. Thereafter, the system bus control function 2
2, 23, input / output devices 41, 42, and storage devices 51, 52
Means that a request to use the system bus 200 can be issued to the system bus 200 to issue the next request or reply.

Upon receiving the write request and the write data, the storage device 51 performs a write process of the write data. After that, the content of the information indicating the source of the request included in the write request is stored in the information indicating the destination of the write reply.

The storage device 51 issues a request for using the system bus 200 to the system bus 200. System bus control functions 22 and 23, input / output devices 41 and 42, and storage device 5
The devices 1 and 52 see the request for use of the system bus 200 and give the right to use the system bus 200 to the storage device 51.

The storage device 51 that has acquired the right to use the system bus 200 issues a write reply to the system bus 200. The system bus control function 22 refers to the write reply and receives the write reply. Thereafter, the system bus control functions 22 and 23, the input / output devices 41 and 42, and the storage devices 51 and 52 are connected to the system bus 200 to issue the next request or reply.
0 can be issued.

The system bus control function 22 sends the received write reply to the TAG buffer control unit 25. TAG
When receiving the write reply, the buffer control unit 25 receives the T of the information indicating the destination of the reply included in the write reply.
The TAG held at the same address of the TAG buffer table 26 as the AG and the information of the issuing device are read. Here, since the TAG of the reply is 1, addresses 1 to 6 of the TAG buffer table 26 and the CPU 11 are read.

Further, the TAG buffer control unit 25 sets the TA of the information indicating the destination of the reply included in the write reply.
G is read from the TAG buffer table 26,
The CPU 11 replaces the information of the issue destination device, and sends a write reply to the local bus control function 21. At this time, if the local bus control function 21 is processing a previously issued request or reply, this write reply is stored in the TAG buffer control unit 25, and after the processing of the local bus control function 21 is completed, Sent to control function 21.

When the local bus control function 21 receives the write reply, the local bus 100
A request to use 00 is issued. The CPUs 11 and 12 and the local bus control function 21 see the use request of the local bus 100 and give the right to use the local bus 100 to the local bus control function 21.

The local bus control function 21 having acquired the right to use the local bus 100 issues a write reply to the local bus 100. The CPU 11 refers to the write reply and receives the write reply.

Next, the operation at the time of reading from the CPU 11 to the storage device 51 will be described. The CPU 11 issues a request for using the local bus 100 to the local bus 100.
The CPUs 11 and 12 and the local bus control function 21 see the use request of the local bus 100 and
Is given to the CPU 11.

C that has acquired the right to use local bus 100
The PU 11 issues a read request to the local bus 100. This read request includes information indicating the request issuing source including the TAG and the information of the issuing source device, and information indicating the request issuing destination. Here, the request number 6 is added to the TAG of the request issuing source information. ,
The CPU 11 is written in the information of the issuing device, and the storage device 51 is written in the information indicating the destination of the request.

The local bus control function 21 refers to the read request and receives the read request. After this, C
The PUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

The local bus control function 21 sends the received read request to the TAG buffer control unit 25. TA
When the G buffer control unit 25 receives the read request,
The information indicating the source of the request included in the read request is held in the vacant address 1 of the TAG buffer table 26.

The TAG buffer control unit 25 stores the TAG of the information indicating the issue source of the request included in the read request at the address 1 of the TAG buffer table 26,
The source device information is replaced by the system bus adapter 2 and a read request is sent to the system bus control function 22. At this time, if the system bus control function 22 is processing the previously issued request or reply, the read request is sent to the TAG buffer control unit 25.
Is sent to the system bus control function 22 after the processing of the system bus control function 22 is completed.

Upon receiving the read request, the system bus control function 22 issues a request to use the system bus 200 to the system bus 200. System bus control function 22,
32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200, and
00 is given to the system bus control function 22.

The system bus control function 22 having acquired the right to use the system bus 200 issues a read request to the system bus 200. The storage device 51 refers to the read request and receives the read request. Thereafter, the system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 issue a use request of the system bus 200 to the system bus 200 in order to issue the next request or reply. It becomes possible.

Upon receiving the read request, storage device 51 performs read data read processing. After that, the content of the information indicating the issue source of the request included in the read request is stored in the information indicating the issue destination of the reply of the read reply. The storage device 51 is a system bus 200
Issues a request to use the system bus 200. The system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200 and give the use right of the system bus 200 to the storage device 51.

The storage device 51 having acquired the right to use the system bus 200 issues a read reply and read data to the system bus 200. The system bus control function 22 refers to the read reply and receives the read reply and the read data. Thereafter, the system bus control functions 22 and 3
2, the input / output devices 41 and 42 and the storage devices 51 and 52 can issue a use request of the system bus 200 to the system bus 200 to issue the next request or reply.

The system bus control function 22 transmits the received read reply and read data to the TAG buffer control unit 2.
Send to 5. Upon receiving the read reply and the read data, the TAG buffer control unit 25 receives the TAG stored in the same address of the TAG buffer table 26 as the TAG of the information indicating the destination of the reply included in the read reply.
And the information of the issuing device are read. Here is the reply T
Since AG is 1, addresses 1 to 6 of the TAG buffer table 26 and the CPU 11 are read.

Further, the TAG buffer controller 25 sets the TA of the information indicating the destination of the reply included in the read reply.
At 6 when G is read from the TAG buffer table 26, the information of the destination device is replaced by the CPU 11, and the read reply and the read data are sent to the local bus control function 21. At this time, if the local bus control function 21 is processing the previously issued request or reply, the read reply and the read data are stored in the TAG buffer control unit 25, and the processing of the local bus control function 21 ends. Thereafter, it is sent to the local bus control function 21.

When the local bus control function 21 receives the read reply and the read data, the local bus control function 21
Issues a request to use the local bus 100. CPU1
The local bus control function 21 gives the right to use the local bus 100 to the local bus control function 21 upon seeing the request to use the local bus 100.

The local bus control function 21 having acquired the right to use the local bus 100 issues a read reply and read data to the local bus 100. The CPU 11 refers to the read reply and receives the read reply and the read data.

The operation at the time of data output from the CPU 11 to the input / output device 41 is performed in the same manner as described above.
This is the same as the operation when writing to. The operation at the time of data input from the CPU 11 to the input / output device 41 is the same as the operation at the time of reading from the storage device 51 of the CPU 11 described above. Therefore, description of the operation of the CPU 11 when outputting data to the input / output device 41 and the operation when outputting data will be omitted.

Next, the operation of the inter-processor communication in the local bus 100 from the CPU 11 to the CPU 12 will be described. The CPU 11 issues a request for using the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 look at the use request of the local bus 100 and change the right to use the local bus 100 to the CPU 1.
Give to 1.

C that has acquired the right to use local bus 100
The PU 11 issues an inter-processor communication request and data to the local bus 100. This inter-processor communication request includes information indicating the request issuing source and information indicating the request issuing destination, which is composed of the TAG and the information of the issuing source device. Here, the TAG of the information indicating the request issuing source includes 6 in the information of the issuing device C
PU11 is set to the information indicating the destination of the request.
Write 2 each.

The CPU 12 refers to the inter-processor communication request and receives the inter-processor communication request and data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

Upon receiving the inter-processor communication request and the data, the CPU 12 performs a process corresponding to the inter-processor communication request. Then, the content of the information indicating the issue source of the request included in the inter-processor communication request is stored in the information indicating the issue destination of the reply of the inter-processor communication reply.

The CPU 12 issues a request for using the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 look at the use request of the local bus 100 and change the right to use the local bus 100 to the CPU 1.
Give to 2.

C that has acquired the right to use local bus 100
The PU 12 issues an inter-processor communication reply and data to the local bus 100. The CPU 11 refers to the inter-processor communication reply and receives the inter-processor communication reply and data.

Next, the operation of inter-processor communication from the CPU 11 to the CPU 13 via the system bus 200 will be described. The CPU 11 issues a request for using the local bus 100 to the local bus 100. The CPUs 11 and 12 and the local bus control function 21 look at the use request of the local bus 100 and change the right to use the local bus 100 to the CPU 1.
Give to 1.

C that has acquired the right to use local bus 100
The PU 11 issues an inter-processor communication request and data to the local bus 100. This inter-processor communication request includes information indicating the request issuing source and information indicating the request issuing destination, which is composed of the TAG and the information of the issuing source device. Here, the TAG of the information indicating the request issuing source includes 6 in the information of the issuing device C
PU11 is set to the information indicating the destination of the request.
Write 3 each.

The local bus control function 21 refers to the inter-processor communication request and receives the inter-processor communication request and data. Thereafter, the CPUs 11 and 12 and the local bus control function 21 can issue a use request of the local bus 100 to the local bus 100 to issue the next request or reply.

The local bus control function 21 sends the received inter-processor communication request and data to the TAG buffer control unit 25. When the TAG buffer control unit 25 receives the inter-processor communication request and the data, the TAG buffer control unit 25 holds information indicating the issue source of the request included in the inter-processor communication request at the vacant address 1 of the TAG buffer table 26.

The TAG buffer control unit 25 stores the TAG of the information indicating the issue source of the request included in the inter-processor communication request at the address 1 of the TAG buffer table 26 and the information of the issue source device on the system bus adapter 2.
And sends the inter-processor communication request and data to the system bus control function 22. At this time, if the system bus control function 22 is processing the previously issued request or reply, the inter-processor communication request and data are stored in the TAG buffer control unit 25, and the processing of the system bus control function 22 is performed. After the completion, it is sent to the system bus control function 22.

When the system bus control function 22 receives the inter-processor communication request and the data, the system bus control function 22
At 00, a request to use the system bus 200 is issued. The system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200 and give the use right of the system bus 200 to the system bus control function 22.

The system bus control function 22 having acquired the right to use the system bus 200 issues an inter-processor communication request and data to the system bus 200. The system bus control function 32 refers to the inter-processor communication request and receives the inter-processor communication request and data.
Thereafter, the system bus control functions 22, 32, the input / output devices 41, 42, and the storage devices 51, 52 communicate with the system bus 200 to issue the next request or reply.
, A request to use the system bus 200 can be issued.

The system bus control function 32 sends the received inter-processor communication request and data to the TAG buffer control unit 35. Upon receiving the inter-processor communication request and the data, the TAG buffer control unit 35 stores information indicating the issue source of the request included in the inter-processor communication request at the vacant address 3 of the TAG buffer table 36.

The TAG buffer control unit 35 stores the TAG of the information indicating the issue source of the request included in the inter-processor communication request at the address 3 of the TAG buffer table 36 and the information of the issue source device on the system bus adapter 3.
And sends the inter-processor communication request and data to the local bus control function 31. At this time, if the local bus control function 31 is processing the previously issued request or reply, the inter-processor communication request and data are stored in the TAG buffer control unit 35, and the processing of the local bus control function 31 is performed. After the completion, it is sent to the local bus control function 31.

When the local bus control function 31 receives the inter-processor communication request and the data, the local bus control function 31
01, a request to use the local bus 101 is issued. CPU
The local bus control function 31 gives the right to use the local bus 101 to the local bus control function 31 upon seeing the request to use the local bus 101.

The local bus control function 31 having acquired the right to use the local bus 101 issues an inter-processor communication request and data to the local bus 101. CPU1
Reference numeral 3 refers to the inter-processor communication request, and receives the inter-processor communication request and data.

Upon receiving the inter-processor communication request and the data, the CPU 13 performs a process corresponding to the inter-processor communication request. Thereafter, the CPU 13 stores the content of the information indicating the issue source of the request included in the inter-processor communication request in the information indicating the issue destination of the reply of the inter-processor communication reply.

The CPU 13 issues a request to the local bus 101 to use the local bus 101. The CPUs 13 and 14 and the local bus control function 31 see the request to use the local bus 101 and change the right to use the local bus 101 to the CPU 1.
Give to 3.

C that has acquired the right to use local bus 101
The PU 13 issues an inter-processor communication reply and data to the local bus 101. Local bus control function 31
Refers to the inter-processor communication reply, and receives the inter-processor communication reply and data. Thereafter, the CPU 13,
The local bus control function 14 and the local bus control function 31 can issue a request to use the local bus 101 to the local bus 101 to issue the next request or reply.

The local bus control function 31 sends the received inter-processor communication reply and data to the TAG buffer control unit 35. When the TAG buffer control unit 35 receives the inter-processor communication reply and the data, the TAG buffer control unit 35 sets the T of the information indicating the issue destination of the reply included in the inter-processor communication reply.
The TAG held at the same address of the TAG buffer table 36 as the AG and the information of the issuing device are read. Here, since the TAG of the reply is 3, the 1 and the system bus adapter 2 are read from the address 3 of the TAG buffer table 36.

The TAG buffer control unit 35 reads out the TAG of the information indicating the destination of the reply included in the inter-processor communication reply, and replaces the information of the destination device with the system bus adapter 2, respectively. Send the inter-processor communication reply and data to the function 32. At this time, if the system bus control function 32 is processing a previously issued request or reply, the inter-processor communication reply and data are stored in the TAG buffer control unit 35, and the processing of the system bus control function 32 is performed. After the completion, it is sent to the system bus control function 32.

When the system bus control function 32 receives the inter-processor communication reply and the data, the system bus control function 32
At 0, a request to use the system bus 200 is issued. The system bus control functions 22 and 32, the input / output devices 41 and 42, and the storage devices 51 and 52 look at the use request of the system bus 200 and give the use right of the system bus 200 to the system bus control function 32.

The system bus control function 32 having acquired the right to use the system bus 200 issues an inter-processor communication reply and data to the system bus 200. The system bus control function 22 refers to the inter-processor communication reply,
Receive inter-processor communication reply and data. Thereafter, the system bus control functions 22 and 32 and the input / output device 4
1, 42 and the storage devices 51, 52 are sent to the system bus 200 to issue the next request or reply.
A request to use the system bus 200 can be issued.

The system bus control function 22 sends the received inter-processor communication reply and data to the TAG buffer control unit 25. When the TAG buffer control unit 25 receives the inter-processor communication reply and the data, the TAG buffer control unit 25 sets the T of the information indicating the destination of the reply included in the inter-processor communication reply.
The TAG held at the same address of the TAG buffer table 26 as the AG and the information of the issuing device are read. Here, since the TAG of the reply is 1, addresses 1 to 6 of the TAG buffer table 26 and the CPU 11 are read.

The TAG buffer control unit 25 reads out the TAG of the information indicating the issue destination of the reply included in the inter-processor communication reply from the TAG buffer table 26, and replaces the information of the issue destination device with the CPU 11 respectively. The inter-processor communication reply and data are sent to the bus control function 21. At this time, if the local bus control function 21 is processing the previously issued request or reply, the inter-processor communication reply and data are stored in the TAG buffer control unit 25, and the processing of the local bus control function 21 is performed. After the completion, it is sent to the local bus control function 21.

When the local bus control function 21 receives the inter-processor communication reply and the data, the local bus control function 21
At 0, a request to use the local bus 100 is issued. CPU1
The local bus control function 21 gives the right to use the local bus 100 to the local bus control function 21 upon seeing the request to use the local bus 100.

The local bus control function 21 having acquired the right to use the local bus 100 issues an inter-processor communication reply and data to the local bus 100. CPU11
Refers to the inter-processor communication reply and stores the inter-processor communication reply and data.

Similarly to the CPU 11, the CPU 12 can process requests and replies. Also,
Similarly to the system bus adapter 2, the system bus adapter 3 is connected to the CPUs 13 and 14 and the system bus 200, and can process requests and replies from the CPUs 13 and 14, respectively.

Here, the local bus 100 connecting the CPUs 11 and 12 and the system adapter 2 and the CPU 1
The local bus 101 for connecting the system bus adapters 3 and 14 to the system bus adapter 3 and the system bus 200 are configured under the same interface conditions. Therefore, CPU1
1 to 14 can be directly connected to the system bus 200,
Connection via the system bus adapters 2 and 3 is also possible.

With the above configuration, as in the above-described embodiment of the present invention, as shown in FIGS. 2 (a) to 2 (c), the system bus By connecting 2 and 3 to the system bus 200, it is possible to increase the required number of arithmetic processing units.

That is, according to the present embodiment, usually, in the case of two CPUs 11 and 13, the CPUs 11 and 13 are connected to the system bus 20 without passing through the system bus adapters 2 and 3.
0 [see FIG. 2 (a)].

In the case of the CPUs 11 to 13, the CPU 11
Instead of CP via one system bus adapter 2
U11 and 12 are connected to the system bus 200, and the CPU 1
3 is directly connected to the system bus 200 (see FIG. 2B).

In the case of the CPUs 11 to 14, the CPU 1
2 system bus adapters 2 and 3 instead of 1 and 13
CPU 11 and 12 are connected to system bus adapter 2
Connected to the system bus 200 via the
4 is a system bus 20 via the system bus adapter 3.
0 [see FIG. 2 (c)].

The storage devices 51 and 52 and the input / output device 4
1 and 42 are connected to the system bus 200,
There is no need to worry about the number of interfaces for connecting to the system bus adapters 2 and 3.

As described above, one or more CPUs 11 to 14
Alternatively, one or more system bus adapters 2 and 3, one or more storage devices 51 and 52, and one or more input / output devices 4
1 and 42 via the system bus 200, the CPUs 11 to 14 or the system bus adapters 2 and 3 and the storage devices 51 and 5 as long as the system bus 200 permits.
2 and the input / output devices 41 and 42 can be connected.

By connecting one or more CPUs 11 to 14 to the local buses 100 and 101 which have the same interface conditions as the system bus 200,
CPUs 11 to 14 without concern for the number of interfaces between the system bus adapters 2 and 3 and the system bus adapters 2 and 3 and the storage devices 51 and 52.
4 can be added. Therefore, the system can be easily expanded.

Further, by using the system bus 200 and the local buses 100 and 101, an arithmetic processing unit and an arithmetic processing unit, system bus adapters 2 and 3 and an arithmetic processing unit, and a system bus adapter and a system bus adapter can be easily connected. Therefore, communication between the arithmetic processing units can be performed.

[0150]

As described above, according to the present invention, information comprising an arithmetic processing unit, a storage device, an input / output device, and a system bus connecting the arithmetic processing device, the storage device, and the input / output device. In the processing device, a local bus configured under the same interface conditions as the system bus and connected to the arithmetic processing unit is connected to a system bus adapter having means for controlling an interface with the local bus and means for controlling an interface with the system bus. By connecting to the system bus, there is an effect that the number of arithmetic processing units can be easily increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIGS. 2A to 2C are diagrams showing a connection form to a system bus in an information processing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of an information processing apparatus according to another embodiment of the present invention.

FIGS. 4A and 4B are diagrams illustrating a configuration example of a TAG buffer table in a system bus adapter of an information processing apparatus according to another embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a conventional information processing apparatus.

[Explanation of symbols]

 2, 3 System bus adapter (SBA) 11 to 14 Processing unit (CPU) 21, 31 Local bus control function (LBC) 22, 32 System bus control function (SBC) 23, 33 Local bus buffer (LBB) 24, 34 System bus buffer (SBB) 25, 35 TAG buffer controller (TBC) 26, 36 TAG buffer table (TBT) 41, 42 Input / output device (IO) 51, 52 Storage device (MM) 100, 101 Local bus (LB) 200 System bus (SB)

Claims (10)

[Claims] 1. An information processing apparatus comprising: an arithmetic processing device, a storage device, an input / output device, and a system bus connecting the arithmetic processing device, the storage device, and the input / output device. A local bus configured under the same interface conditions as the bus and connected to the arithmetic processing unit; and a system bus adapter including means for controlling an interface with the local bus and means for controlling an interface with the system bus. An information processing apparatus configured to connect the local bus to the system bus by the system bus adapter. 2. The information processing apparatus according to claim 1, wherein the system bus adapter is connected to the system bus in place of the arithmetic processing device connected to the system bus. 3. The means for controlling the interface with the local bus receives the request and data with reference to the request from the arithmetic processing unit and sends the request and data to the means for controlling the interface with the system bus. 2. The system according to claim 1, wherein said means for controlling an interface with said system is configured to issue said request and data to said system bus after acquiring said right to use said system bus when receiving said request and data. The information processing device according to claim 2. 4. A means for controlling the interface with the system bus, wherein the means for controlling the interface with the local bus receives the reply and the data by referring to the reply to the request and sends it to the means for controlling the interface with the local bus. 4. The information processing apparatus according to claim 3, wherein the control unit is configured to issue the reply and the data to the local bus after acquiring the right to use the local bus. 5. The system bus adapter according to claim 1, wherein the system bus adapter includes means for storing the request and the reply transmitted and received between the local bus and the system bus. An information processing apparatus according to claim 1. 6. An additional processing unit for an information processing device comprising a processing unit, a storage device, an input / output device, and a system bus connecting the processing unit, the storage device, and the input / output device. A method comprising the steps of: providing a local bus configured with the same interface conditions as the system bus and connected to the processing unit; controlling the interface with the local bus; and controlling the interface with the system bus. A method of adding an arithmetic processing unit, wherein the local bus is connected to the system bus by a system bus adapter including: 7. The additional processing device according to claim 6, wherein the system bus adapter is connected to the system bus instead of the processing device connected to the system bus. Method. 8. A means for controlling an interface with the local bus, wherein the means for receiving a request and data with reference to a request from the arithmetic processing unit and sending the received request and data to means for controlling an interface with the system bus, 7. The system according to claim 6, wherein the means for controlling the interface with the controller issues the request and data to the system bus after acquiring the right to use the system bus when receiving the request and data. A method for adding an arithmetic processing device according to claim 7. 9. A means for controlling the interface with the system bus, wherein the means for controlling the interface with the local bus receives the reply and the data with reference to the reply to the request and sends it to the means for controlling the interface with the local bus. 9. The method according to claim 8, wherein the control unit issues the reply and the data to the local bus after acquiring the right to use the local bus. 10. The system bus adapter according to claim 6, wherein the system bus adapter stores the request and the reply transmitted and received between the local bus and the system bus. The method of adding an arithmetic processing unit according to the above.