JPH0553999A - Inter-cpu interruption controller - Google Patents

Abstract

PURPOSE:To provide the inter-CPU interruption controller which enables interruption at plural levels between plural CPUs so as to shorten processing time for inter-CPU interruption and to simplify the interruption processing. CONSTITUTION:An interruption register 33 for CPU is composed of an interruption storage part 35 equipped with the interruption flags of respective interruption levels on the CPU side to receive the interruption from the same CPU for loading the interruption and an access control storage part 34 to manage storage to the interruption storage part 35, and these registers 33 are correspondent to the respective CPU for loading the interruption and is provided as many as the corresponding CPU. An interruption cause register 36 for interruption level can simultaneously read the contents of the interruption storage part 35 for each CPU and each CPU side interruption level to receive the interruption, these registers 36 are correspondent to the respective levels and are provided as many as the corresponding levels, and an interruption request part 37 is provided to request the interruption to the CPU by levels based on information in the interruption storage part 35 of the interruption register 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a numerical control device for a laser beam machine, etc., and uses a plurality of CPUs in the equipment, and uses an interrupt to execute information exchange between the CPUs. And an interrupt control device between a plurality of CPUs.

[0002]

2. Description of the Related Art In recent years, in devices using microcomputers, an increase in the amount of information in the devices and a high processing speed are demanded, and a plurality of CPUs are used to control each CP.
There is an increasing number of distributed systems in which the U is individually assigned a function having a characteristic and information is exchanged between the CPUs to configure the entire system.

In a device using such a distributed system microcomputer, a system shown in FIG. 1 is known as a system for exchanging information between CPUs in a large amount at high speed.

In the conventional example shown in FIG. 1, an interrupt control device provided for each CPU 5 receives an interrupt generation unit 9 for generating an interrupt and an interrupt reception for receiving an interrupt generated by another CPU 5. And a section 10. As shown in FIG. 2, the interrupt receiving unit 10 includes an interrupt receiving register 15 including a large number of interrupt flags 16 so as to be able to respond to the interrupt generation of all the CPUs 5 of the other party.
And an interrupt request unit 17 which issues an interrupt request to its own CPU 5. Also, the interrupt generation unit 9
Has a large number of interrupt generation units for each CPU so as to be able to handle the interrupt reception of all the CPUs 5 of the other party. As shown in FIG. 2, the interrupt generation units for each CPU and the interrupt flags 16 corresponding thereto are provided. And are in a one-to-one correspondence, and are connected by the interrupt request line 13.

However, according to this conventional example, when the number of CPUs 5 for performing interrupt communication between the CPUs 5 increases, the number of interrupt request lines 13 increases geometrically.

That is, assuming that the number of CPUs 5 is M, the number W of interrupt request lines 13 is represented by the equation (1).

W = M × (M 1) (1) FIG. 3A shows the case where the number of CPUs 5 is four. In this case, the interrupt request line 13 Will be 12. Further, FIG. 3B shows a case where the number of CPUs 5 is 5, but in this case, the number of interrupt request lines 13 is 20.
It will be a book.

In the above case, the interrupt level was not taken into consideration, but in many cases the interrupt level must actually be taken into consideration. If there are N levels of interrupt levels, the interrupt request line The number W of 13 is expressed as in equation (2).

W = N × M × (M 1) (2) Therefore, for example, the number of CPUs 5 is 4 and the interrupt level is 7
In the stage, the number of interrupt request lines 13 becomes 84. As described above, in the conventional example described above, the CPU 5
The number of interrupt request lines 13 increases extremely as the number of interrupts increases, and in particular, when the number of interrupt levels increases in addition to the increase in the CPU 5, there is a problem that it is practically impossible to deal with this. There is.

As a conventional example that solves such a problem, there are conventional examples shown in FIGS.

In this conventional example, the interrupting CPU obtains the exclusive right of the local bus of the interrupt destination CPU and stores the interrupt information to perform the interrupt between the CPUs.

As shown in FIG. 4, corresponding to each CPU 21, a bus control unit 18, a buffer 19, a memory 22, an interrupt control unit 23, an I / O 24, and an inter-CPU interrupt control device 2 are provided.
5 are provided. Inter-CPU interrupt controller 25
Is an interrupt register 2 having an interrupt storage unit 30 having an individual interrupt flag configuration for each CPU, as shown in FIG.
9 and an interrupt request unit 31. The internal structure of the interrupt register 29 is shown in Table 1. Table 2 is a state transition table of the interrupt flag in the interrupt register 29. FIG. 6 shows the interrupt register 29 and the interrupt request unit 3.
1 shows an example of a circuit configuration of 1.

[0013]

[Table 1]

[0014]

[Table 2]

As shown in FIGS. 4 and 5, each CPU 21
There is provided a common memory 20 for storing management information for managing the individual access to the interrupt register 29 which is locally present. The common memory 20 has an interrupt register access control storage unit 32. The access control storage unit 32, as shown in Table 3, has a semaphore flag corresponding to each interrupt register 29.

[0016]

[Table 3]

Next, the interrupt operation between the CPUs of the above conventional example will be described. Since the interrupt register 29 of the inter-CPU interrupt control device 25 attached to each CPU 21 has an interrupt flag corresponding to all the other CPUs 21, each C
Access from the PU 21 may be mixed. For this reason, the interrupt generation processing by the other CPU 21 and its own C
It is necessary to guarantee a series of read and write access to the interrupt register 29 in the interrupt reception processing by the PU 21, and for this guarantee, the access control storage unit 32 on the common memory 20 stores the interrupt register 29 of each CPU 21. In order to individually manage the access right, it is configured to have semaphore flags for the number of interrupt registers 29,
This controls the access right.

FIG. 7 is a flowchart showing the control of the access right. The CPU requesting the interrupt accesses the interrupt register access control storage unit 32 on the common memory 20, determines whether the semaphore flag corresponding to the interrupt register 29 of the other CPU is “0”,
When this is "1", the other CPU has acquired the access right, and therefore waits for the release of the access right of the other CPU (step # 1). When it is "0", "1" is written in the corresponding semaphore flag to acquire the access right, and this is notified to the other CPU (step # 2). Then, a series of processing to the corresponding interrupt register 29 is performed (step # 3), and immediately thereafter, the semaphore flag is set to "0".
To release the access right (step # 4).

FIG. 8 shows a flow chart when the interrupt from the i-th CPU (CPU-i) to the j-th CPU (CPU-j) is performed. CP requesting an interrupt
U-i is the interrupt register 2 of the CPU-j on the other side.
The access right is acquired for the semaphore flag corresponding to 9 according to the access right control flow (step # 1).
1, # 12). Next, the CPU-i accesses the interrupt register 29 in the local area of the CPU-j, reads the contents, and then changes only its own interrupt flag for the CPU-i to "1" (steps # 13, # 1).
4). Based on this information, the interrupt request unit 31 determines that the CPU-j
An interrupt request is issued via the interrupt controller 23 (see FIG. 5, step # 16). At the same time, the CPU-i sets the semaphore flag to "0", and the interrupt register 2
The access right to 9 is released (step # 15).

The CPU-j on the side requested to interrupt recognizes the interrupt request, interrupts the current process (steps # 17, # 18), and then C in the common memory 20.
The access right is acquired in accordance with the access right control flow (see FIG. 7) for the semaphore flag for the interrupt register of PU-j (steps # 19, # 20). Then, by reading the interrupt register 29, the CPU-i requesting the interrupt is recognized (steps # 21 and # 2).
2). Further, only the interrupt flag corresponding to the CPU-i which has requested the interrupt is changed to "0" to initialize the interrupt factor (steps # 23, # 24). Finally CPU-
Set the interrupt register semaphore flag of j to "0",
The access right of the interrupt register is released, the process corresponding to the interrupt is executed, and then the process of returning from the interrupt process is executed (steps # 25, # 26, # 27).

In FIG. 7 and FIG. 8, the processing indicated by a is access that prohibits division, and it is necessary to guarantee this in terms of hardware. As one method for this, T
There is a method of guaranteeing division prohibition by having an AS (test and set) instruction.

The process indicated by b shows the access right control flow of FIG.

[0023]

The conventional example shown in FIG.
As described above, in order to guarantee a series of accesses relating to interrupt generation processing by another CPU and interrupt reception processing by its own CPU, an access control storage unit is provided on the common memory, and this access control storage unit is local to each CPU. It was necessary to configure the interrupt register of semaphore flag individually and perform the access right control flow.
The access right control flow is complicated and the processing time is long.

If the number of CPUs is M and the interrupt level is N stages, the number of semaphore flags is (M × N).
There is also a problem that the number of individuals becomes extremely large, and the management of access rights becomes complicated.

If the interrupt register access control storage unit 32 shown in FIG. 5 is omitted and the access right control flow shown in FIG. 8B is omitted, the following inconvenience occurs.

FIG. 9 shows the CPU-
2 shows the transition of the interrupt flag in the interrupt register in the inter-CPU interrupt control device attached to the receiving CPU when the interrupt request is generated. In the case shown in FIG. 9, since the prohibition of access by the other CPUs is guaranteed and the interrupt request of only the CPU-2 occurs during the period shown by P and Q, normal processing is performed. However, it is difficult to guarantee P and Q by hardware, and if this is not guaranteed, interrupt requests from a plurality of CPUs are mixed and normal processing is not performed as shown in FIGS. 10 and 11. Cause a situation.

FIG. 10 shows a case where the CPU-2 and the CPU-M request an interrupt to the same interrupt register. In this case, the prohibited period of P shown in FIG.
The PU-2 and subsequently the CPU-M read the interrupt register, and after that, the CPU-2 writes "1" to the CPU-2 flag, and then the CPU-M sets the CPU-2 flag to "0". “1” is written in the CPU-M flag, which causes a disadvantage that the interrupt request of the CPU-2 disappears.

FIG. 11 shows a case where an interrupt request is issued from CPU-M while the receiving CPU recognizes the interrupt from CPU-2. In this case, the prohibited period of Q shown in FIG. 9 is not guaranteed, and the receiving CPU and the CPU subsequent to this are not guaranteed.
-M reads the interrupt register, and then the receiving CPU changes the CPU-2 flag to "0" to initialize the interrupt factor. Then, CPU-M causes the CPU-2 flag and the CPU-M flag. As a result of writing "1" to the CPU
The -2 flag is reset to "1", which causes a double interruption.

The present invention solves the above-mentioned problems of the conventional example and enables a CPU up to a plurality of interrupt levels.
An object is to provide an inter-interruption control device.

[0030]

In order to achieve the above object, the present invention has a plurality of CPUs in a device, and the interrupting CPU acquires the bus exclusive right of the local bus of the CPU that receives the interrupt and interrupts. CP in the system
In an inter-CPU interrupt control device attached to U, an interrupt storage unit having an interrupt flag of each interrupt level on the CPU side where the interrupting CPU is the same, and an access control unit managing storage in the interrupt storage unit An interrupt register composed of and is provided corresponding to each of the CPUs that make interrupts and provided by the corresponding number, and the contents of the interrupt storage unit of each CPU are read out collectively for each interrupt level of the CPU that receives the interrupt. It is provided with an interrupt factor register that can handle each level and is provided with the corresponding number of interrupt factor registers, and an interrupt request unit that requests an interrupt request for each level from the CPU based on the information in the interrupt storage unit of the interrupt register. , An address for selecting one of the plurality of interrupt registers and the plurality of interrupt factor registers to make it accessible A coder is provided, and the interrupt register is configured to be accessed for each CPU that issues an interrupt, and the storage operation for the interrupt storage unit is managed by the information of the access control unit in the interrupt register that corresponds to the CPU that issues the interrupt. It is characterized by

[0031]

According to the present invention, since an interrupt control register (semaphore flag) is provided in the interrupt register of each CPU (transmission CPU) that issues an interrupt, an interrupt in its own interrupt register is made by using the semaphore flag. The control flow of the access right to the storage unit can be performed, and FIG.
There is no need to arrange the access control storage unit on the common memory as in the conventional example shown in FIG.

Since there is a semaphore flag in the same interrupt register, the operation of releasing the access right by setting the semaphore flag to "0" in the access right control flow is executed as an interrupt generation process to the interrupt register. Alternatively, since it can be performed simultaneously with the interrupt initialization process, the interrupt process can be simplified.

Further, since the interrupt register is divided for each CPU, the transmitting CPU manages the interrupt generation for each interrupt level, so that the contention of access to one interrupt register can be eliminated and the interrupt factor register is Since the interrupt level is divided according to the interrupt level, the CPU receiving the interrupt (reception CPU) can easily recognize the interrupt factor from the interrupt factor register of the corresponding level.

As described above, according to the present invention, it is possible to realize an inter-CPU interrupt control device corresponding to a plurality of interrupt levels without complicated management of interrupts.

[0035]

EXAMPLE An example of the present invention will be described with reference to FIGS. 4 and 12 to 17.

In this embodiment, as in the above-mentioned conventional example, the CPU (transmission CPU) that makes an interrupt is the CPU (reception C) that is the interrupt destination.
It is configured to perform an interrupt between CPUs by acquiring the bus occupation right of the local bus (PU) and storing the interrupt information. The basic system is shown in FIG. 4, but in the above-mentioned conventional example, an access control storage unit constituted by a semaphore flag is provided on the common memory 20, and the access right control flow shown in FIG. 8 is provided. On the other hand, in the present embodiment, the CPs provided in each local area without providing them
The U-interrupt controller 25 is characterized in that it has an access right control function.

The basic configuration of the system shown in FIG. 4 is the same as that explained in the above-mentioned conventional example, and therefore its explanation is omitted.

As shown in FIG. 12, the inter-CPU interrupt controller 25 comprises a plurality of interrupt registers 33, a plurality of interrupt factor registers 36, an interrupt request section 37 and an address decoder 38.

The interrupt register 33 includes an interrupt storage unit 35 having the same sending CPU and a flag for each interrupt level on the receiving CPU side, and an access control unit (semaphore) 34 for managing storage in the interrupt storage unit 35. It is configured. Then, the inter-CPU interrupt control device 25, as shown in FIG.
PU-2 interrupt register ... An interrupt register group including a CPU-M interrupt register, that is, an interrupt register group provided so as to correspond to each transmitting CPU.

The interrupt factor register 36 is used for each transmitting CPU.
And has a function of collectively reading the contents of the interrupt storage unit 35 for each transmitting CPU for each interrupt level on the receiving CPU side. And CPU
As shown in FIG. 12 and Table 4, the inter-interrupt control device 25 includes an interrupt factor register for interrupt level 1, an interrupt factor register for interrupt level 2, ..., An interrupt factor register for interrupt level N. A factor register group, that is, an interrupt factor register group provided so as to correspond to each interrupt level is provided.

[0041]

[Table 4]

The interrupt request unit 37 is connected to the interrupt storage unit 3
It has a function of requesting an interrupt request to the CPU 21 for each level based on the information of 5.

The address decoder 38 includes the plurality of interrupt registers 33 and the plurality of interrupt factor registers 36.
It has a function of selecting one from among the two to make it accessible.

Table 5 shows the state transition of the interrupt flag in the interrupt storage unit 35. As shown in this table, the flag information after access is the same as the write flag information.

[0045]

[Table 5]

FIG. 13 shows the transmission CPU to the interrupt register 3
3 shows a flowchart for accessing 3. 14
Shows a flowchart for the receiving CPU to access the interrupt factor register 36 and the interrupt register 33.
In these, after acquiring the access right to the interrupt storage unit 35 using the access control storage unit 34,
A storage operation to the interrupt storage unit 35 is being performed. The steps # 31 to # 34b of FIG. 13 and the steps # 41 to # 46b of FIG. 14 are the steps # 31 of FIG.
31 to Step # 34 and Step # 41 to Step #
46, which will be specifically described later with reference to FIG.

FIG. 15 and FIG. 16 more specifically show the structure of this embodiment. Each interrupt register 33 has a total of (N + 1) semaphores and CPU-1 to CPU-N.
Bits connected to the data bus. Each interrupt factor register 36 has a total of M bits for level 1 to level M and is connected to the data bus. Each interrupt factor register 36 is configured so that the contents of the interrupt storage unit 35 for each CPU can be read collectively for each interrupt level of the receiving CPU. For example, the interrupt factor register for interrupt level 1 is a CPU Contents of M bits of the interrupt level 1 flag of the -1 interrupt register, the interrupt level 1 flag of the CPU-2 interrupt register, ..., the interrupt level 1 flag of the CPU-N interrupt register Are collectively read.

The interrupt request unit 37 issues an interrupt request for each interrupt request level based on the information in the interrupt storage unit 35. That is, the interrupt request unit 37 transmits one of the interrupt request signal level 1, the interrupt request signal level 2, ..., And the interrupt request signal level N to the interrupt control unit 23 (FIG. 4). The address decoder 38 selects one of the interrupt registers 33 and the interrupt factor registers 36 based on the address signal from the connected address bus.

Next, based on FIG. 17, CPU-i to CPU
The interrupt operation of -j to the interrupt level k will be described.

First, the CPU-i is a CP which is a receiving CPU.
The bus control right of the U-j local bus is given to the bus control unit 18
(Via Figure 4). Then CPU-i is CPU
CPU of inter-CPU interrupt controller 25 attached to -j
It is confirmed whether the semaphore flag (access control storage unit) 34 of the -i interrupt register 33 is "0", that is, whether the access right is released (step # 3).
1) If it is "0", it is changed to "1" and the access right is acquired (step # 32).

After obtaining the access right, the CPU-i
Access the for-use interrupt register 33. That is, the contents of the interrupt register 33 are read (step # 3
3) Then, the flag for interrupt level K is changed to "1" and the semaphore flag is changed to "0", and the changed contents are written in the interrupt register 33 (step # 34). In this way, the semaphore flag is set to "0" to release the access right.

The interrupt flag for interrupt level k is
The information of "1" is transmitted to the interrupt request unit 37, and the interrupt request unit 37 requests the CPU-j for the interrupt processing of the interrupt level k (step # 35).

The CPU-j recognizes the interrupt request of the interrupt level k (step # 36) and interrupts the current process (step # 37).

Next, the CPU-j reads the interrupt factor register 36 for the interrupt level k (step # 41),
Recognizing that the CPU-i factor flag is "1",
Recognized as an interrupt from CPU-i (step # 4
2).

Then, the CPU-j confirms the semaphore flag 34 of the CPU-i interrupt register 33, and performs the process of acquiring the access right to the interrupt register 33. That is, when the semaphore flag 34 of the CPU-i interrupt register 33 is "0", it is changed to "1" and the access right is acquired (steps # 43, # 4).
4). After acquiring the access right, the CPU-i interrupt register 33 is read (step # 45), the interrupt level k flag is changed to "0" and the semaphore flag is changed to "0", and the CPU-i interrupt register is changed. It is stored in 33 (step # 46).

As a result, the flag for interrupt level k and the semaphore flag of the CPU-i interrupt register 33 are initialized (step # 47). After that, CPU-j
Executes interrupt processing of interrupt level k from CPU-i, and then executes return processing from interrupt processing (steps # 48, # 49).

The processing indicated by a in FIG. 17 (FIGS. 13 and 14)
The same applies to the process indicated by a. ) Is an access that prohibits division, and is realized by using a read-modify-write that does not divide the TAS (test & set) instruction of the CPU.

Inter-CPU interrupt control device 2 described above
Since 5 has an access control storage unit (semaphore flag) 34 in the interrupt register 33 for each transmission CPU, the access right to the interrupt storage unit 35 in its own interrupt register 33 by using the semaphore flag 34. By performing the control flow of, it is not necessary to dispose the access control storage unit on the common memory as in the conventional example shown in FIG. Furthermore, since the semaphore flag of the access control storage unit 34 is in the same interrupt register 33, the semaphore flag in the access right control flow is set to "0".
Since the operation for releasing the access right can be performed simultaneously with the interrupt generation processing or the interrupt initialization processing for the interrupt register 33, the interrupt processing can be simplified. Further, since the interrupt register 33 is divided for each CPU, the transmission CPU manages the interrupt generation for each interrupt level, so that the contention of access to one interrupt register can be eliminated, while the interrupt factor register 3
Since 6 is divided for each interrupt level, the receiving CPU can easily recognize the interrupt factor (the factor that the transmitting CPU belongs to) from the interrupt factor register 36 of the corresponding level.

The basic structure and operation of the inter-CPU interrupt control device of this embodiment have been described above.
By executing the process flow indicated by I and II, it is possible to smoothly perform the process of delivering a large amount of information associated with the interrupt. That is, an information storage unit is provided for each interrupt CPU on the common memory 20 (FIG. 4), and each interrupt register 3
Information can be stored and information can be read out by using the semaphore flag of the access control storage unit 34 of the third embodiment. The process flow indicated by I in FIG. 17 indicates a process (step # 51) of storing information at the time of CPU-i and level k in the common memory 20, and the process flow indicated by II in FIG. 17 is indicated by I. The information written in the process is stored in the common memory 20.
In this process (step # 52), the access right to the information storage unit on the common memory 20 is guaranteed by the semaphore flag of the access control storage unit 34. As described above, the inter-CPU interrupt control device is highly expandable in the transfer of information between CPUs by an interrupt.

[0060]

According to the present invention, the access control storage unit on the common memory and the access right control flow using this access control storage unit, which were required in the conventional example, are not required, so that an interrupt between CPUs is not required. The processing time can be shortened.

Further, according to the present invention, it is possible to easily reduce the contention of access to the interrupt register divided for each CPU, and to simplify the individual interrupt processing to the interrupt register. No, multiple CPUs
C capable of enabling interrupts at multiple levels between
An inter-PU interrupt controller can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first conventional example.

FIG. 2 is a configuration diagram showing a first conventional CPU interrupt control device.

FIG. 3 is an explanatory diagram showing a problem of the first conventional example.

FIG. 4 is a configuration diagram showing a system used in the present invention and a second conventional example.

FIG. 5 is a configuration diagram showing an inter-CPU interrupt control device and an access control storage unit in a second conventional example.

FIG. 6 is a circuit configuration diagram showing an interrupt register and an interrupt request unit in a second conventional example.

FIG. 7 is a flowchart showing an operation of access right control in the second conventional example.

FIG. 8 is a flowchart showing the operation of the inter-CPU interrupt control device in the second conventional example.

FIG. 9 is an explanatory diagram showing flag transitions in the interrupt storage unit in the interrupt register in the second conventional example.

FIG. 10 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 11 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 12 is an internal configuration diagram of an inter-CPU interrupt control device according to an embodiment of the present invention.

FIG. 13 is a flowchart illustrating an operation when accessing the interrupt register from the transmission CPU according to the embodiment of the present invention.

FIG. 14 is a flowchart illustrating an operation when accessing the interrupt factor register and the interrupt register from the receiving CPU in the embodiment of the present invention.

FIG. 15 is a configuration diagram showing an inter-CPU interrupt control device in an embodiment of the present invention.

FIG. 16 is a circuit configuration diagram showing an interrupt register, an interrupt factor register, and an interrupt request unit in the embodiment of the present invention.

FIG. 17 is a flowchart illustrating the operation of the inter-CPU interrupt control device according to the embodiment of the present invention.

[Explanation of symbols]

 21 CPU 33 Interrupt Register 34 Access Control Storage 35 Interrupt Storage 36 Interrupt Factor Register 37 Interrupt Request 38 Address Decoder

Claims (1)

[Claims] 1. An inter-CPU interrupt control attached to each CPU in a system having a plurality of CPUs in a device, and a CPU issuing an interrupt acquires a bus exclusive right of a local bus of the CPU receiving the interrupt and executes an interrupt. In the device, an interrupt register composed of an interrupt storage unit having an interrupt flag of each interrupt level on the CPU side where the interrupting CPU is the same and receiving an interrupt, and an access control unit managing the storage in the interrupt storage unit, CP that interrupts
A CP that corresponds to each of U and is provided with the corresponding number and receives the contents of the interrupt storage unit for each CPU
The interrupt factor registers that can be read collectively for each interrupt level on the U side are provided corresponding to each level and the corresponding number of interrupt factor registers are provided.
An interrupt request unit for requesting an interrupt request to U for each level is provided, and an address decoder is provided to select one of the plurality of interrupt registers and the plurality of interrupt factor registers to make it accessible. The interrupt register is configured to be accessed for each CPU that issues an interrupt, and the storage operation for the interrupt storage unit is managed by the information of the access control unit in the interrupt register corresponding to the CPU that issues the interrupt. Inter-CPU interrupt controller.