JP3049125B2 - CPU interrupt controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a numerical controller for a laser beam machine or the like, and uses a plurality of CPUs in a device and uses an interrupt to exchange information between the CPUs. And an interrupt control device between a plurality of CPUs.

[0002]

2. Description of the Related Art In recent years, in a device using a microcomputer, an increase in the amount of information in the device and a high-speed processing have been demanded.
There is an increasing number of distributed systems in which U is assigned a function having individual characteristics, and information is exchanged between CPUs to constitute the entire system.

FIG. 1 shows a known system for exchanging information between CPUs in a large amount and at a high speed in a device using a microcomputer of such a distributed system.

In the conventional example shown in FIG. 1, an interrupt control unit provided for each CPU 5 includes an interrupt generation unit 9 for generating an interrupt and an interrupt reception unit for receiving an interrupt generated from another CPU 5. A part 10. As shown in FIG. 2, the interrupt receiving unit 10 has an interrupt receiving register 15 composed of a large number of interrupt flags 16 so as to be able to respond to the occurrence of interrupts of all the other CPUs 5.
And an interrupt request unit 17 that issues an interrupt request to its own CPU 5. Also, the interrupt generation unit 9
Has a large number of interrupt generating units for each CPU so as to be able to respond to the interrupt reception of all the CPUs 5 of the other party. As shown in FIG. 2, the interrupt generating units for each CPU and the interrupt flags 16 corresponding thereto are provided. Are connected one by one, and are connected by an interrupt request line 13.

However, according to this conventional example, as the number of CPUs 5 performing interrupt communication between CPUs 5 increases, the number of interrupt request lines 13 increases geometrically.

That is, assuming that the number of CPUs 5 is M, the number W of the interrupt request lines 13 is expressed by equation (1).

W = M × (M 1) (1) FIG. 3 (a) shows a case where the number of CPUs 5 is four. Is 12 lines. FIG. 3B shows a case where the number of CPUs 5 is five. In this case, the number of interrupt request lines 13 is 20.
It becomes a book.

In the above case, the interrupt level was not taken into account. However, in many cases, the interrupt level must be taken into consideration. In the case where there are N levels of interrupt levels, the interrupt request line The number W of thirteen is expressed as in equation (2).

W = N × M × (M 1) (2) Therefore, for example, the number of CPUs 5 is four, and the interrupt level is seven.
In the case of the stage, the number of the interrupt request lines 13 becomes as many as 84. As described above, in the above conventional example, the CPU 5
When the number of interrupt request lines 13 increases, the number of interrupt request lines 13 extremely increases. In particular, in addition to the increase in the number of CPUs 5, there is a problem that it becomes virtually impossible to cope with the increase in the number of interrupt levels. I have.

As a conventional example which solves such a problem, there is a conventional example shown in FIGS.

In this conventional example, the interrupting CPU acquires the right to occupy the local bus of the interrupting CPU, and executes interrupts between CPUs by storing interrupt information.

As shown in FIG. 4, a bus controller 18, a buffer 19, a memory 22, an interrupt controller 23, an I / O 24, an inter-CPU interrupt controller 2
5 are provided. The inter-CPU interrupt control device 25
5 shows an interrupt register 2 having an interrupt storage unit 30 having an individual interrupt flag configuration for each CPU, as shown in FIG.
9 and an interrupt request unit 31. The internal structure of the interrupt register 29 is as shown in Table 1. Table 2 is a state transition table of the interrupt flag in the interrupt register 29. FIG. 6 shows the interrupt register 29 and the interrupt request unit 3
1 shows one example of the circuit configuration of FIG.

[0013]

[Table 1]

[0014]

[Table 2]

As shown in FIG. 4 and FIG.
And a common memory 20 for storing management information for managing individually accessing the interrupt register 29 located on the local memory. The common memory 20 has an access control storage unit 32 for an interrupt register. The access control storage unit 32 has a semaphore flag corresponding to each interrupt register 29, as shown in Table 3.

[0016]

[Table 3]

Next, an interrupt operation between CPUs in the above-mentioned conventional example will be described. Since the interrupt register 29 of the inter-CPU interrupt control device 25 attached to each CPU 21 has an interrupt flag corresponding to all the other CPUs 21,
There is a possibility that accesses from the PU 21 may be mixed. Therefore, the interrupt generation processing by the other CPU 21 and its own C
It is necessary to guarantee a series of read and write accesses to the interrupt register 29 in the interrupt reception processing by the PU 21. For this guarantee, the access control storage unit 32 on the common memory 20 stores the interrupt register 29 of each CPU 21. It is configured to have semaphore flags as many as the number of interrupt registers 29 in order to individually manage access rights.
Thus, the access right is controlled.

FIG. 7 is a flowchart showing the control of the access right. The CPU requesting the interrupt accesses the interrupt register access control storage unit 32 on the common memory 20 and determines whether or not the semaphore flag corresponding to the interrupt register 29 of the other CPU is “0”.
When this is "1", since the other CPU has acquired the access right, it waits for release of the access right of the other CPU (step # 1). When this is "0", "1" is written in the corresponding semaphore flag to acquire the access right, and this is notified to other CPUs (step # 2). Then, a series of processing for the corresponding interrupt register 29 is performed (step # 3), and immediately thereafter, the semaphore flag is set to “0”.
And release the access right (step # 4).

FIG. 8 shows a flowchart when an interrupt is issued from the i-th CPU (CPU-i) to the j-th CPU (CPU-j). CP requesting interrupt
Ui is the interrupt register 2 of the partner CPU-j.
9 for the semaphore flag corresponding to No. 9 according to the access right control flow (step # 1).
1, # 12). Next, the CPU-i accesses the interrupt register 29 in the local area of the CPU-j, reads its contents, and then changes only its own interrupt flag for CPU-i to "1" (steps # 13, # 1).
4). Based on that information, the interrupt request unit 31
, Via the interrupt control unit 23 (see FIG. 5, step # 16). At the same time, the CPU-i sets the semaphore flag to “0” and sets the interrupt register 2
Release the access right to No. 9 (step # 15).

The CPU-j which has received the interrupt request recognizes the interrupt request, interrupts the current process (steps # 17 and # 18), and then executes the C process in the common memory 20.
The access right is acquired for the semaphore flag for the interrupt register of PU-j according to the flow of access right control (see FIG. 7) (steps # 19 and # 20). By reading the interrupt register 29, the CPU-i requesting the interrupt is recognized (steps # 21 and # 2).
2). Further, only the interrupt flag corresponding to the CPU-i requesting the interrupt is changed to "0" to initialize the interrupt factor (steps # 23 and # 24). Finally, CPU-
j is set to “0” for the interrupt register semaphore flag,
After releasing the access right of the interrupt register and executing a process corresponding to the interrupt, a return process from the interrupt process is performed (steps # 25, # 26, and # 27).

In FIG. 7 and FIG. 8, the processing indicated by a is an access for inhibiting the division, and it is necessary to guarantee this in hardware. One way to do this is to use T
There is a method of guaranteeing the prohibition of division by having an AS (test and set) instruction.

The process indicated by b indicates the access right control flow of FIG.

[0023]

The conventional example shown in FIG.
As described above, an access control storage unit is provided on the common memory in order to guarantee a series of accesses relating to the interrupt generation process by another CPU and the interrupt reception process by its own CPU. Semaphore flags individually corresponding to the respective interrupt registers, and the access right control flow needs to be performed.
This access right control flow has a problem that it is complicated and requires a long processing time.

If the number of CPUs is M and the interrupt level is N stages, the number of the semaphore flags is (M × N)
There is also a problem that the number increases extremely and the management of access rights becomes complicated.

If the access control storage unit 32 for the interrupt register shown in FIG. 5 is omitted and the access right control flow shown in FIG. 8B is omitted, the following inconvenience occurs.

FIG. 9 shows a case where the CPU-
2 shows a transition of an interrupt flag in an interrupt register in an inter-CPU interrupt control device attached to a receiving-side CPU when an interrupt request is generated by the CPU 2. In the case shown in FIG. 9, the prohibition of access by other CPUs is guaranteed during the period indicated by P and Q, and an interrupt request is issued only to CPU-2, so that normal processing is performed. However, it is difficult to guarantee the P and Q in terms of hardware. If the P and Q are not guaranteed, interrupt requests from a plurality of CPUs are mixed and normal processing is not performed as shown in FIGS. Invite the situation.

FIG. 10 shows a case where CPU-2 and CPU-M request an interrupt to the same interrupt register. In this case, the prohibition period of P shown in FIG.
PU-2 and subsequently CPU-M read the interrupt register, and then CPU-2
After the flag for CPU-2 becomes "1", the flag for CPU-2 becomes "0" by writing of CPU-M,
The M flag becomes "1" (see Table 2), and C
There is a disadvantage that the interrupt request of PU-2 disappears.

FIG. 11 shows a case where an interrupt request is issued from the CPU-M while the receiving CPU recognizes the interrupt from the CPU-2. In this case, the prohibition period of Q shown in FIG. 9 is not guaranteed, and the receiving CPU and the subsequent CPU
−M reads the interrupt register, then changes the flag for CPU-2 to “0” by writing to the receiving CPU and initializes the interrupt factor, and then writes the flag for CPU-2 and the CPU by writing to CPU-M. As a result, the flag for -M is set to "1" (see Table 2), so that the flag for CPU-2 is returned to "1", which causes an inconvenience that a double interrupt occurs.

The present invention solves the above-mentioned problems of the prior art and can cope with a plurality of interrupt levels.
It is an object of the present invention to provide an interrupt control device.

[0030]

In order to achieve the above object, the present invention has a plurality of CPUs in a device, and an interrupting CPU acquires a bus occupation right of a local bus of an interrupting CPU by interrupting the CPU. CP in the system that performs
The CPU-to-CPU interrupt control device attached to U is provided with an interrupt storage unit for storing interrupt information for each interrupting CPU and each interrupt level. An interrupt transmission register having an interrupt flag of an interrupt level and having an interrupt generation information creating section for creating interrupt occurrence information based on the information in the interrupt storage section and the write information is provided so as to correspond to each of the CPUs that interrupts. An interrupt that has the same interrupt level as that of the CPU that receives the interrupt, has an interrupt flag from the CPU that issues each interrupt, and initializes the interrupt based on the information in the interrupt storage unit and the write information. An interrupt reception register having an initialization information generating section is provided by the number corresponding to each of the interrupt levels. An interrupt request unit for requesting an interrupt request to the CPU for each level based on the information in the storage unit, and selecting and accessing one of the plurality of interrupt transmission registers and the plurality of interrupt reception registers An address decoder for enabling the interrupt is provided, and the interrupt transmitting side and the interrupt receiving side can separately access the same interrupt storage unit.

[0031]

According to the present invention, it is possible to eliminate the danger that an interrupt flag of another interrupt level is erroneously initialized without having a function of initializing an interrupt in the interrupt generation information creating section of the interrupt transmission register. CPU that does not have an interrupt generation function in the interrupt initialization information creation section of the interrupt reception register
Since the risk of generating an interrupt in the interrupt flag for use can be eliminated and the control of the access right to the interrupt register becomes unnecessary, the access control storage unit is stored on the common memory as in the conventional example shown in FIG. Need to be placed.

Further, since the interrupt transmitting side and the interrupt receiving side can access the same interrupt storage section separately, the configuration is simplified.

As described above, according to the present invention, it is possible to realize an interrupt control device between CPUs corresponding to a plurality of interrupt levels without complicating the management of the interrupt.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

In this embodiment, similarly to the above-described conventional example, the CPU that issues the interrupt (the transmitting CPU) is the CPU (the receiving C) that is the interrupt destination.
The PU is configured so as to execute an interrupt between CPUs by acquiring the bus occupation right of the local bus and storing interrupt information. The basic system is shown in FIG. 4, but in the above-mentioned conventional example, an access control storage section composed of a semaphore flag is provided on the common memory 20, and the access right control flow shown in FIG. On the other hand, in the present embodiment, these are not provided, and the CPs provided in each local area are not provided.
It is characterized in that the U-to-U interrupt controller 25 has an access right control function.

The basic configuration of the system shown in FIG. 4 is the same as that described in the above-mentioned conventional example, and the description is omitted.

As shown in FIG. 12, the CPU-to-CPU interrupt controller 25 includes an interrupt storage 37, an interrupt transmission register 3,
3, an interrupt reception register 35, an interrupt request unit 38, and an address decoder 39.

The interrupt storage unit 37 is configured to store interrupt information for each transmitting CPU and each interrupt level.

As shown in FIG. 12 and Table 4, the interrupt transmitting register 33 has the same transmitting CPU and has an interrupt flag for each interrupt level on the receiving CPU side.
7 and an interrupt occurrence information creating section 34 for creating interrupt occurrence information based on the write information. As shown in Table 4, the inter-CPU interrupt control device 25 generates an interrupt including a CPU-1 interrupt transmission register, a CPU-2 interrupt transmission register,..., A CPU-M interrupt transmission register. A transmission register group, that is, an interrupt transmission register group provided for each transmission CPU is provided.

As shown in FIG. 12 and Table 4, the interrupt reception register 35 has the same interrupt level of the receiving CPU and has an interrupt flag for each transmitting CPU.
7 and an interrupt initialization information creating unit 36 for initializing an interrupt based on the write information. And C
As shown in Table 4, the inter-PU interrupt control device 25 includes an interrupt receiving register for an interrupt level 1 interrupt receiving register, an interrupt level 2 interrupt receiving register,..., An interrupt level N interrupt receiving register. Group, that is, a group of interrupt reception registers provided so as to correspond to each interrupt level.

[0041]

[Table 4]

The interrupt request unit 38 stores the interrupt storage unit 3
The CPU 21 has a function of requesting the CPU 21 to request an interrupt for each level based on the information of the CPU 7.

The address decoder 39 has a function of selecting one of the plurality of interrupt transmission registers 33 and the plurality of interrupt reception registers 35 to make them accessible.

The interrupt transmitting register 33 is accessed by the transmitting CPU 21 and the interrupt receiving register 35 is accessed.
Are registered so that the CPU 21 on the receiving side accesses them, and the respective registers 33 and 35 perform processing for the interrupt storage unit 37 that they have in common.

As described above, the interrupt transmission register 33 accessed by the transmission CPU 21 is divided for each CPU, and each register includes an interrupt flag for each interrupt level, so that the transmission CPU 21 is assigned to itself. Interrupt transmission register 33 (for example, when the transmission CPU
If it is PU-1, access the interrupt transmission register for CPU-1 (see Table 4), and a flag for the corresponding interrupt level (for example, if the interrupt level is 1, C
The interrupt level can be managed by setting the flag for interrupt level 1 of the interrupt transmission register for PU-1 (see Table 4) to "1". Also, each interrupt transmission register 33 has an interrupt occurrence information creating unit 34, and the information stored in the interrupt storage unit 37 is modified by the interrupt occurrence information creating unit 34 as shown in the state transition table of Table 5. That is, writing “0” to the interrupt flag does not change the internal information,
When writing "1", the internal information is set to "1". The writing of "1" is performed only on the flag of the level that generates an interrupt, and the writing of "0" which does not change the internal information is performed on the flags of the other interrupt levels. Is “0” and “1” when “1”
And the retention of internal information is guaranteed. As described above, since the interrupt occurrence information creating unit 34 does not have a function of initializing an interrupt, there is no danger of erroneously initializing a flag of another interrupt level.

[0046]

[Table 5]

As described above, the interrupt receiving register 35 accessed by the receiving CPU 21 is divided for each interrupt level, and each register is constituted by an interrupt flag for each transmitting CPU, so that the receiving CPU 21 is interrupted. The interrupt receiving register 35 (for example, if the interrupt level is 1, the interrupt receiving register for interrupt level 1-see Table 4) is accessed, and the corresponding transmission CPU is accessed.
Flag (for example, if the transmitting CPU is CPU-1, CPU-1 of the interrupt receiving register for interrupt level 1)
Read the interrupt flag for use-see Table 4) or "0"
By performing initialization, the transmission CPU can be managed. Each interrupt receiving register 35 has an interrupt initialization information creating unit 36, and information stored in the interrupt storage unit 37 is
The state is modified by the interrupt initialization information creating unit 36 as shown in the state transition table of Table 6. That is, the internal information is not changed when "0" is written to the interrupt flag, and the internal information is set to "0" when "1" is written. The writing of "1" is performed only for the flag for the transmitting CPU for initializing the interrupt, and the other flags for the transmitting CPU are written with "0" which does not change the internal information. When it is "0", it is "0", and when it is "1", it is "1", and the retention of internal information is guaranteed. As described above, since the interrupt initialization information creating unit 36 does not have a function of generating an interrupt, there is no danger of erroneously setting a flag for another transmission CPU to “1”.

[0048]

[Table 6]

FIG. 13 is a flowchart for accessing the interrupt transmission register 33 from the transmission CPU 21. That is, the transmission CPU 21 generates an interrupt by writing "1" only to the corresponding interrupt level flag of the CPU interrupt transmission register 33.

FIG. 14 is a flowchart for accessing the interrupt reception register 35 from the reception CPU 21. That is, the receiving CPU 21 reads the interrupt receiving register 35 for the corresponding interrupt level, recognizes what the transmitting CPU is, and then writes “1” only in the interrupt flag for the CPU recognized by the interrupt receiving register 35 to initialize. Become

FIGS. 15 and 16 show the structure of this embodiment more specifically. The interrupt generation information creating unit 34 in the interrupt transmission register 33 has a data bus and an output of the interrupt storage unit 37 as inputs, is formed by a logical sum, and is connected to the interrupt storage unit 37. The interrupt initialization information creating unit 36 in the interrupt receiving register 35 has a data bus and an output of the interrupt storage unit 37 as inputs, and issues a clear signal to the interrupt storage unit 37 only when the interrupt is “1” and “1”. It is connected to the. The interrupt storage unit 37 is connected to the data bus and the buffer via the interrupt transmission register 33 and the interrupt reception register 35, and its internal information can be read. Interrupt request unit 38
In the configuration shown in FIG. 15, the output of the interrupt storage unit 37 is ORed for each interrupt level, and an interrupt request is issued to the CPU 21 for each interrupt level.

Next, based on FIG.
A description will be given of the operation of interrupting the −j interrupt level k.

First, the CPU-i is a receiving CPU CP.
The bus exclusive right of the local bus of Uj is transferred to the bus control unit 18.
(FIG. 4). Next, CPU-i is CPU
CPU of the inter-CPU interrupt control device 25 attached to -j
Only the interrupt level k flag of the −i interrupt transmission register 33 is written to “1”. Interrupt generation information creation unit 3
Reference numeral 4 designates only the flag for the interrupt level k as "1" and latches "1" at the end of the write operation, so that the interrupt storage unit 3
7 is stored in the interrupt flag for interrupt level k (step # 31).

The interrupt storage unit 37 transmits the information of the interrupt to the interrupt request unit 38, and the interrupt request unit 38
Request the interrupt processing of the interrupt level k (step #)
32).

The CPU-j recognizes the interrupt request of the interrupt level k (step # 33), and interrupts the current processing (step # 34).

Next, the CPU-j reads the interrupt reception register 35 for the interrupt level k (step # 35),
It recognizes that the interrupt flag for CPU-i is "1" and recognizes it as an interrupt from CPU-i (step # 3).
6).

Then, the CPU-j sets only the CPU-i flag of the interrupt reception register 35 for the interrupt level k to "1" and writes it (step # 37). The interrupt initialization information creating unit 36 inverts only the CPU-i flag to “0” and initializes the interrupt flag for the CPU-i and the interrupt level k in the interrupt storage unit 37 (step # 3).
8).

Thereafter, the CPU-j executes an interrupt process of the interrupt level k from the CPU-i, and then executes a return process from the interrupt process (steps # 39 and # 4).
0).

The CPU-to-CPU interrupt controller 2 described above
In No. 5, since the control of the access right to the interrupt register is not required, it is not necessary to arrange the access control storage unit on the common memory as in the conventional example shown in FIG.

The basic configuration and operation of the CPU-to-CPU interrupt control apparatus of this embodiment have been described above.
By executing the processing flows indicated by I and II, it is possible to smoothly perform a process of transferring a large amount of information accompanying the interrupt. That is, an information storage unit is provided for each interrupt CPU and each interrupt level on the common memory 20 (FIG. 4), and information storage and information read processing are executed by using an interrupt flag in each interrupt storage unit 37. it can. FIG.
The process flow indicated by I is a process of storing information at the time of CPU-i and level k in the interrupt control device 25 of CPU-j on the common memory 20 (steps # 41 and # 4).
The process flow indicated by II in FIG. 17 is a process of reading the information written by the process indicated by I from the common memory 20 (step # 51). The access right to the storage unit is guaranteed by the interrupt flag in the interrupt storage unit 37. As described above, the CPU-to-CPU interrupt control device uses the C
It is rich in information transfer between PUs.

[0061]

According to the present invention, the access control storage unit on the common memory and the access right control flow using this access control storage unit, which are required in the conventional example, are not required, so that the interrupt between CPUs is eliminated. Processing time can be shortened.

Further, according to the present invention, an interrupt between CPUs capable of enabling interrupts at a plurality of levels among a plurality of CPUs even though interrupt processing and management can be easily performed without controlling access rights. A control device can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first conventional example.

FIG. 2 is a configuration diagram showing a first conventional example of an inter-CPU interrupt control device.

FIG. 3 is an explanatory diagram showing a problem of the first conventional example.

FIG. 4 is a configuration diagram showing a system used in the present invention and a second conventional example.

FIG. 5 is a configuration diagram showing an interrupt control device between CPUs and an access control storage unit in a second conventional example.

FIG. 6 is a circuit configuration diagram showing an interrupt register and an interrupt request unit in a second conventional example.

FIG. 7 is a flowchart showing an operation of access right control in a second conventional example.

FIG. 8 is a flowchart showing the operation of the CPU-to-CPU interrupt control device in the second conventional example.

FIG. 9 is an explanatory diagram showing a flag transition in an interrupt storage unit in an interrupt register in the second conventional example.

FIG. 10 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 11 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 12 is an internal configuration diagram of an interrupt control device between CPUs in an embodiment of the present invention.

FIG. 13 is a flowchart illustrating an operation when the transmission CPU accesses the interrupt transmission register according to the embodiment of the present invention.

FIG. 14 is a flowchart illustrating an operation when an interrupt reception register is accessed from a reception CPU according to the embodiment of the present invention.

FIG. 15 is a configuration diagram showing an interrupt control device between CPUs in an embodiment of the present invention.

FIG. 16 is a circuit diagram showing an interrupt transmission register and an interrupt reception register according to the embodiment of the present invention.

FIG. 17 is a flowchart for explaining the operation of the inter-CPU interrupt control device according to the embodiment of the present invention.

[Explanation of symbols]

 21 CPU 33 Interrupt transmission register 34 Interrupt generation information creation unit 35 Interrupt reception register 36 Interrupt initialization information creation unit 37 Interrupt storage unit 38 Interrupt request unit 39 Address decoder

Continuation of the front page (56) References JP-A-3-100853 (JP, A) JP-A-61-264467 (JP, A) JP-A-63-292362 (JP, A) JP-A-3-257652 (JP) JP-A-64-46155 (JP, A) JP-A-63-59649 (JP, A) National Technical Report VOL. 36, NO. 2 pp. 155-159 1990 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/177 676 G06F 9/46 360 G06F 13/24 310 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. An interrupt control between CPUs attached to each CPU in a system having a plurality of CPUs in a device, wherein a CPU that issues an interrupt acquires a bus occupation right of a local bus of the interrupted CPU and performs an interrupt. The apparatus further comprises an interrupt storage unit for storing interrupt information for each interrupting CPU and each interrupt level, wherein the interrupting CPU has an interrupt flag for each interrupt level of the CPU that receives the interrupt. Based on the information in the interrupt storage unit and the write information, an interrupt transmission register having an interrupt generation information generation unit that generates interrupt generation information is provided for each of the interrupting CPUs by the corresponding number. The interrupt level of the receiving CPU side is the same, and an interrupt flag from the CPU that issues each interrupt is provided. An interrupt receiving register having an interrupt initializing information creating section for initializing an interrupt based on information and write information is provided by the number corresponding to each of the interrupt levels, and the information of the interrupt storing section is also provided. An address requester for requesting an interrupt request to the CPU for each level, and selecting one of the plurality of interrupt transmission registers and the plurality of interrupt reception registers to be in an accessible state. An interrupt control device between CPUs, wherein the interrupt transmitting side and the interrupt receiving side can separately access the same interrupt storage unit.