JPH0554001A - Inter-cpu interruption controller - Google Patents

Abstract

PURPOSE:To provide an inter-CPU interrupt controller which shortens the processing time of inter-CPU interruption and simplifies the interruption handling and is capable of interrupts in plural levels among plural CPUs. CONSTITUTION:An interruption storage part 37 where interrupt information classified by interruption source CPUs and interruption levels is stored is provided. The same number or transmission registers 33, which have interruption generation information generating parts 34 having interruption flags of interruption levels of interruption destination CPUs for the same interruption source CPUs and generating interruption generation information based on information in the interruption storage part 37 and write information, as CPUs are provided correspondingly to individual interruption source CPUs. The same number of interruption reception registers 35, which have interruption initialization information generating parts 36 having interruption flags of interruption source CPUs for the same interruption levels of interruption destination CPUs and initialize the interruption based on information in the interruption storage part 36 and write information, as interruption levels are provided correspondingly to individual interruption levels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a numerical control device for a laser beam machine, etc., and uses a plurality of CPUs in the equipment, and uses an interrupt to execute information exchange between the CPUs. And an interrupt control device between a plurality of CPUs.

[0002]

2. Description of the Related Art In recent years, in devices using microcomputers, an increase in the amount of information in the devices and a high processing speed are demanded, and a plurality of CPUs are used to control each CP.
There is an increasing number of distributed systems in which the U is individually assigned a function having a characteristic and information is exchanged between the CPUs to configure the entire system.

In a device using such a distributed system microcomputer, a system shown in FIG. 1 is known as a system for exchanging information between CPUs in a large amount at high speed.

In the conventional example shown in FIG. 1, an interrupt control device provided for each CPU 5 receives an interrupt generation unit 9 for generating an interrupt and an interrupt reception for receiving an interrupt generated by another CPU 5. And a section 10. As shown in FIG. 2, the interrupt receiving unit 10 includes an interrupt receiving register 15 including a large number of interrupt flags 16 so as to be able to respond to the interrupt generation of all the CPUs 5 of the other party.
And an interrupt request unit 17 which issues an interrupt request to its own CPU 5. Also, the interrupt generation unit 9
Has a large number of interrupt generation units for each CPU so as to be able to handle the interrupt reception of all the CPUs 5 of the other party. As shown in FIG. 2, the interrupt generation units for each CPU and the interrupt flags 16 corresponding thereto are provided. And are in a one-to-one correspondence, and are connected by the interrupt request line 13.

However, according to this conventional example, when the number of CPUs 5 for performing interrupt communication between the CPUs 5 increases, the number of interrupt request lines 13 increases geometrically.

That is, assuming that the number of CPUs 5 is M, the number W of interrupt request lines 13 is represented by the equation (1).

W = M × (M 1) (1) FIG. 3A shows the case where the number of CPUs 5 is four. In this case, the interrupt request line 13 Will be 12. Further, FIG. 3B shows a case where the number of CPUs 5 is 5, but in this case, the number of interrupt request lines 13 is 20.
It will be a book.

In the above case, the interrupt level was not taken into consideration, but in many cases the interrupt level must actually be taken into consideration. If there are N levels of interrupt levels, the interrupt request line The number W of 13 is expressed as in equation (2).

W = N × M × (M 1) (2) Therefore, for example, the number of CPUs 5 is 4 and the interrupt level is 7
In the stage, the number of interrupt request lines 13 becomes 84. As described above, in the conventional example described above, the CPU 5
The number of interrupt request lines 13 increases extremely as the number of interrupts increases, and in particular, when the number of interrupt levels increases in addition to the increase in the CPU 5, there is a problem that it is practically impossible to deal with this. There is.

As a conventional example that solves such a problem, there are conventional examples shown in FIGS.

In this conventional example, the interrupting CPU obtains the exclusive right of the local bus of the interrupt destination CPU and stores the interrupt information to perform the interrupt between the CPUs.

As shown in FIG. 4, corresponding to each CPU 21, a bus control unit 18, a buffer 19, a memory 22, an interrupt control unit 23, an I / O 24, and an inter-CPU interrupt control device 2 are provided.
5 are provided. Inter-CPU interrupt controller 25
Is an interrupt register 2 having an interrupt storage unit 30 having an individual interrupt flag configuration for each CPU, as shown in FIG.
9 and an interrupt request unit 31. The internal structure of the interrupt register 29 is shown in Table 1. Table 2 is a state transition table of the interrupt flag in the interrupt register 29. FIG. 6 shows the interrupt register 29 and the interrupt request unit 3.
1 shows an example of a circuit configuration of 1.

[0013]

[Table 1]

[0014]

[Table 2]

As shown in FIGS. 4 and 5, each CPU 21
There is provided a common memory 20 for storing management information for managing the individual access to the interrupt register 29 which is locally present. The common memory 20 has an interrupt register access control storage unit 32. The access control storage unit 32, as shown in Table 3, has a semaphore flag corresponding to each interrupt register 29.

[0016]

[Table 3]

Next, the interrupt operation between the CPUs of the above conventional example will be described. Since the interrupt register 29 of the inter-CPU interrupt control device 25 attached to each CPU 21 has an interrupt flag corresponding to all the other CPUs 21, each C
Access from the PU 21 may be mixed. For this reason, the interrupt generation processing by the other CPU 21 and its own C
It is necessary to guarantee a series of read and write access to the interrupt register 29 in the interrupt reception processing by the PU 21, and for this guarantee, the access control storage unit 32 on the common memory 20 stores the interrupt register 29 of each CPU 21. In order to individually manage the access right, it is configured to have semaphore flags for the number of interrupt registers 29,
This controls the access right.

FIG. 7 is a flowchart showing the control of the access right. The CPU requesting the interrupt accesses the interrupt register access control storage unit 32 on the common memory 20, determines whether the semaphore flag corresponding to the interrupt register 29 of the other CPU is “0”,
When this is "1", the other CPU has acquired the access right, and therefore waits for the release of the access right of the other CPU (step # 1). When it is "0", "1" is written in the corresponding semaphore flag to acquire the access right, and this is notified to the other CPU (step # 2). Then, a series of processing to the corresponding interrupt register 29 is performed (step # 3), and immediately thereafter, the semaphore flag is set to "0".
To release the access right (step # 4).

FIG. 8 shows a flow chart when the interrupt from the i-th CPU (CPU-i) to the j-th CPU (CPU-j) is performed. CP requesting an interrupt
U-i is the interrupt register 2 of the CPU-j on the other side.
The access right is acquired for the semaphore flag corresponding to 9 according to the access right control flow (step # 1).
1, # 12). Next, the CPU-i accesses the interrupt register 29 in the local area of the CPU-j, reads the contents, and then changes only its own interrupt flag for the CPU-i to "1" (steps # 13, # 1).
4). Based on this information, the interrupt request unit 31 determines that the CPU-j
An interrupt request is issued via the interrupt controller 23 (see FIG. 5, step # 16). At the same time, the CPU-i sets the semaphore flag to "0", and the interrupt register 2
The access right to 9 is released (step # 15).

The CPU-j on the side requested to interrupt recognizes the interrupt request, interrupts the current process (steps # 17, # 18), and then C in the common memory 20.
The access right is acquired in accordance with the access right control flow (see FIG. 7) for the semaphore flag for the interrupt register of PU-j (steps # 19, # 20). Then, by reading the interrupt register 29, the CPU-i requesting the interrupt is recognized (steps # 21 and # 2).
2). Further, only the interrupt flag corresponding to the CPU-i which has requested the interrupt is changed to "0" to initialize the interrupt factor (steps # 23, # 24). Finally CPU-
Set the interrupt register semaphore flag of j to "0",
The access right of the interrupt register is released, the process corresponding to the interrupt is executed, and then the process of returning from the interrupt process is executed (steps # 25, # 26, # 27).

In FIG. 7 and FIG. 8, the processing indicated by a is access that prohibits division, and it is necessary to guarantee this in terms of hardware. As one method for this, T
There is a method of guaranteeing division prohibition by having an AS (test and set) instruction.

The process indicated by b shows the access right control flow of FIG.

[0023]

The conventional example shown in FIG.
As described above, in order to guarantee a series of accesses relating to interrupt generation processing by another CPU and interrupt reception processing by its own CPU, an access control storage unit is provided on the common memory, and this access control storage unit is local to each CPU. It was necessary to configure the interrupt register of semaphore flag individually and perform the access right control flow.
The access right control flow is complicated and the processing time is long.

If the number of CPUs is M and the interrupt level is N stages, the number of semaphore flags is (M × N).
There is also a problem that the number of individuals becomes extremely large, and the management of access rights becomes complicated.

If the interrupt register access control storage unit 32 shown in FIG. 5 is omitted and the access right control flow shown in FIG. 8B is omitted, the following inconvenience occurs.

FIG. 9 shows the CPU-
2 shows the transition of the interrupt flag in the interrupt register in the inter-CPU interrupt control device attached to the receiving CPU when the interrupt request is generated. In the case shown in FIG. 9, since the prohibition of access by the other CPUs is guaranteed and the interrupt request of only the CPU-2 occurs during the period shown by P and Q, normal processing is performed. However, it is difficult to guarantee P and Q by hardware, and if this is not guaranteed, interrupt requests from a plurality of CPUs are mixed and normal processing is not performed as shown in FIGS. 10 and 11. Cause a situation.

FIG. 10 shows a case where the CPU-2 and the CPU-M request an interrupt to the same interrupt register. In this case, the prohibited period of P shown in FIG.
The PU-2 and, subsequently, the CPU-M read the interrupt register, and then write to the CPU-2 to
-2 flag becomes "1", then CPU-M write causes the CPU-2 flag to become "0",
The M flag becomes "1" (see Table 2), and C
The inconvenience that the interrupt request of PU-2 disappears occurs.

FIG. 11 shows a case where an interrupt request is issued from CPU-M while the receiving CPU recognizes the interrupt from CPU-2. In this case, the prohibited period of Q shown in FIG. 9 is not guaranteed, and the receiving CPU and the CPU subsequent to this are not guaranteed.
-M reads the interrupt register and then writes the receiving CPU to change the CPU-2 flag to "0" to initialize the interrupt factor. Then, write CPU-M to the CPU-2 flag and CPU. As a result of the -M flag being set to "1" (see Table 2), the CPU-2 flag is returned to "1", resulting in a double interrupt.

The present invention solves the above-mentioned problems of the conventional example and enables a CPU up to a plurality of interrupt levels.
An object is to provide an inter-interruption control device.

[0030]

In order to achieve the above object, the present invention has a plurality of CPUs in a device, and the interrupting CPU acquires the bus exclusive right of the local bus of the CPU that receives the interrupt and interrupts. CP in the system
The inter-CPU interrupt control device attached to the U has an interrupt storage unit for storing interrupt information for each CPU that makes an interrupt and for each interrupt level, and the CPUs that make an interrupt are the same An interrupt transmission register having an interrupt flag of an interrupt level and having an interrupt occurrence information creation unit for creating interrupt occurrence information based on the information in the interrupt storage unit and write information is made to correspond to each of the CPUs that make an interrupt. An interrupt which has the corresponding number of interrupts, has the same interrupt level on the side of the CPU that receives the interrupt, has an interrupt flag from the CPU that issues each interrupt, and initializes the interrupt based on the information in the interrupt storage section and the write information. An interrupt reception register having an initialization information creation unit is provided in the corresponding number so as to correspond to each interrupt level. An interrupt request unit for requesting an interrupt request to the CPU for each level based on the information in the storage unit is provided, and one of the plurality of interrupt transmission registers and the plurality of interrupt reception registers is selected and accessed. The present invention is characterized in that it is provided with an address decoder for enabling it, and that the interrupt transmitting side and the interrupt receiving side can separately access the same interrupt storage section.

[0031]

According to the present invention, the interrupt generation information creation unit of the interrupt transmission register does not have the function of initializing an interrupt, and the risk of accidentally initializing an interrupt flag of another interrupt level can be eliminated. In addition, the CPU that does not have a function for generating an interrupt in the interrupt initialization information creation unit of the interrupt reception register and accidentally issues another interrupt
Since there is no need to control the access right to the interrupt register because there is no danger of generating an interrupt in the interrupt flag for use in the access control storage unit on the common memory as in the conventional example shown in FIG. Eliminates the need to place

Further, since the interrupt transmitting side and the interrupt receiving side can separately access the same interrupt storing section, the structure is simplified.

As described above, according to the present invention, it is possible to realize an inter-CPU interrupt control device corresponding to a plurality of interrupt levels without complicated management of interrupts.

[0034]

EXAMPLE An example of the present invention will be described with reference to FIGS. 4 and 12 to 17.

In this embodiment, as in the above-mentioned conventional example, the CPU (transmission CPU) that makes an interrupt is the CPU (reception C) at the interruption destination.
It is configured to perform an interrupt between CPUs by acquiring the bus occupation right of the local bus (PU) and storing the interrupt information. The basic system is shown in FIG. 4, but in the above-mentioned conventional example, an access control storage unit constituted by a semaphore flag is provided on the common memory 20, and the access right control flow shown in FIG. 8 is provided. On the other hand, in the present embodiment, the CPs provided in each local area without providing them
The U-interrupt controller 25 is characterized in that it has an access right control function.

The basic configuration of the system shown in FIG. 4 is the same as that explained in the above-mentioned conventional example, and therefore its explanation is omitted.

As shown in FIG. 12, the inter-CPU interrupt control device 25 includes an interrupt storage unit 37 and an interrupt transmission register 3
3, an interrupt reception register 35, an interrupt request unit 38, and an address decoder 39.

The interrupt storage unit 37 is constructed so as to be able to store interrupt information for each transmission CPU and for each interrupt level.

As shown in FIG. 12 and Table 4, the interrupt transmission register 33 has the same transmission CPU and has an interruption flag for each interruption level on the reception CPU side.
It has an interrupt generation information creation unit 34 that creates interrupt generation information based on the information of No. 7 and the write information. Then, the inter-CPU interrupt control device 25, as shown in Table 4, includes an interrupt transmission register for CPU-1, an interrupt transmission register for CPU-2, ..., An interrupt transmission register for CPU-M. A transmission register group, that is, an interrupt transmission register group provided corresponding to each transmission CPU is provided.

As shown in FIG. 12 and Table 4, the interrupt receiving register 35 has the same interrupt level of the receiving CPU and the interrupt flag of each transmitting CPU, and the interrupt storing unit 3
It has an interrupt initialization information creation unit 36 that initializes the interrupt based on the information of 7 and the write information. And C
As shown in Table 4, the inter-PU interrupt control device 25 includes an interrupt receiving register including an interrupt receiving register for interrupt level 1, an interrupt receiving register for interrupt level 2, ..., An interrupt receiving register for interrupt level N. A group, that is, an interrupt reception register group provided so as to correspond to each interrupt level.

[0041]

[Table 4]

The interrupt request unit 38 is the interrupt storage unit 3
It has a function of requesting an interrupt request to the CPU 21 for each level based on the information of 7.

The address decoder 39 has a function of selecting one of the plurality of interrupt transmission registers 33 and the plurality of interrupt reception registers 35 to make it accessible.

The CPU 21 on the transmitting side accesses the interrupt transmission register 33, and the interrupt reception register 35
Are distinguished so that the CPU 21 on the receiving side accesses them, and the respective registers 33 and 35 perform processing on the interrupt storage section 37 which they have in common.

As described above, the interrupt transmission register 33 accessed by the transmission CPU 21 is divided for each CPU, and each register is configured with an interrupt flag for each interrupt level. Therefore, the transmission CPU 21 is assigned to itself. Interrupt transmission register 33 (for example, the transmission CPU is C
If it is PU-1, the CPU-1 interrupt transmission register for CPU-1 (see Table 4) is accessed, and the flag for the corresponding interrupt level (for example, if the interrupt level is 1, C
The interrupt level can be managed by setting the interrupt level 1 flag of the PU-1 interrupt transmission register (see Table 4) to "1". Each interrupt transmission register 33 has an interrupt generation information creation unit 34, and the information stored in the interrupt storage unit 37 is modified by the interrupt generation information creation unit 34 as shown in the state transition table of Table 5. In other words, writing "0" to the interrupt flag does not change the internal information,
To write "1", the internal information is set to "1". When "1" is written, "0" is written only to the flag of the level that generates an interrupt, and "0" that does not change the internal information is written to the flags of other interrupt levels. Is "0", "1" when it is "1"
Therefore, the retention of internal information is guaranteed. As described above, since the interrupt generation information creation unit 34 does not have a function of initializing an interrupt, there is no risk of accidentally initializing flags of other interrupt levels.

[0046]

[Table 5]

As described above, the interrupt receiving register 35 accessed by the receiving CPU 21 is divided according to the interrupt level, and each register is configured with an interrupt flag for each transmitting CPU, so that the receiving CPU 21 is interrupted. Access the interrupt receiving register 35 (for example, if the interrupt level is 1), the interrupt receiving register for interrupt level 1 (see Table 4) is accessed, and the corresponding transmitting CPU
Flag (for example, if the transmitting CPU is CPU-1, CPU-1 of the interrupt receiving register for interrupt level 1)
Interrupt flag-see Table 4-) or "0"
The transmission CPU can be managed by initializing as. Each interrupt reception register 35 has an interrupt initialization information creation unit 36, and the information stored in the interrupt storage unit 37 is
The interrupt initialization information creation unit 36 corrects the state transition table shown in Table 6. That is, the internal information is not changed when writing "0" to the interrupt flag, and the internal information is set to "0" when writing "1". Then, "1" is written only to the flag for the transmitting CPU that initializes the interrupt, and "0" that does not change the internal information is written to the flags for the other transmitting CPUs. When it is "0", it is "0", and when it is "1", it is "1", and retention of internal information is guaranteed. As described above, the interrupt initialization information creating unit 36 does not have a function of generating an interrupt, and therefore there is no risk of accidentally setting the flag for another transmitting CPU to "1".

[0048]

[Table 6]

FIG. 13 is a flow chart for accessing the interrupt transmission register 33 from the transmission CPU 21. That is, the transmitting CPU 21 generates an interrupt by writing "1" only to the corresponding interrupt level flag of the CPU interrupt transmitting register 33.

FIG. 14 is a flow chart for accessing the interrupt reception register 35 from the reception CPU 21. That is, the receiving CPU 21 reads out the interrupt receiving register 35 for the corresponding interrupt level, recognizes what the transmitting CPU is, and then writes "1" only to the interrupt flag for the CPU recognized by the interrupt receiving register 35 to initialize it. Turn into.

FIG. 15 and FIG. 16 more specifically show the structure of this embodiment. The interrupt generation information creation unit 34 in the interrupt transmission register 33 has a data bus as an input and an output from the interrupt storage unit 37, is configured by a logical sum, and is connected to the interrupt storage unit 37. The interrupt initialization information creating unit 36 in the interrupt receiving register 35 has a data bus and an output of the interrupt storage unit 37 as inputs, and outputs a clear signal to the interrupt storage unit 37 only when “1” and “1”. It is connected to the. The interrupt storage unit 37 is connected to the data bus via a buffer via the interrupt transmission register 33 and the interrupt reception register 35, and its internal information can be read. Interrupt request unit 38
In the configuration shown in FIG. 15, the output of the interrupt storage unit 37 is logically ORed for each interrupt level, and an interrupt request is issued to the CPU 21 for each interrupt level.

Next, referring to FIG. 17, CPU-i to CPU
The interrupt operation of -j to the interrupt level k will be described.

First, the CPU-i is the receiving CPU CP.
The bus exclusive right of the U-j local bus is given to the bus control unit 18
(Via Figure 4). Then CPU-i is CPU
CPU of inter-CPU interrupt controller 25 attached to -j
Write only the interrupt level k flag of the i-interrupt transmission register 33 to "1". Interrupt generation information creation unit 3
4 sets only the interrupt level k flag to “1” and latches “1” at the end of the write operation to interrupt the storage unit 3
It is stored in the interrupt flag for the CPU-i of 7 and the interrupt level k (step # 31).

The interrupt storage unit 37 transmits the interrupt information to the interrupt request unit 38, and the interrupt request unit 38 sends the CPU-j.
Request interrupt processing of interrupt level k (step #
32).

The CPU-j recognizes the interrupt request of the interrupt level k (step # 33) and interrupts the current process (step # 34).

Next, the CPU-j reads the interrupt receiving register 35 for the interrupt level k (step # 35),
Recognizing that the interrupt flag for CPU-i is "1", it is recognized as an interrupt from CPU-i (step # 3).
6).

Then, the CPU-j writes only the CPU-i flag of the interrupt receiving register 35 for the interrupt level k to "1" (step # 37). The interrupt initialization information creation unit 36 inverts only the CPU-i flag to "0" and initializes the interrupt flags for the CPU-i and the interrupt level k in the interrupt storage unit 37 (step # 3).
8).

After that, the CPU-j executes the interrupt processing of the interrupt level k from the CPU-i, and then the return processing from the interrupt processing (steps # 39, # 4).
0).

Inter-CPU interrupt control device 2 described above
In the case of 5, the control of the access right to the interrupt register is unnecessary, so that it is not necessary to arrange the access control storage section on the common memory as in the conventional example shown in FIG.

The basic structure and operation of the inter-CPU interrupt control device of this embodiment have been described above.
By executing the process flow indicated by I and II, it is possible to smoothly perform the process of delivering a large amount of information associated with the interrupt. That is, an information storage section is provided on the common memory 20 (FIG. 4) for each interrupt CPU and for each interrupt level, and information storage and information read processing can be executed using the interrupt flags in each interrupt storage section 37. it can. FIG. 17
The process flow indicated by I is a process of storing information at the time of CPU-i and level k in the interrupt control device 25 of CPU-j in the common memory 20 (steps # 41, # 4).
2) and the process flow indicated by II in FIG. 17 is a process of reading the information written in the process indicated by I from the common memory 20 (step # 51). The access right to the storage unit is guaranteed by the interrupt flag in the interrupt storage unit 37. In this way, the inter-CPU interrupt control device uses the interrupted C
It is highly expandable in passing information between PUs.

[0061]

According to the present invention, the access control storage unit on the common memory and the access right control flow using this access control storage unit, which were required in the conventional example, are not required, so that an interrupt between CPUs is not required. The processing time can be shortened.

Further, according to the present invention, an interrupt between CPUs which enables interrupts at a plurality of levels among a plurality of CPUs although interrupt processing and management can be easily performed without controlling access rights. A control device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first conventional example.

FIG. 2 is a configuration diagram showing a first conventional CPU interrupt control device.

FIG. 3 is an explanatory diagram showing a problem of the first conventional example.

FIG. 4 is a configuration diagram showing a system used in the present invention and a second conventional example.

FIG. 5 is a configuration diagram showing an inter-CPU interrupt control device and an access control storage unit in a second conventional example.

FIG. 6 is a circuit configuration diagram showing an interrupt register and an interrupt request unit in a second conventional example.

FIG. 7 is a flowchart showing an operation of access right control in the second conventional example.

FIG. 8 is a flowchart showing the operation of the inter-CPU interrupt control device in the second conventional example.

FIG. 9 is an explanatory diagram showing flag transitions in the interrupt storage unit in the interrupt register in the second conventional example.

FIG. 10 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 11 is an explanatory diagram showing a problem that occurs when there is no access right control flow in the second conventional example.

FIG. 12 is an internal configuration diagram of an inter-CPU interrupt control device according to an embodiment of the present invention.

FIG. 13 is a flowchart illustrating an operation when accessing the interrupt transmission register from the transmission CPU according to the embodiment of the present invention.

FIG. 14 is a flowchart illustrating an operation when accessing the interrupt reception register from the reception CPU according to the embodiment of the present invention.

FIG. 15 is a configuration diagram showing an inter-CPU interrupt control device in an embodiment of the present invention.

FIG. 16 is a circuit configuration diagram showing an interrupt transmission register and an interrupt reception register in the embodiment of the present invention.

FIG. 17 is a flowchart illustrating the operation of the inter-CPU interrupt control device according to the embodiment of the present invention.

[Explanation of symbols]

 21 CPU 33 Interrupt transmission register 34 Interrupt generation information creation unit 35 Interrupt reception register 36 Interrupt initialization information creation unit 37 Interrupt storage unit 38 Interrupt request unit 39 Address decoder

Claims (1)

[Claims] 1. An inter-CPU interrupt control attached to each CPU in a system having a plurality of CPUs in a device, and a CPU issuing an interrupt acquires a bus exclusive right of a local bus of the CPU receiving the interrupt and executes an interrupt. The device is provided with an interrupt storage unit for storing interrupt information for each CPU that issues an interrupt and for each interrupt level, and the interrupting CPU has the same interrupt flag for each interrupt level on the CPU side that receives the interrupt. Based on the information in the interrupt storage section and the write information, the interrupt transmission register that has the interrupt generation information creation section that creates the interrupt generation information is provided by the corresponding number so as to correspond to each CPU that issues an interrupt. The interrupt level of the receiving CPU is the same and has an interrupt flag from the CPU that issues each interrupt. An interrupt reception register having an interrupt initialization information creation unit that initializes an interrupt based on information and write information is provided by the corresponding number so as to correspond to each interrupt level, and the information in the interrupt storage unit is also included. And an address requesting unit for requesting an interrupt request to the CPU for each level, and selecting one from the plurality of interrupt transmission registers and the plurality of interrupt reception registers to make it accessible. And an inter-CPU interrupt control device, characterized in that the interrupt transmission side and the interrupt reception side can separately access the same interrupt storage unit.