JPS6124742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for coupling two common busbars.

In recent years, so-called multiprocessor systems, in which multiple processors are combined and work cooperatively, have been attracting attention. One method that has become popular in multiprocessor systems is to directly connect the respective busbars so that multiple processors can freely access each other's memory 1/0 devices. Difficult problems arise when combining multiple busbars. That is, since each processor is operating independently, if one processor uses the bus of the other processor, a conflict in the use of the bus will occur. In such cases, the common method is to receive an access request from one bus, send a usage request to the processor connected to the other bus, receive approval, and then access the bus. It is taken. but,
If the processors on the opposite side also request access to the other bus at the same time, a so-called "dead log" may occur in which both processors are stuck without being authorized to use the other bus. One method for preventing this is to perform each access as an independent cycle for each bus. According to this, when writing data to another memory, for example, a write cycle is first completed on one bus line, and then a write cycle is similarly completed on the other bus line, thereby completing the write cycle. When reading, the read cycle is completed on one bus line, then the read cycle is completed on the other bus line, and then the read data transfer is completed in the reverse order. At first glance, this method seems to work correctly without any contradictions, but if we consider the case where access is performed via three buses and an unauthorized access occurs on the third bus, it becomes impossible to Since the first access is normal, that access is processed as normal, and the third access becomes abnormal, resulting in data loss or the coupling device becoming unable to operate.

The purpose of the present invention is to combine two buses managed by two independently operating processors, receive an access request from one bus, complete the access, and issue an access request to the other bus. , makes a usage request to the other processor, receives an access response from the other bus whose usage request has been approved, maintains the response state, and when access corresponding to the accepted access request is made to one bus. An object of the present invention is to provide a coupling device having a function of returning an access response to one bus.

According to the coupling device of the present invention, even if unauthorized access occurs for some reason during the access, a response is always returned, and by returning this to the requesting side, data is not lost or "dead log" occurs. Since there is no risk, it is possible to easily realize a multiprocessor system.

The present invention will be explained in detail below using examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which 10 and 20 are bus bars, 1 is an access request reception circuit, 2 is an access request circuit,
P1 and P2 are processors, 3 is an access response reception circuit, and 4 is an access response circuit.

The access request reception circuit 1 detects that a specific address range has been accessed on the bus 10, accepts the access request, once ends the access to the bus 10, and issues a start command 101 to the access request circuit 2.

The access request circuit 2 sends a start command 101 and a use request 104 to the receiving processor P2, and issues a use approval 1.
05, it issues an access request to the bus 20.
The access response reception circuit 3 issues a response state 102 when it receives an access response from the bus 20 or when it receives a signal that the access request is not accepted when issued. The access response circuit 4 receives the response state 102, issues an access response to the bus to which the access corresponding to the access request received from the bus 10 is performed, issues a release signal 103, and releases the access request reception circuit 1 from the busy state.

FIG. 2 is a block diagram showing an example of the configuration of the access request reception circuit 1 of the present invention. 21 is a control circuit, 22 is an address detection circuit, and 23 is a bus transceiver. The address circuit 22 detects that the address line 210 on the bus 10 accesses a specific address area and outputs a detection output 205. When the control circuit 21 receives the access request 201 and receives the detection output 205, the control circuit 21 sends the bus 1 to the bus transceiver 23.
A command 206 to set information of 0 is issued. 202,2
03, 204 are approval, disapproval, and standby signals, respectively, and the control circuit 21 receives the access request 201.
If the access request circuit 2 successfully receives the request, it returns an approval signal 202 and transmits a start signal 207 to the access request circuit 2. If it is already being processed and is in a busy state, wait signal 2
Roll out 04. Further, in the case of some kind of unauthorized access request, a disapproval signal 203 is issued.

Bus transceiver 23 transmits information on bus 10 to address request circuit 2 through signal line 208.
FIG. 3 is a block diagram showing an example of the configuration of the address request circuit 2, in which 31 is a control circuit and 32 is a bus drive circuit.

When the control circuit 31 receives a start signal 207, it issues a use request 104 to the processor 2, and when a use approval 105 is input from the processor P2, it issues an access request 301 to the bus 20, and the bus drive circuit 3
An output command is issued to the information line 305 of the bus 20 of the information 208 to 2.

302, 303, and 304 are approval, disapproval, and standby signals on the bus 20, respectively, and the control circuit 31
When receiving the approval signal 302 or disapproval signal 303, the access request is terminated. Also standby signal 3
When receiving 04, the access request is terminated once,
The access request is made again and the process is repeated until the approval signal 302 or disapproval signal 303 is obtained.

FIG. 4 is a block diagram showing the configuration of the access response reception circuit 3. As shown in FIG. 41 is a control circuit, 42
is a transceiver, and 43 is a state holding circuit. When the access response 306 for the bus 20 is issued, the control circuit 41 outputs an approval signal 302 to access the bus 20 at that time.
A command 410 to set the above information is issued.

The control circuit 41 also issues a set command 410 when an access request 301 is issued and a disapproval signal 303 is issued, and prepares to return an access response even in the event of an unauthorized access request. The state holding circuit 43 holds information on the approval signal 302 and non-approval signal 303 when the set command 410 is issued, and maintains the approval state 402,
A non-approval status 403 is output. Transceiver 42
transmits information about the bus 20 to the access response circuit 4 in accordance with the set command 410.

FIG. 5 is a block diagram showing an example of the structure of the access response circuit 4. As shown in FIG. 51 is a control circuit, and 52 is a bus drive circuit. The control circuit 51 is connected to the bus 1
When an access 502 is performed in response to an access request accepted from 0, when an approval state 402 or a non-approval state 403 is received from the access response reception circuit 3, an access response 207 is issued and an output command 501 is issued to the bus drive circuit 52. Approval signal 202
When obtained, a release signal 103 is sent to the access request receiving circuit 1 to release the busy state and terminate the access response.

The bus drive circuit 52 receives the output command 501 and outputs the information 405 from the access response reception circuit 3 to the bus 10.

As described above in detail below, the present invention is applicable to a system in which a plurality of processors perform processing by combining subsequent bus lines, and when one processor accesses the bus line of another processor, the access request is Once received, the access is terminated and an access request is made to the other bus, and when an access response is issued, it is accepted.Even if the acceptance is not approved at the time of the access request, an access response from one bus is returned and the busy state of the access reception is confirmed. A coupling device is provided which is composed of a circuit having a release function and can respond to failures even if unauthorized access occurs during mutual access between processors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing one example of the configuration of an access request receiving circuit used in the present invention, and FIG. 3 is a block diagram showing one example of the configuration of the access request circuit used in the present invention. FIG. 4 is a block diagram showing one example of the configuration of the access response reception circuit used in the present invention, and FIG. 5 is a block diagram showing one example of the configuration of the access response circuit used in the invention. . In the figure, 10, 20...Bus line, P1, P2...Processor, 1...Access request receiving circuit, 2...
Access request circuit, 3...Access response reception circuit, 4...Access response circuit, 21, 31, 4
1, 51... Control circuit, 22... Address detection circuit, 23, 42... Bus transceiver, 32,
52 shows a bus drive circuit, and 43 shows a state holding circuit.

Claims (1)

[Claims] 1 A device that connects two bus lines in which two processors manage each bus line, detects that a specific address range has been accessed to one of the bus lines, and once the access is accepted, the an access request circuit which becomes busy and does not accept any further access, and requests the other processor activated by the access request circuit and managing the other bus to use the other bus; an access request circuit that requests access to the other bus when the request is approved; an access response reception circuit that accepts an access response to the access request from the other bus and maintains a state of the response; and the access response circuit. When an access corresponding to the accepted access request is made to the one bus bar, an access response is made in response to the state of the response held, and the busy state of the access request receiving circuit is changed. and an access response circuit for releasing the coupling device.