JPH0351017B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical field to which the invention pertains] A computer is provided in a computer connected to a system bus including a plurality of computers, and is accessed from the computer via the internal bus as well as from other computers. The present invention relates to a method for controlling access to data shared within a system stored in a common memory configured as a dual port memory so as to be accessible via the system bus.

[Prior art and its problems]

FIG. 1 shows a conventional configuration of an information processing system having a shared memory consisting of this type of dual port memory. In Figure 1, 1 and 17 are central processing units (CPU), 2 and 3 are internal buses, 4 is an internal bus memory access signal, 5 is a common memory consisting of dual port memory, 6 is a memory access signal, and 7 is a common A memory access circuit, 8 a memory drive signal, 9 a system bus, 11 and 12 registers, 16 a normal memory, and 18 and 19 input/output circuits. Master devices (computers) used in such information processing systems include those using a common memory 5 as shown at 10, and those using a common memory 16 as shown at 20.
There are devices using the master device 30,
40 is also configured like the master devices 10 and 20.

In such an information processing system, since the shared memory 5 in the master device 10 may be competitively accessed by the internal bus 3 and the system bus 9, a prior access priority method is adopted. That is, as shown in the time chart of FIG. 2A, during a period _T1 when the common memory 5 is accessed by the internal bus memory access signal 4 and the memory access signal 6 is output, for example, the input/output circuit is activated by the master device 20. Even if the memory drive signal 8 is issued from the system bus 9 side via 18 and 19 and an attempt is made to access the common memory 5, there is a period T ₂ until the access from the internal bus 3 is completed.
Access from the system bus 9 is made to wait.
Conversely, if the common memory 5 is accessed by the memory drive signal 8 from the system bus 9 and an attempt is made to access it by the access signal 4 from the internal bus 9 during the period _T3 when the memory access signal 6 is output, the system bus During the period _T3 until the access from the internal bus 9 is completed, the access from the internal bus 3 is made to wait.

In this type of advance access priority method, when access from one of the internal bus 3 and system bus 9 is completed, access from the other bus becomes possible. Periods A and C in which the common memory 5 is accessed by the memory drive signal 8 from the bus 9 cannot be accessed by the internal bus memory access signal 4 from the internal bus 3; It can be accessed by bus memory access signal 4.

By the way, if there is data that is shared within the system in the common memory 5, and there is some data (hereinafter referred to as resources) that has a correlation with each other, priority is given to early access as described above. If it is just a method, if one of the data is read and processed by some master device in period 4 and comes back again in period C, that data is being processed externally. If the central processing unit 1 reads and processes related data other than the relevant data during the period B, the correlation may become incorrect.

Conventionally, in order to manage resources by accessing data with this type of correlation from many master devices, ordinary memory was directly connected to the system bus 9,
Usually, the master device accesses the memory as needed. In this case, one master device sends a bus busy signal on the system bus to inform the other master devices that the system bus is being used, thereby prohibiting the use of the memory by other master devices. There is no problem since it is accessed only by the master device.

However, if the configuration is such as the common memory 5 in FIG. 1 that can be accessed from both the internal bus 3 and the system bus 9, one master device may be using the system bus 9 and outputting a bus busy signal. Even if access is possible from the internal bus 3, a situation may arise where correlated data is used multiple times and the correlation becomes out of order as described above.

In order to solve such a problem, the conventional technology uses registers that can only be written by the central processing unit 1 and read only by the other master devices 20, 30, and 40, as shown in 11 and 12 in FIG. 12 and the opposite relationship are prepared, and before the central processing unit 1 uses the resource, it reads the register 11 and determines whether the resource can be used.If the resource can be used, it sets the register 12 and transfers it to the master device 20. Prohibits the use of resources. In the opposite case, the master device 20 first reads the register 12, makes a determination, and then sets the register 11.

However, in this method, it is necessary to read or write to register 11 or 12 every time a resource is used, which increases the burden on the software. Furthermore, it is necessary to control so that the master device 20 does not read the register 12 while the central processing unit 1 is setting the register 12, and to prevent the central processing unit 1 from reading the register 11 while the master device 20 is setting the register 11. The disadvantage is that it requires additional hardware that slightly slows down the timing.

[Purpose of the invention]

In view of the above-mentioned circumstances, the present invention aims to minimize the number of accesses and reduce the burden on software in an information processing system having a common memory, and at the same time allows one master device to access data in the common memory that has a mutual relationship. , etc., the RAM is locked even if related data is retrieved via the internal bus to prevent data correlation from being disrupted.
The present invention aims to provide an access method that eliminates the drawbacks of the common memory access method and enables resource management by software with a simple hardware configuration.

[Key points of the invention]

The present invention is provided in a computer connected to a system bus including a plurality of computers, and is accessed by the computer via the internal bus, and is also accessible from other computers via the system bus. In a method for controlling access to data shared within a system stored in a common memory configured as a dual port memory, the computer accesses the system bus after reading the common data in the common memory from the other computer. The present invention is characterized in that access to the common memory from the internal bus side is prohibited during a period in which a busy signal is output. In other words, in the present invention, even when this common memory is not being accessed from the system bus side, the bus in the device is disabled while the bus busy signal is continuously output after the memory drive signal is output from the system bus side. At the same time, this was achieved by using existing signals on the system bus and simple hardware additions, without preparing any special signals for this purpose.

[Embodiments of the invention]

FIG. 3 shows a block diagram constructed using the present invention. In FIG. 3, the same components as in FIG. 1 are indicated by the same reference numerals. To explain this in comparison with the configuration diagram according to the prior art shown in FIG. 1, according to the present invention, a new lock signal generation circuit 14 is added to the master device 10, thereby making the registers 11 and 12 in FIG. 1 unnecessary. Become. According to the present invention, the memory drive signal 8 is configured to enter the lock signal generation circuit 14 without directly entering the common memory access control circuit 7, and the bus busy signal 13 is also input to the lock signal generation circuit 14. ing. Lock signal generation circuit 1
An example of circuit No. 4 is shown in FIG. When the memory drive signal 8 is output from the system bus 9, the S-R flip-flop 22 is set and the memory lock signal 15 is output. In other words, when the memory drive signal 8 becomes "0", its output becomes "1" through the NOT circuit 21.
become. Therefore, the input to the S terminal of flip-flop 22 changes from "0" to "1". On the other hand, at this time, the R terminal changes from "1" to "0" because the bus busy signal 13 is input. As a result, the output of the flip-flop 22 changes from "1" to "0" and the lock signal 15 is applied to the memory access control circuit 7 in the form of "0". After that, the memory drive signal 8 becomes "1",
Even if the output of the NOT circuit 21 becomes "0" and the input of the S terminal changes to "0", the bus busy signal 13
As long as is "0", the output Q of flip-flop 22 remains "0" and does not change. In this way, when the bus busy signal 13 becomes "1", the input to the S terminal is switched to "0" and the input to the R terminal is switched to "1", so the output of the flip-flop 22 changes to "1", and the lock signal 15 disappears and returns to its original state. Return to state.

In such a configuration, assuming that the common memory 5 is accessed from the external master device 20 and the master device 20 processes data, the master device 20 first issues the bus busy signal 13 to monopolize the system bus 9, and then Necessary data is taken from the common memory 5 by issuing a memory drive signal 8 and an address signal. The lock signal generation circuit 14 outputs a memory lock signal 15 to prevent the central processing unit 1 from accessing the common memory 5 via the internal bus 3 on the condition that the bus busy signal 13 and the memory drive signal 8 are output. Access from other than the access control circuit 7 is locked. At the same time, the common memory access control circuit 7 outputs the common memory access signal 6. When the common memory access signal 6 is output and access is performed, the memory drive signal 8 disappears and the master device 20 receives the data. While the data is being processed in the master device 20, the bus busy signal 13 is continuously output. As a result, the lock signal 15 becomes the same as the bus busy signal 13.
is output while . Therefore, the central processing unit 1
Access to the common memory 5 from other master devices 30, 40 is locked, and access to the common memory 5 from other master devices 30, 40 is prohibited via the system bus 9.
is not performed because it is exclusively used by the master device 20. The processed data is again written to the common memory 5 by the memory drive signal 8 and address signal. When writing is completed, the memory drive signal 8 for writing and the bus busy signal 13 disappear, so the lock signal 15 also disappears. This will return you to the initial state. When the central processing unit 1 accesses the common memory 5, it issues an internal bus memory access signal 4, and the common memory access circuit 7 issues a memory access signal 6 to retrieve data. During this time, the common memory access control circuit 7 cannot be used by others, so the others are locked.

FIG. 5 is a time chart of the embodiment of the present invention shown in FIG. As long as the signal 13 remains, the memory lock signal 15 is output, indicating a situation in which other central processing units 1 cannot access the common memory 5 until the processing on the master device 20 side is completed. That is,
The memory drive signal 8 is sent from the master device 20.
Following the MD period, the common memory access signal 6 is output for a period of 20R, and the data is read by the master device 20. During this process, even if the memory access signal 4 from the central processing unit 1 is in the MA period, the lock signal 15 is output during the BBSY period when the bus busy signal 13 is output from the master device 20, so as long as this does not disappear, memory access will not be possible. signal 4
is not valid, and data enters the central processing unit 1 starting from the period 10R of the common memory access signal 6 after the period BBSY ends.

〔Effect of the invention〕

According to this invention, since the memory lock signal is created by combining the bus in use signal and the memory drive signal, access to the common memory from the internal bus side is prohibited even if the memory drive signal drops, and the system is controlled by software. Resource management can be performed correctly. Furthermore, the system bus itself does not require any special signals for locking the memory; the system bus itself can be used as is, and only a small amount of new hardware is required. Therefore, a new type of information processing system has been realized by establishing a simple and reliable control method for a dual-port type common memory with a light burden on software.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional system, Figure 2 is a time chart of the system shown in Figure 1,
FIG. 3 is a block diagram of a system as an embodiment of the present invention, FIG. 4 is a circuit diagram of a memory lock signal generating circuit according to the present invention, and FIG. 5 is a time chart of the system shown in FIG. 3. 10, 20, 30, 40... Computer (master device) 1, 17... Central processing unit, 5... Common memory (dual port type), 9... System bus, 3... Internal bus, 13... Bus busy signal,
14...Lock signal generation circuit, 7...Common memory access control circuit, 8...Memory drive signal.

Claims (1)

[Claims] 1. Connected between an internal bus of a first computer and a system bus to which a plurality of second computers are connected,
In the control method for controlling access to a common memory composed of dual port memory accessible from both the internal bus and the system bus, the memory lock signal is set by a memory access signal from the system bus and outputs a memory lock signal. , a lock signal generation circuit that is reset when the bus busy signal of the system bus disappears; and the memory lock signal and the memory access signal from the internal bus are input, and during the period when the memory lock signal is input, , a common memory access control circuit that disables a memory access signal from the internal bus, and during a period when the second computer is outputting a bus busy signal to the system bus, a first control circuit for the common memory is provided. A common memory control method for multiple computer systems that disables access by computers from the internal bus.