JPS6341973A - Multi-processor system - Google Patents

Abstract

PURPOSE:To attain the data transmission at a high speed and a good efficiency by executing the data transmission to other micro-processor system when the data read from a memory circuit are temporarily held at a control part. CONSTITUTION:During the data transferring of a master micro-processor system 40, namely, at the time of the output of a reading control signal through a control signal bus, the data transmission of other master micro-processor systems 50 and 60 is executed. Thus, the data for transferring the data are temporarily held at a DMA controller (control part), when the data are held, the data transmission is executed to other master micro-processor systems 50 and 60, and at the time of transferring the data of the master micro-processor system 40, the data held at the DMA controller are sent. Thus, even when the overlapping using request of a system bus occurs, the system bus in not monopolized to the special data transferring and the data transferring at a high speed and a good efficiency can be executed.

Description

Detailed Description of the Invention Technical Field The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system that is composed of a plurality of microprocessor systems and a system bus to which these microprocessor systems are commonly connected, and that provides communication between these microprocessor systems. This paper relates to a multiprocessor system that transfers data using direct memory access.

BACKGROUND ART Conventionally, data transfer between a plurality of microprocessor systems is generally performed via a system bus that can be commonly used by the respective microprocessor systems.

This type of system bus includes IEEE-796 (The
In5titude of Electrical a
nd Electronics Engineer −
796> multipath and IEEE-P4O10 VME
Buses are used.

As shown in FIG. 5, the multipath system includes multiple mask microprocessor systems 4 on a multipath 101.
0.50.60 can exist, and each mask microprocessor system 40.50°60 has a multipath 101
When using the local bus 44, the bus exchange control circuits 42, 52 and 62 provided in each system are arbitrated by the bus exchange control signal via the multipath 102.
．． 56.67 and buffer circuits 43, 53, and 63, address signals, data signals, and control signals are output onto the multipath 101.

The architecture of the multipath 101 is as shown in FIG. It is output from the central processing unit 41.51.61 and performs data transfer with other mask microprocessor systems 40.50.60 and the slave system 70.

In FIG. 5, the master microprocessor system 5
0 has an input/output device (l10) 54 and a memory circuit 55.
The mask microprocessor system 60 is provided with an input/output device 64, a memory circuit 65, and a bidirectional control circuit 66, and the slave system 70 is provided with a memory circuit 71 and a buffer circuit 72, respectively.

In such a conventional multiprocessor system, the speed of data transfer between microprocessor systems depends on the clock signal frequency of CPtJ41.51.61, the execution speed of data transfer instructions, and the speed of 8-bit CPU or 16-bit CPU. Data transfer can be performed at high speed using direct memory access (hereinafter referred to as DMA) technology, which allows large amounts of data to be transferred at high speed without CPU intervention, although this greatly depends on the type of CPU.

However, in a multiprocessor system, the microprocessor systems 40, 50, and 60 are
01, 102 to another microprocessor system 40, 50, 60, once the DMA is started, the multipath 101
, 102 while data transfer by DMA is being performed,
Even if there is a request to use the multipaths 101, 102 from another microprocessor system 40, 50, 60, the multipaths 101, 10 will continue until the data transfer is completed.
2 is used exclusively for data transfer. Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks of the conventional system, and is capable of high-speed and efficient data transfer without being exclusively used for a specific data transfer even if the system bus is required to be used repeatedly. The purpose of the present invention is to provide a multiprocessor system that can perform the following functions.

Configuration of the Invention A multiprocessor system according to the present invention includes a plurality of microprocessor systems and a system bus to which the microprocessor systems are commonly connected, and data is transferred between the microprocessor systems by direct memory access. The multiprocessor system is provided with a control unit for storing data for the data transfer and controlling the data transfer for each of the microprocessor systems, and the control unit for storing the data for the data transfer is stored in the control unit of the microprocessor system that performs the data transfer. The data transfer is performed by direct memory access using the data transferred, and when the data is stored in the control unit of the microprocessor system that performs the data transfer, one of the other microprocessor systems performs the data transfer. It is characterized by the following.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one microprocessor system constituting the multiprocessor system includes a CPU 1, a control signal generation circuit 2, and a DMA controller that controls data transfer using DMA.
fvl A controller 3, an address latch circuit 4 that separates addresses and data that are multiplexed and output on the address/data signal bus 13, data transceiver circuits 5 and 11, and a memory circuit 7 that decodes addresses.
an address decoder circuit 6, a memory circuit 7,
A control signal logic circuit 8 that generates signals to control each circuit, a control signal buffer circuit 9 that interfaces the control signal bus 14 and the multipath 101, and an address signal buffer that interfaces the address signal bus 15 and the multipath 101. It consists of a circuit 10 and a bus exchange control circuit 12 that arbitrates the right to use the multipath 101.

Here, the data transceiver circuit 11 inkfaces the address/data signal 13 and the multipath 101. Further, the address/data signal bus 13, the control signal bus 14, and the address signal bus 15 are local buses of this microprocessor system.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention, and FIG. 3 is a configuration diagram of a frequency dividing circuit of the control signal logic circuit 8 of FIG. 1. The operation of an embodiment of the present invention will be explained using these figures and FIG. 1. In one embodiment of the present invention, a multiprocessor system is constructed by adding the same content as the microprocessor system in FIG. 1 to the configuration of each master microprocessor system 40, 50, and 60 in FIG. do.

When CPU1 issues a data transfer request to another master microprocessor system or slave system,
A DMA start command is sent to the DMA controller 3. D
The MA controller 3 has local buses (address/data signal bus 13, control signal bus 14, and address signal bus 1).
5), the bus hold request signal 18 indicating the use request is sent to cp.
Output to ui. When CPU i accepts this request to use the local bus, it outputs a bus hold permission signal 19 to the DMA controller 3 and the control signal logic circuit 8. After this handshake sequence, the right to use the local bus is transferred to the DMA controller 3.

DMA controller 3 receives address strobe signal 2
1 is output to the control signal logic circuit 8, and this address strobe signal 21 is input to the frequency divider circuit 30 (see FIG. 3) of the control signal logic circuit 8. The frequency dividing circuit 30 inputs the address initial setting signal 27° 28, divides the frequency of the address strobe signal 21 by 1/2, and outputs it to the bus exchange control circuit 12 as a bus use request signal 25 requesting the use of the multipath 101. The control signal buffer circuit and the address signal buffer circuit 10 are also logically ANDed with the bus use permission signal 26 from the bus exchange control circuit 12 that permits the use of the multipath 101, and the buffer permission signal 24 is generated.
and is output to the data transceiver circuit 11. The control signal buff circuit 9, the address signal buffer 7 circuit 10, and the data transceiver circuit 11 use this buffer enable signal 2.
Controlled by 4.

After the DMA controller 3 obtains the right to use the local bus, when the pulse of the first address strobe signal 21 is input to the control signal logic circuit 8, the control signal logic circuit 8 converts the bus permission/prohibition signal 22 into a control signal. Generation circuit 2, address latch circuit 4, and data transceiver circuit 5
The address latch circuit 4 latches the address from the address/data signal bus 13. That is,
Address strobe signal 2 from DMA controller 3
The first pulse of 1 is output as a timing pulse for latching the address to the memory circuit 7.

The control signal generation circuit 2 outputs a read control signal to the memory circuit 7 via the control signal bus 14, and data is read from the memory circuit 7 and sent to the DMA controller 3 via the data transceiver circuit 5 via the data signal bus 16. sent out,
It is temporarily held in the DMA controller 3.

The second pulse of the address strobe signal 21 is frequency-divided by 1/2 by the frequency dividing circuit 30 and outputted to the bus exchange control circuit 12 as a bus use request signal 25. Also, this second
The second pulse serves as a timing pulse for ratting the addresses of the memory circuits of other master microprocessor systems and slave systems.

The control signal generation circuit 2 receives the bus permission/prohibition signal 22 from the control signal logic circuit 8 by this second pulse.
outputs a write control 111 signal via the control signal bus 14, and this write control signal is sent to the control signal buffer circuit 9.
The data held in the DMA controller 3 is written to the memory circuit of another mask microprocessor system or slave system targeted for DMA. This write operation continues until a response signal is sent back via multipath 101.

The third pulse of the address strobe signal 21 is the first pulse.
The same operation as in the case of the second pulse is performed, but since this multipath 101 is not used by this microprocessor system, it will be used by another mask microprocessor system. When the fourth pulse of address strobe signal 21 is output, this microprocessor system uses multipath 101 again to transfer data.

The bus usage state in FIG. 2 is the multipath 1 when one embodiment of the present invention is applied to the multiprocessor system in FIG. 5.
01 during data transfer of the master microprocessor system 40, i.e. the control signal bus 1
Data transfer to other master microprocessor systems 50, 60 will take place when the read control signal is output via the microprocessor 4.

In this way, the DMA controller 3 (control unit) temporarily holds the data for data transfer, and when holding this data, causes the other mask microprocessor systems 50 and 60 to transfer the data, and this master microprocessor system 40 When transferring data, by having the DMA controller 3 send out the data held, the system bus is not exclusively used for a specific data transfer even if there is a request to use the system bus repeatedly, resulting in a high-speed and efficient system. Data transfer can be performed.

As explained above, according to the present invention, data read out from the storage circuit is temporarily held in the lltllll section, and the temporarily held data is sent to the control section during data transfer, and the data read out from the storage circuit is sent to the control section. When temporarily holding read data,
By having other microprocessor systems perform data transfers, even if there are duplicate requests for use of the system bus, this system bus will not be monopolized for a particular data transfer, allowing high-speed and efficient data transfers. The effect is that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of an embodiment of the present invention, and FIG. 3 is a frequency division of the t, II m signal logic circuit in FIG. FIG. 4 is a configuration diagram showing the circuit, FIG. 4 is a timing chart showing the multipath architecture, and FIG. 5 is a block diagram showing a conventional example. Explanation of symbols of main parts 3...DMA (Direct Memory Access)
Controller 8...Control signal logic circuit 12...Path exchange fII control circuit 21...
... Address strobe signal 24 ... Buffer permission signal 25 ... Bus use request signal 26 ... Bus use permission signal 30 ... Frequency division circuit 101 ...・・・Multi-path

Claims (2)

[Claims] (1) A multiprocessor system consisting of a plurality of microprocessor systems and a system bus to which the microprocessor systems are commonly connected, and which transfers data between the microprocessor systems by direct memory access, Each of the microprocessor systems is provided with a control unit that stores data for the data transfer and controls the data transfer, and direct memory access is performed using the data stored in the control unit of the microprocessor system that performs the data transfer. The data transfer is performed by one of the other microprocessor systems, and when the data is stored in the control unit of the microprocessor system that performs the data transfer, one of the other microprocessor systems performs the data transfer. multiprocessor system. (2) In the data transfer between the microprocessor system and the other microprocessor system, the microprocessor system and the system bus are connected by an output signal obtained by dividing the address strobe signal by 1/2 from the control unit. 2. The multiprocessor system according to claim 1, wherein the processing is performed intermittently.