JP3304503B2 - Dual system multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-system multiprocessor system and, more particularly, to a system which does not require special processing for information communication between a master system and a slave system, and which has improved processing efficiency.

[0002]

2. Description of the Related Art Conventionally, this type of double-system multiprocessor system has been used for a train control device, for example.
One control system is used in order to have to be controlled by the other control system when down, does not disturb the train operation as possible.

FIGS. 4 and 5 show a conventional system. Among them, the system shown in FIG. 4 has a plurality of main systems (hereinafter referred to as self-systems) connected to one system bus L. ) Processor boards (hereinafter, also referred to as boards) A to N, and slave (hereinafter, sometimes referred to as other) processor boards A ′ to corresponding to the main boards A to N, respectively. N 'are connected to each other.

Further, the conventional system shown in FIG.
The main boards A to N are respectively connected to the main system bus L, and the sub boards A 'to N' corresponding to the main boards are connected to the sub system bus L ',
Both system buses L and L 'are connected by an interface board X (which is an interface board in the figure).

[0005] Referring to FIG. 5, a conventional processing example will be described in detail. For example, when the system is started, the slave system needs to match the processing contents with the master system.
Each processor board of the main system regularly transmits the processing contents and the communication contents between the boards to the subordinate system via the interface board X.

[0006]

However, of the above-mentioned conventional systems, in the former system in which the main and sub boards are connected to one system bus, one board has acquired the bus right. When a state failure occurs, there is a disadvantage that another board cannot acquire the bus right and the whole system is down.

In the above-mentioned conventional system, since the system bus is separated between the master system and the slave system, the above-mentioned disadvantage of acquiring the bus right can be solved. Each processor board requires a process for sending data to the slave system. Furthermore, since the frequency of use of the system bus increases, the system efficiency of the entire system decreases.

That is, in a multiprocessor system, it is important to reduce the use frequency of the system bus which is a common resource. That is, when multiple boards request the system bus, only one of them is given permission and the other is waited, so reducing this wait time is important in multi-systems. Was a challenge.

Therefore, the present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a simple configuration and that each processor board of the main system performs processing without being conscious of the subordinate system. Even if this is done, it is an object of the present invention to provide an efficient dual-system multiprocessor system that can transmit processing contents and communication contents between boards to a slave system, and that requires less use of a system bus.

[0010]

According to the present invention, there is provided a dual-system multiprocessor system for achieving the above object.
A main multiprocessor with multiple processor boards connected to the main system bus, and a multiprocessor with multiple processor boards corresponding to each main processor port connected to the sub system bus. A dual system multiprocessor system comprising a multiprocessor and a mirror memory provided between both system buses, wherein the mirror memory includes a bidirectional memory for storing data, when the communication data is performed in one system, simultaneously with writing means for writing the data to the upper Symbol bidirectional memory, the other of the both systems the data written in the writing means of possess a capturing means for capturing the processor board of the system, the address of the bidirectional memory have different spatial assigned at the time of data communication with each other processor, the two-way note Writing data to is characterized to be performed when reading data within one system. Further, data written in the bidirectional memory is stored in a storage circuit for temporarily storing data.

[0011]

In the above configuration, when data communication is performed in the main system, the data is simultaneously transmitted to both of the mirror memories .
The slave boards fetch the data written in the bidirectional memory and process the data with the main system (coincidence of processing), or perform system switching. Make necessary preparations. Therefore, the slave system can continue without interrupting the system function when the system switching command is given.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a dual system multiprocessor system according to the present invention. The difference from the conventional example of FIG. 5 is that a pair of mirror memories M and M 'are provided instead of the interface board X. It is in. Therefore, the components other than the mirror memories M and M 'are the same as those in FIG. 5 described above, and the same components will be denoted by the same reference numerals, and the description of the components having the same reference numerals will be omitted. Omitted because of duplication.

The mirror memories M and M 'have the same configuration. FIG. 2 is a block diagram showing the electrical configuration of one of the mirror memories M.

The mirror memory M has two system buses L,
It has a pair of bus buffers 1a and 1b respectively connected to the data bus L1, address bus L2 and control bus L3 of L '. The bus buffer 1a on the main system side is a data buffer capable of temporarily recording data.
Via a through-latch type temporary storage circuit 2, it is connected to a bidirectional memory 3 capable of writing data from the main system and reading (taking in) the written data from the subordinate system. The slave bus buffer 1b is directly connected to the bidirectional memory 3.

The bidirectional memory 3 includes a pair of control circuits 4
a and 4b are connected, and one of the control circuits 4
a is configured to receive data from the control bus L3, the temporary storage circuit 2, and a counter circuit (CNT) described later to control the data write timing. Further, the other control circuit 4b is connected to the bus buffer 1 on the slave side.
b and a signal from the control bus L3 'to control the data read timing.

CNT5, flip-flop circuit (FF)
6, the AND circuit 7 and the three inverting circuits 8a to 8c generate the above-described data write and read timing signals, and operate by inputting a clock signal (CLK) from a clock signal generator (not shown). BUS indicating the operating state from the bidirectional memory 3
Y * (* indicates an inversion signal, and in the drawing, inversion is indicated by “−”), and a signal can be output to the temporary storage circuit 2 and one control circuit 4a.

The other mirror memory M 'is connected between the two system buses L and L' in a form inverted from the above-mentioned one mirror memory M. That is, the other mirror memory M 'is connected with the temporary storage circuit 2 on the slave side.

FIG. 3 is a time chart of the system according to the present embodiment, in which (a) shows a basic signal state for generating a data write / read timing signal, and mainly shows a state around the CNT 5. 3 shows the signal state of the signal.

FIGS. 2B and 2C are time charts for explaining the access timing states of the master system and the slave system. FIG. 2B shows the timing chart when the access does not conflict. Shows a case where an access conflict occurs.
The numbers in parentheses in FIG. 3 indicate the signal states of the numbers shown in parentheses in FIG. Here, the access conflict means that the master and the slave simultaneously select the same address on the bidirectional memory. At this time, if one of them writes and the other reads, the read data The inconvenience of changing occurs.

Next, a control operation of the system according to the present embodiment will be described with reference to a time chart of FIG.

Now, it is assumed that the main system board A is going to obtain predetermined data from the board B and perform predetermined arithmetic processing, and all the sub system boards have access to the mirror memory. It is assumed that it has not been performed ((b) of FIG. 3)
State. ).

The board A reads data d addressed to itself from the board B at a predetermined board address b of the board B (this data is referred to as "ad"), and performs predetermined arithmetic processing.

The data d read by the board A is also simultaneously received by the temporary storage circuit 2 via the bus buffer 1a, but here, it is temporarily stored at an address b 'different from the board address b of the board B ( This data is referred to as "b '
d ”. ). That is, address data different from that of the board A is added to the temporary storage circuit 2 and temporarily stored. This is because, when the slave reads this data, if it is read at the board address b, it becomes the same address as the board B 'on the slave system, thereby preventing data confusion.

Since none of the slave boards is accessing the mirror memory, the temporarily stored data can be immediately written to the bidirectional memory. At this time, since reading is being performed on the system bus, the control circuit (4a) converts the read signal into a write signal.

Since the data through latch type is used for the temporary storage circuit 2, the latch signal LCP * becomes "H".
In the case of, the input data passes through to the output side
Input data is latched at the fall of CP * (↓),
LCP * is “L”, and the latched data is held.
If there is no conflict, LCP * becomes "H", and the address data and control signal on the system bus are directly input to the bidirectional memory 3 and the control circuit 4a.
Then, writing to the bidirectional memory is executed as it is.

Next, the operation at the time of access contention will be described. The priority in the event of an access conflict is given to the first accessor using the first-come-first-served method. Also, in the case of exactly the same time, priority is given to either one. The result of the determination is output by the BUSY * signal (FIG. 3
(C), (1), (2), (3), (7), (8) and (a)).

When an access conflict occurs and the priority is given to the slave, "L" of BUSY * is output, and writing of the data a'd to the bidirectional memory 3 is prohibited (FIG. 3).
(C) (b)). This write prohibition is continued until the access on the slave side ends and the contention is released. But,
Since the board A reads the data d from the board B, the access may be terminated before the access conflict in the bidirectional memory is released. Therefore, a temporary storage circuit 2 is provided to temporarily store address data and control signals, and furthermore, a circuit such as CNT5 is provided to reliably write the temporarily stored data to the bidirectional memory.

When the slave access is completed, BUSY *
Becomes “H”, and the CNT 5 starts counting. CN
CNT2 and CNT4, which are output signals of T5, are a signal that defines a retention time of temporarily stored data and the like,
It is used to create an ITE * signal, and data a'd is written to the bidirectional memory 3 by a WRITE * signal.
Therefore, the slave board can fetch correct data a'd from the bidirectional memory 3 even when an access conflict occurs.

As described above, in the system according to the present embodiment, the main system does not require processing for data transmission to the subordinate system, and the frequency of use of the system bus can be reduced. An efficient dual-system multiprocessor system can be provided.

Although the above description of the operation has been given of an example in which the main board A reads data from the board B, the operation is similarly performed for other boards. When the main board takes in data from the subordinate board, the same operation as described above is performed via the mirror board M '.

[0031]

In the dual system multiprocessor system according to the present invention, the mirror memory has a bidirectional memory for storing data, and a mirror memory when data is exchanged in one of the two systems. Writing means for writing the data into the bidirectional memory at the same time; and taking means for taking the data written by the writing means into the processor board of the other of the two systems , The address of the bidirectional memory is
Space allocated when data is exchanged between
Data is written to the bidirectional memory in one system.
Since the processing is performed at the time of data reading , the master system does not need to perform special processing for data transmission to the slave system, so that processing efficiency can be improved. Further , the frequency of using the system bus can be reduced. Further, confusion of data at the time of reading can be prevented. Further , when the data written to the bidirectional memory is stored in a storage circuit for temporarily storing data, the data can be processed while effectively avoiding a conflict between the two systems.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an electrical configuration of a mirror memory.

FIG. 3 is a time chart of the system according to one embodiment.

FIG. 4 is a schematic configuration diagram showing an example of a conventional system.

FIG. 5 is a schematic configuration diagram showing another example of a conventional system.

[Explanation of symbols]

1a, 1b Bus buffer 2 Temporary storage circuit 3 Bidirectional memory 4a, 4b Control circuit 5 Counter circuit (CNT) 6 Flip-flop circuit (FF) L, L 'System bus A to N, A' to N 'Microprocessor board (Board) M, M 'mirror memory (writing means, capturing means)

──────────────────────────────────────────────────続 き Continuing on the front page (72) Atsushi Takeko, Inventor 2-8-8 Hikaricho, Kokubunji-shi, Tokyo Inside the Railway Technical Research Institute (72) Inventor, Masatoshi Umeyama 1-13, Kamikizaki, Urawa-shi, Saitama No. 8 Inside the Yono Works of Nippon Signal Co., Ltd. (72) Inventor Yoshio Usami 2-20-2 Nakaikekami, Ota-ku, Tokyo Daiko Signal Co., Ltd. (56) References JP-A-3-252852 JP-A-3-142534 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/16-11/20 G06F 15/16-15/177

Claims (2)

(57) [Claims] 1. A main multiprocessor having a plurality of processor boards connected to a main system bus, and a plurality of processor boards corresponding to respective main processor boards connected to a sub system bus. A multi-processor system comprising a slave multi-processor and a mirror memory provided between the two system buses, wherein the mirror memory includes a bi-directional memory for storing data; when the communication data is performed in one system of both systems, at the same time a writing means for writing the data to the upper Symbol bidirectional memory, the two data written in the writing means and a capturing means for capturing the other system processor board of one of the systems, a of the two-way memory
The dress is empty, which is different from when the processors exchange data.
Space allocated and writing data to its bidirectional memory
Is performed at the time of data reading in one of the systems. 2. The data written to the bidirectional memory is data
2. The dual multiprocessor system according to claim 1 , wherein the data is stored in a storage circuit for temporarily storing data .