JPH0572619B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control method in a computer, and more particularly to a common bus control method in data transfer of a multiprocessor.

(Prior Art) Conventionally, there have been two types of control methods of this type: the semaphore method and the burst method. The following description assumes that the transfer data is 3 bytes, and that the data that can be transferred in one bus cycle of the common bus is 1 byte.

Figure 3 is a time chart of the semaphore system, where 10 is the semaphore flag, 11 is the data on the common bus, 12 is the data on the local bus of CPU1, 13 is the data on the local bus of CPU2, 1
4 and 21 are semaphore test and set timings, 15, 17, and 19 are data transfer timings for CPU1, 16 and 18 are semaphore test timings, 20 and 25 are semaphore release timings, and 22, 23, and 24 are CPU2 data transfer timings. This is the data transfer timing.

Figure 4 shows the configuration of the data transmission buffer using the semaphore method in Figure 3, where 26 is the area where the transfer from the CPU has been completed, 27 is the 3-byte data area transferred by CPU1, and 28 is the area transferred by CPU2. A 3-byte area, 29, indicates a free area. In this figure, 15, 17, 19 and 22, 2
3 and 24 indicate data of time slots with corresponding numbers in the time chart of FIG. Now, when CPU1 tries to transfer 3 bytes of data, CPU1 first tests the semaphore flag at timing 14, and since it is not prohibited, sets the prohibition bit. The CPU 1 transfers 3 bytes of data in three bus cycles of 15, 17, and 19, and releases the semaphore at timing 20 to end the transfer. When CPU2 tries to transfer data while CPU1 is transferring data, it tests the semaphore at timing 16, and since it is prohibited,
Repeat the test at timings 8 and 21. 2
Since semaphore is not prohibited at timing 1,
Set the prohibition bit in the semaphore flag and 22,
Three bytes of data are transferred in three bus cycles at 23 and 24, and the semaphore is released at 25 to end the transfer. With the above control, CPU1 and CPU
CPU 1 and CPU 1 on the data transmission buffer common to 2.
Data from CPU2 will not be mixed.

FIG. 5 is a time chart of the burst method, where 30 is the bus lock signal, 31 is the data on the common bus, 32 is the data on the local bus of CPU1,
33 is the data of the local bus of CPU2, 34,
35 and 36 are the data transfer timings of CPU1,
37, 38, and 39 are data transfer timings of the CPU2.

FIG. 6 shows the buffer for data transmission using the burst method in FIG.
The 3-byte data area transferred by 43 indicates an empty area. Here, 34, 35, 36 and 3
7, 38, and 39 indicate data of time slots with corresponding numbers in the time chart of FIG. When CPU1 transfers 3 bytes of data,
First, it locks the common bus to prevent other CPUs from monopolizing the bus and transfers data. Release the bus after the transfer is complete. The CPU 2 then occupies the bus and transfers data. Therefore, even in the burst method, data from CPU1 and CPU2 will not be mixed on the transmission buffer.

(Problems to be solved by the invention) In the conventional semaphore system described above,
When the CPU transfers data, it must check the flag and periodically check the flag when the transfer is prohibited, which has the disadvantage that data transfer cannot be performed efficiently. Another disadvantage of the burst method is that since one CPU occupies the bus for a long time, other CPUs cannot occupy the bus, causing processing to temporarily stop.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a common bus control method that allows efficient data transfer and prevents one CPU from occupying the common bus for a long time.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides means for connecting a plurality of CPUs to a common data transmission/reception buffer via a common bus, and for each bus access, In the method of performing arbitration and transferring bytes one byte at a time, a pointer indicates the start address of the free area of the data transmission/reception buffer, the CPU reads the value of the pointer in one bus cycle before data transfer, and the pointer It is characterized in that a new pointer value is generated by adding the number of transferred bytes and the current pointer value within a cycle.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system diagram of one embodiment of the present invention. 1, 2, and 3 constitute a multiprocessor
4 is a common bus, and 5 is peripheral equipment such as a communication control device for transmitting and receiving data. In this example, when 1 transfers a large amount of data to 5, multiple bus cycles are required. if,
When 2 transfers data to 5 between bus cycles, buffer 5 transfers data from 1 to 2.
It must be prohibited because it mixes with other data.

FIG. 2 is a conceptual diagram showing the configuration of a storage area of a transmission buffer in the peripheral device 5. As shown in FIG. p is a pointer indicating free space in the transmission buffer, n and m are the size of the transmission buffer occupied by one signal, 6 is the area where data transfer from the CPU is completed, 7 is the CPU 1
8 indicates the transfer area of the CPU 2, and 9 indicates the free area of the transmission buffer.

When 1 transfers data to 5, it first reads p. At this time, p is automatically updated to p+n within the bus cycle in which p is read. n is the size of data that 1 transfers. The pointer consists of an adding circuit, which adds the size n of the transfer data to the pointer value p indicating the free space in the transmission buffer,
Generate a pointer value for CPU1. 1 is p
Transfer the data to the location indicated by . If 2 transfers data to the same sending buffer while 1 is transferring data, or if it tries to read the pointer at the same time, 2 will be forced to wait by bus arbitration and will not be able to read p in the next bus cycle after 1 reads p. Since we read the pointer, we get p+n. At this time, the pointer is p+n+
m. m is the size of data transferred by 2. The following explanation will be given using a timing chart assuming that the transfer data is 3 bytes and 1 byte is transferred in one bus cycle of the common bus.

FIG. 7 is a timing chart of data transfer in the embodiment shown in FIG. 1, where 44 indicates the contents of the pointer, 45 indicates data on the common bus, 46 indicates data on the local bus of CPU1, and 47 indicates data on the local bus of CPU2. . 48 indicates the timing at which the CPU 1 reads the pointer, and 50 indicates the timing at which the CPU 2 reads the pointer. 49,51,
53 is the timing when CPU1 transfers data,
52, 54, and 55 indicate timings at which the CPU 2 transfers data. Figure 8 shows m in Figure 2.
The configuration of the data transmission buffer in the case where =n=3 is shown. 56 is an area where data transfer from the CPU has been completed, 57 is a 3-byte data area transferred by CPU 1, 58 is a 3-byte data area transferred by CPU 2, and 59 is an empty area. 49, 51, 53 and 52, 54, 55 indicate data of time slots with corresponding numbers in the time chart of FIG.

When CPU1 transfers 3 bytes of data,
At timing 48, read 44 and obtain p. At this time,
The contents 44 of the pointer become p+3. and,
CPU1 transfers 3 bytes from the address indicated by p. When the CPU 2 transfers data, it reads 44 at timing 50 and obtains p+3. At this time, 44 becomes p+6. CPU2 transfers 3 bytes to three consecutive addresses starting at p+3.
Therefore, since the transmission buffer transfer areas of CPU1 and CPU2 are different, data will not be mixed with each other.

(Effects of the Invention) As described above, in the present invention, by updating the pointer for buffer management within a read bus cycle, a plurality of CPUs can simultaneously transfer data to the same buffer. Therefore, according to the present invention, data can be efficiently transferred and
It is possible to provide a common bus control method that prevents two CPUs from occupying the common bus for a long time.

[Brief explanation of the drawing]

Figure 1 is a system diagram of one embodiment of the present invention, Figure 2 is a system diagram of an embodiment of the present invention.
The figures are a conceptual diagram showing the configuration of the transmission buffer in the peripheral device 5 in the embodiment shown in FIG. 1, FIG. 3 is a time chart based on the Semapho system, FIG. The figure is a time chart according to the burst method, and FIG. 6 is a diagram showing the configuration of a transmission buffer according to the burst method.
FIG. 7 is a time chart in the embodiment shown in FIG.
FIG. 8 is a diagram showing the configuration of the transmission buffer in the embodiment of FIG. 1 when the transfer data is 3 bytes and 1 byte is transferred in one bus cycle of the common bus. 1, 2, 3...CPU, 4...Common bus, 5...
...Peripheral equipment for data transmission and reception, 6, 26, 40, 5
6... Area where the transfer from the CPU has been completed, 7,
8...Area where data is being transferred from the CPU, 9,2
9, 43, 59...Batsuhua's vacant area, 10
...Semapho flag, 11, 31, 45...
Data on the common bus, 12, 32, 46...
Data on local bus of CPU1, 13, 33,
47...Data on the local bus of CPU2, 1
4, 21... Semaphore check and set timing, 15, 17, 19, 34, 35, 36,
49, 51, 53... Data transfer timing of CPU1, 16, 18... Semaphore check timing, 20, 25... Semaphore release timing, 22, 23, 24, 37, 38, 39, 5
2, 54, 55... Data transfer timing of CPU2, 27, 41, 57... Transfer data area from CPU 1, 28, 42, 58... Transfer data area from CPU 2, 30... Bus lock signal, 44... Contents of pointer, 48, 50... Pointer reading timing.

Claims (1)

[Claims] 1. In a method in which multiple CPUs are connected to a common data transmission/reception buffer via a common bus, bus arbitration is performed for each bus access, and one byte is transferred, the starting address of the free area of the data transmission/reception buffer is indicated by a pointer, The CPU reads the value of the pointer in one bus cycle before data transfer, and the pointer generates a new pointer value by adding the number of transferred bytes and the current pointer value within the one bus cycle. Features a common bus control method.