GB2060961A - Data processing system having memory modules with distributed address information - Google Patents

Abstract

A plurality of modules are distinguished from each other by high-order memory address bits while locations in each memory module are addressed by low-order memory address bits. Each of the memory modules includes a memory identifier means for storing a high- order identifier address and a comparator means for comparing the high-order address bits of an address applied to all modules with the identifier address. If they match, an identifier signal is provided enabling the memory module to be addressed with the low-order address bits. All memory modules which do not have a match between the identifier address and the high-order memory address are not enabled. Different numbers of high and low order bits may be used in different modules depending on their storage capacity. The numbers used are set in each module by a switch. The enabling identifier signal lines of all modules are connected to provide a signal indicating that one module has responded to a high order address.

Description

SPECIFICATION Data processing system having memory modules with distributed address information Background of the invention The present invention relates to the field of digital computers and particularly to memory units, sometimes called storage units, for use within such systems.

Data processing systems come in many different sizes and have many different memory requirements. Frequently it is desirable to upgrade or otherwise alter the memory capacity or composition.

In conventional memory design, memory modules are addressed by a standard address (for example, 21 bits) having a lower-order field and a higher-order field. The high-order bits of an address are conventionally decoded in a centralized decoder to select one of several memory modules and the selected module is then addressed by the remaining loworder bits. Such decoders conventionally have explicit enable lines which connect directly from the centralized decoder to the different memory modules. The use of such a decoder and the enable lines is undesirable when a modular memory with a modular bus structure is desired.

Accordingly, it is the objective of the present invention to provide an improved modular memory structure suitable for modular data processing systems.

Summary of the invention The present invention is an improved memory apparatus having address information distributed among a plurality of memory modules. Memory modules are distinguished from each other by the high-order memory address while locations in each memory module are addressed by the low-order memory address. Memory addresses, formed of high-order and low-order addresses, for addressing the memory locations are communicated in parallel to all of the memory modules. Each of the memory modules includes a memory identifier means for storing a high-order identifier address. Each module includes comparator means for comparing the highorder address with the identifier address and if they match, an identifier signal is provided enabling the memory module to be addressed with the low-order address bits.All memory modules which do not have a match between the identifier address and the high-order memory address are not enabled.

The method of module identification of the present invention provides great flexibility in changing the size of address modules connected to the storage unit, or in adding or otherwise modifying the configuration of the modules comprising the storage unit.

Additional objects and features of the present invention will appear from the following description in which the preferred embodiments of the invention have been set forth in detail in conjunction with the drawings.

Brief description of the drawings Figure 1 is an overall block diamgram of a digital computer employing the modular storage unit in accordance with the present invention.

Figure 2 is a block diagram showing further details of a typical one of the memory modules within the storage unit of the Figure 1 system.

Figure 3 is a block diagram of the system bus interface and the storage unit used with the digital computer of Figure 1.

Figures 4 and 5 represent electrical schematic diagrams of the control circuitry within the storage unit of Figure 1.

Figure 6 is a block diagram representing waveforms of the signals employed in the operation of the present invention.

Detailed description In Figure 1, a schematic block diagram of a digital computer is shown. The digital computer includes a processor unit 34, a storage unit 35 and a plurality of input/output (I/O) units 36, designated 36-1,36-2 36-N. The units 34,35 and 36 are interconnected by a system bus 37.

Input/output units such as units 36 of Figure 1 typically include controllers and channels for communicating with input/output devices such as magnetic tape units, magnetic disk units and other peripheral units used with digital computers. In a typical system, an operator console is connected through one of the input/output units 36 to the remainder of the system.

The system bus 37 connects to each of the units of Figure 1 through a separate interface for each unit.

Particularly, the processor unit 34 includes one or more system bus interfaces such as interfaces 34-1 and 34-1'. The storage units 25 and 35 include storage unit system bus interfaces 35-1 and 25-1.

Each of the I/O units 36 includes a corresponding system bus interface 39. The interfaces 39 are designated 39-1,39-2 39-N in Figure 1 corresponding to the I/O units 36-1,36-2 36-N, respectively.

In a typical embodiment, the system bus 37 has an information field which is 32 bits wide. The system bus information field carries information of different types between the various units of Figure 1. The system bus 37 also includes a bus operation code field which in one embodiment is 8-bits wide. The operation code field (OP CODE) is encoded to specify the different types of information that are carried by the information field of the system bus.

In addition to the information field, and the operation code field, the system bus 37 includes a number of explicit lines. Among those lines are the priority lines including a parallel priority bus and serial priority lines. Additionally, each priority circuit receives priority setting lines for setting the parallel priority level of the particular priority circuit.

A typical system bus operation commences when one of the units connected to the system bus has a need to utilize the system bus. The processor unit and the I/O units are all capable of requesting access to the system bus. Any unit needing to access the system bus generates a bus request signal. Since more than one unit may request access to the system bus, the priority circuitry functions to establish priority among the units requesting access to the system bus.

If no unit of higher priority is requesting access to the system bus and if the system bus is not currently busy, then a unit seeking access to the system bus will access and take control of the system bus.

When a unit takes control of the system bus, the unit generates a bus busy signal indicating the system bus is busy and hence that no other unit can obtain access until the particular unit is finished with its operations on the system bus. The priority circuitry determines which one of the units seeking to acquire the system bus is the next one to acquire access to the system bus in accordance with the invention described and claimed in the aboveidentified cross-reference application entitled DATA PROCESSING APPARATUS WITH SERIAL AND PARALLEL PRIORITY.

Further details of one system bus and its operation in a system suitable for use with the present invention are described and claimed in the above identified cross-referenced application DATA PROCESSING APPARATUS AND METHOD WITH ENCODED SYSTEM BUS.

In Figure 1, the storage unit 35 includes a memory unit 404. Memory unit 404 is comprised of the memory modules MO, Ml ..., MN which are desig- nated 670-0,670-1 670-N. Collectively the modules are referred to as the modules 670. Each of the modules is identical or substantially identical. The modules 670 all receive the 32-bit information field from the system bus 37. The information field is identified as bus 37-1 and includes the bits -SYS BUS(0-31). The 32-bit information field of bus 37-1, is connected as an input memory address bus to each of the modules 670.

Each of the modules 670 also receives the 64-bit data bus 406. The data bus 406 is bidirectional and connects to and from the system bus interface 35-1.

Each of the modules 670 also receive in parallel the seven control lines forming the storage control bus 658.

Memory Module - Figure 2 In Figure 2 memory module 670 is typical of all the modules 670-0,670-1 670-N in Figure 1. The module 670 connects to the 64-bit data bus 406, the 32-bit address bus 37-1 and the storage control bus 658.

In Figure 2, the seven control lines comprising the storage control bus 658 are -REFRESH, -COLUMN ADDRESS STROBE, -WRITE STROBE, -ROW ADDRESS STROBE, -GATE DATA FROM STORAGE, -HOLD ADDRESS, -STORAGE CARD SELECTED and they connect to the gates 661 through 667, respectively. Gates 661 through 665 are conventional inverter drivers and gate 666 is non-inverting. Gate 667 is a conventional NAND gate and provides -STORAGE CARD SELECTED as the only output signal of bus 658.

In Figure 2, the memory card 671 is a memory means such as constructed from semiconductor memory chips and includes the memory locations which are to be addressed by the low-order address from the memory address on address bus 37-1. The memory address bits from bus 37-1 are inverted in the inverter gates 673 and are stored in address register (ADDR REG) 659. Register 659 stores the low-order address, comprised of "L" bits, which is employed to address the memory card 671. The low-order address from register 659 connects through conventional drivers 672 for addressing - memory card 671. The high-order address, comprised of "H" bits, from inverter gates 673 is connected by bus 657 as an input to a comparator 675. Comparator 675 is a conventional device, such as formed by EXCLUSIVE-OR gates, one for each of the "H" bits on bus 657.The other input to comparator 675 is from the high-order identifier address register 660. Register 660 can be any conventional storage or other device for providing input signals to a comparator. In one embodiment, register 660 is formed of switches which function to connect each of the identifier address bits to a logical 1 or a logical 0. The number of identifier address bits connected from identifier address register 660 is the same as the number "H" of high-order address bits connected to the comparator on the bus 657. The number "H" of high-order bits input to comparator 675 and the number "L" of low-order bits input to the memory card 671 is, of course, a function of the size of the memory card 671. A switch 655 or other means is provided for selecting the relative sizes of "L" and "H". Typically, for a 32K memory card, "L" is 15.If 21 address bits (rather than 32) are employed, then "H" will be up to 6 bits depending on the total memory capacity, that is, the number of modules employed.

In the present invention, "H" and "L" can be different for every module.

In Figure 2 whenever the value of the high-order bits on buses 655 and 657 are identical, the comparator 675 provides the +SETTHIS CARD SELECTED signal active as a logical 1. The +SET THIS CARD SELECTED signal connects to the D input of flip-flop 674 and its logical 1 or logical 0 value is stored there on a positive-going transition of the -HOLD ADDRESS signal connected through driver 666 to the clock input of flip-flop 674. The logical 1 or logical 0 is stored in flip-flop 674 at the same time that the low-order address is stored in the register 659. The -HOLD ADDRESS signal is generated so that the output from comparator 675 is valid for the memorv address when the low-order address is stored in register 659.

The Q output of flip-flop 674 in the identifier Y address signal designated +THIS CARD SELECTED and that output connects as an input to the NAND gates 668 and 669. When +THIS CARD SELECTED is a logical 1, each of the gates 667,668 and 669 is enabled, signifying that the card 670 of Figure 2 is identified by the high-order address on bus 37-1 and the identifier address as the one to be active. Gates 668 and 669 enable the memory card to be accessed eitherto read or write data. Gate 669, when enabled, connects the inverted -ROW ADDRESS STROBE signal to the memory card 671 and gate 668, when enabled, connects the inverted -DATA FROM STOR AGE signal to the memory card 671. Similarly, INVERTER gates 661,662 and 663 connect the -REFRESH, -COLUMN ADDRESS STROBE and -WRITE STROBE signals, respectively, directly to the memory card 671.These signals are conventional signals for accessing memory cards for reading and writing data in a conventional manner.

Data to be written into the memory card 671 is supplied over the bus 406 and data to be read from the card 671 appears as an output on bus 406. Bus 406 is a 64-bit wide bus for carrying data. Memory card 671 typically includes additional input and output bits for error correction and detection. Such error correction and detection bits have not been shown since they can be implemented in any conventional manner.

In Figure 2 the output from the comparator 675 is the module identifier signal and it is connected to both inputs of the NAND gate 667. Gate 667, therefore, acts as an inverter to form the -STORAGE CARD SELECTED signal. Whenever +SET THIS CARD SELECTED signal is active as a logical 1, the +STORAGE CARD SELECTED signal is active as a logical 0. The output from gate 667 for the module 670 of Figure 2 connects to similar outputs for all of the modules like module 670 in Figure 1. If any one of the modules 670-0,670-1 670-N of Figure 1 has a logical 0 output from its corersponding gate 667, the -STORAGE CARD SELECTED signal will be a logical 0.That logical 0 signals to the control circuitry within the system bus interface 35-1 that at least one of the modules within the storage unit 35 has recognized the high-order address and hence will employ the low-order address to access locations within the memory stores of that module.

Storage Unit And System Bus Interface - Figure 3 In Figure 3, the storage unit 35 of Figure 1 and its system bus interface 35-1 is shown.

In Figure 3, the major components of the system bus 37 of Figure 1 are the 32-bit information field -SY BUS(0-31 ), the 8-bit operation code field -BUS OP(0-7), and various explicit signal lines 213 and 214.

The signal lines include -PRIORITY 1,-PRIORITY 2, -PRIORITY 4, -BUS REQUEST IN, -BUS REQUEST OUT, -PRIORITY 1 REQUEST, -PRIORITY 2 REQUEST, and -PRIORITY 4 REQUEST. Additional lines include -CANCEL, -SYSTEM RESET, -SURPRESS INTER RUPTS, -MEMORY BUSY, -CONTROLLER ADDRESS, -MACHINE CHECK, -DISPLAY SYNC, -DISPLAY BUS, -BUS BUSY, -UNIT BUSY and -ACKNOWLEDGE which connect to the bidirectional drivers 204. An additional signal, -CLOCK, is distributed throughout the system to each of the units to synchronize all operations on the system bus.

The -CLOCK signal is connected as an input to the clock unit 64. The clock unit 64 is a conventional device for providing clock signals at the frequency determined by the -CLOCK signal. In one embodiment, the -CLOCK signal has a 100 nanosecond period. The clock unit 64 buffers and inverts the -CLOCK signal and provides conventional clock signals such as +CLK and -CLK for distribution internally throughout each of the units.

In Figure 3, the bus 37-1, -SY BUS(0-31), connects to the bidirectional driver circuit 202. Driver 202 inverts signals on each of the 32 lines 37-1 and connects them over an input bus 401, +SB IN(0-31), to a latch 206-1 and to a latch 206-2 each 32 bits wide. Latch 206-1 receives and stores data from the bus 401 under control of the + LOAD DATA IN(0-31 signal from control 405. Similarly, the latch 206-2 receives and stores data from the bus 401 under control of the + LOAD DATA iN(32-63) signal from control 405.

The outputs from the latches 206-1 and 206-2 connect in parallel as an input to a conventional 64-bit bidirectional driver and receiver (D and R) 406.

The 64-bit input/output from driver/receiver 406 is the storage data bus 408 which connects to/from the memory unit 404. Information from the memory unit 404 over the storage data bus 408 is gated, through the driver/receiver 406, under control of the -GATE DATA TO STORAGE signal, onto the 64-bit bus 409.

Bus 409 is split into two 32-bit parts and one part (bits 0-31) connects as an input to the latch 207-1 and the other part (bits 32-63) connects to the latch 207-2.

The outputs from latches 207-1 and 207-2 in as inputs to multiplexer 410. Multiplexer 410 selects the output from latch 207-1 whenever the -GATE DATA OUT(0-31) signal is a logical 0 and selects the output from latch 207-2 whenever that signal is a logical 1.

The selected data from the latches 207-1 and 207-2 appears as the +SB OUT(0-31) bus 402. The control 405 generates the -ENABLE SYS BUS DR signal for enabling the control gate 202-1 in Figure 3 for connecting the information on the +SB OUT(0-31) bus 402 to the system bus output -SY BUS(0-31).

In a typical embodiment, the latch circuit 205 includes an input latch (IN LAT) 206 which latches the data from the bus -SY BUS(0-31) under control of the rising edge of +LOAD DATA IN which switches with the rising edge of the clock signal +CLK. When latched, the information from circuit 206 is available on the 32-bit system bus latch in bus 217, +SB LCH lN(0-31), which connects to other circuitry 31 located in the system bus interface 31 or located in other circuitry in the storage unit connected to the system bus interface.

In Figure 3, the 8-bit bus 37-2, -BUS OP(0-7), carries the bus operation code field and connects to a bidirectional driver 203. Bidirectional driver 203 is like or similar to the driver 202. Data from -BUS OP(0-7) is connected through driver 203 to the 8-bit input latch 209, OP IN LAT. In the preferred embodiment, latch 209 latches the 8-bit bus op from -BUS OP(0-7) on the rising edge of the signal +LOAD OP IN which is typically switched by the rising edge of the clock signal +CLK. In an alternative embodiment, the bus +OP IN(0-7) by-passes the latch 209 and connects on bus 469 as an input to the system bus op code decoder 212 (SB OP DEC).

In a similar manner, bus ops from the functional unit 31 may be, in some embodiments, clocked into the 8-bit output latch (OP OUT LAT) 210 by the rising edge of +CLK which controls the +LOAD OP OUT signal. When latched in buffer 210, the bus operation field is then available for gating out to the -BUS OP(0-7) bus under control of the -ENABLE SYS BUS DR signal. In an embodiment for the storage unit interface 35-1, latch 210 is not employed. Alternatively, a HEX F code generator 530 is employed.

Whenever -ENABLE SYS BUS DR is active as a logical 0, inverter 531 inputs that signal to form logical 1's for the four high-order bits +OP OUT(0-3) thereby forcing HEX F as binary 1111. The four low-order bits +OP OUT(4-7) remain logical 0's.

The 8-bit +LCH OP IN (0-7) lines from the buffer 209 or alternatively from the driver 203 connect to the system bus operation decoder 212. The decoder 212 functions to decode the system bus op provided by the system bus 37. Decoder 212 typically has a unique decoding for each of the units to which the system bus interface of Figu re 3 is connected. The outputs from decoder 212 provide signals to the functional unit 31 for specifying the nature of the information on the bus 37-1, -SY BUS(0-31). The functional unit31 determines whether or not to accept information provided by -SY BUS(0-31) of the nature specified by the op code provided by -BUS OP(0-7).

The signal lines 213 similarly are or can be bidirectional and connect to the drivers 204. The drivers 204 convert the bidirectional lines on the left to the pair of unidirectional lines on the right. For example, the -CANCEL line on the left of drivers 204 connects as the +CANCEL OUT and the +CANCEL IN lines on the right. The names of the signals on the right correspond to the names of the signals on the left with the additional designation OUT (representing signals transmitted out to the system bus)-and the designation IN (representing signals received in from the system bus). The OUT and IN signals from the drivers 204 connect to the functional unit 31.

In Figure 3, the lines 214 connect to a priority circuit 215. The priority circuit 215 for each of the system bus interfaces like that of Figure 3 establishes the priority among the units which are connected to have access to the system bus. Priority circuit 215 is connected to the functional unit 31 for interpreting the priority information.

Storage Control - Figures 4 and 5 The storage control 405 of Figure 3 is shown in detail in Figures 4 and 5. The control circuitry of Figures 4 and 5 can be implemented using circuits in many different technologies. In one particular embodiment, TTL circuits are employed of the SN74-series marketed by Texas Instruments Incorporated. Of course, the invention is independent of any particular type of circuits employed. In Figures 4 and 5 the AND, NAND, OR, NOR, INVERTER, and AND-OR INVERT gates and the other circuits are all standard TTL components. In Figure 4, counter 450 in one typical embodiment is a type -S163, decoder 454 is a type -S138 and the JKflip-flops 445 are type -S376.

The D type flip-flops 470-2 and 470-3 are typically type -S374. In Figure 5, the D type flip-flops 417,431 and 470 are typically type -S374. The JK flip-flops 432 are typically type -376.

Further details of the Figure 4 and Figure 5 circuitry including specific interconnection of the elements is apparent from an inspection of those figures.

The generation and operation of the signals in Figure 4 and Figure 5 is described in connection with the timing diagram of Figure 6.

Signal Timing - Figure 6 In Figure 3, the system bus clock, -CLOCK, appears from the system bus as an input to the system bus interface and is buffered in a clock unit 64to form the +CLK signal and is reinverted to form the -CLK signals. Referring to Figure 3 and Figures 4 to 6, the +CLK and the -CLK signals are synchronous with, but delayed from, the -CLOCK signal and are distributed throughout the control circuitry for synchronizing the timing of the system bus. In general, actions are controlled on the system bus by the falling (negative-going) edge of the -CLOCK signal and similarly therefore the falling edge of the -CLK signal or the rising (positive-going) edge of the +CLK signal. As shown in Figure 6 for example, the falling edges of -CLK and the rising edges of +CLK appear at times C1, C3, CS ..., and so on.In general, signals that are clocked onto the system bus by one falling edge of the -CLOCK signal are sampled by the next falling edge of the -CLOCK signal. In a typical embodiment, the -CLOCK signal has a 100 nanosecond period and the delay for producing +CLK is approximately 6 nanoseconds. For purposes of explanation, however, that 6 nanosecond delay can be ignored as a minor design detail.

In a typical operation the interface apparatus of Figure 3 does not make a positive request for access to the system bus but obtains access to the system bus to satisfy requests from other units connected to the system bus. For purposes of explanation, therefore, operation commences at a point in time when some other unit (for example processor unit 34) has made a request for the system bus. In describing this operation, the signals represented throughout the specification and drawings with a negative sign ("-") are negative-true so as to be active with a logical 0 and with a positive sign ("+") are positivetrue so as to be active with a logical 1.

BUS REQUEST. Referring to Figure 6, the assumed operation causes the -BUS REQUEST signal on the system bus to go low at time C1 of the -CLK signal.

At time C1, it has been assumed that the processor unit 34 of Figure 1 issued a request for access to the system bus by making -BUS REQUEST go low. That signal remains in the low (active) state for two clock cycles measured between times C1 and C5. If during the time from C1 to C3 no unit of higher priority than the processor unit is making a request for access to the system bus, and if the system bus is not busy, and if the requested access is for a storage unit operation and the storage unit is not busy, then the processor unit 34 acquires the system bus and places a bus op code on the bus op code field, -BUS OP(0-7) together with bus data on the bus information field, -SY BUS(0-31), by operation of Figure 3 interface.

As shown in Figure 6 the -BUS OP(0-7) signal ("DX") representing the bus op code and the -SY BUS (0-31) signal ("ADD" denoting "address") representing the system bus data both appear between times C3 and C5. That address of the system bus 37-1 connects as an input to the storage unit 35 and particularly to each of the modules 670-0,670-1 ....

670-N of Figure 1.

At C1 time, both the -BUS BUSY and the -MEM ORY BUSY signals are high (inactive).

These initial conditions permit the processing unit 34 of Figure 1 to acquire access to the system bus and to place the bus op code and the bus data onto the system bus between times C3 and C5.

The system bus interface of Figure 3 and the control circuitry of Figures 4 and 5 responsively react in the following manner.

Storage Cycle Counter. During a storage operation, there are a number of functions which must be performed. In orderto control the timing of these functions, storage cycle counter 450 in Figure 4 is sequenced. The details of counter 450's operation are described in the above cross-referenced application entitled DATA PROCESSING APPARATUS AND METHOD WITH ENCODED SYSTEM BUS.

Counter 450 does not always count every number in the sequence because, at times, it is parallel loaded with different numbers so that the number of counts counted by counter 450 changes as a function of the operation to be performed. The different counting sequences account for the different duration storage cycles that are required to perform various storage operations. For a fetch cycle, the counter counts 0, 1,4,5,6,7. For a full store, the counter counts 0, 1,4, 5, 6,7. For a partial store, the counter counts 0, 1, 2, 4, 5, 6, 7. For a refresh operation, the counter counts 0,4, 5,6, 7. These different counting sequences are controlled by the time at which the counter 450 is parallel loaded to the four count.The parallel loading is under control of the LD input which is controlled to parallel load by the NOR gate 461.

Each time the storage cycle counter of Figure 4 is cleared for a new storage operation and starts counting, it is parallel loaded at some point in time to a count of 4 or 6. After being thus loaded, the counter 450 continues counting until count seven. When count seven (-T7 is logical 0) is reached, counter 450 is disabled to await the start of a new storage operation.

It will now be assumed, for purposes of explanation, that the FETCH operation of Figure 6 is to be continued. In Figure 6 when the -START NEW STORAGE OP signal is a logical 0 and becomes stored in stage 1 of flip-flops 431 at C5 time, gate 598 and gate 597 each have 0 outputs which cause the counter 450 to be cleared on the next positive-going transition of -CLK at time C6. Since it is a fetch operation, as signified by DX in the bus op field, the storage control counter 450 is to be sequenced through the counts which are decoded as-TO, -T1, -T4, -T5, -T6, -T7. Counter 450 assumes the counts representing those decoded outputs at the positivegoing transitions of -CLK namely, at time C6, C8, C10, C12, SC14and C16.

BUS BUS Yand MEMOR YBUS Y. The -BUS BUSY signal is activated whenever the system bus is being accessed by any unit. The -BUS BUSY signal is activated (logical 0) by any unit when that unit acquires access to the system bus. The -BUS BUSY signal is inactivated one cycle prior to the end of the units operation on the system bus.

Referring now specifically to Figure 6, -BUS BUSY is initially active between times C3 and C13. At time C3, -BUS BUSY is switched from inactive to active by the requesting unit. The requesting unit will hold the -BUS BUSY signal active for one or two cycles, that is, until time C5 or C7.

Referring to Figure 5 and to Figure 6, at time C3 and the -BUS OP(0-7) op code field contains a bus op code DX signifying that a fetch operation is called for. In Figure 5, that bus op code appears on bus 469 as an input to the bus op decoder 212. Decoder 212, in a conventional decoding manner, senses the presence of either a HEX C (store operation) or a HEX D (fetch operation) and responsively activates the output line 466. Accordingly, between time C3 and C5, line 466 from decoder 212 is activated as a logical 1 (high) to enable the NAND gates 427 and 428 and is inverted in INVERTER gate 429 to activate the -STORAGE BUS OP signal as a logical 0. If the storage unit is not busy and hence can honor the request for a fetch of data, NAND gate 427 will be satisfied to activate the -START NEW STORAGE OP line as a logical 0 (low).If the storage unit is busy, NAND gate 428 will be satisfied to set the -SET STORAGE OP PENDING line active as a logical 0. The busy or not busy condition of the storage unit (memory unit 404 of Figure 3) is indicated by the -BUSY signal output from the AND gate 422.

Whenever operations are to be performed by the storage unit involving the circuitry of Figure 3, the storage cycle counter 450 in Figure 4 counts through various stages to control the sequencing of the storage control operation.

The -T7 output as a logical 0 from decoder 454 signifies that the storage operation is inactive awaiting the start of a new storage operation. The -T7 decoded output from decoder 454 is inverted in INVERTER gate 532 to form an input to the AND gate 422 in Figure 5. The other input to AND gate 422 is a signal from NAND gate 442 which signifies with a logical 1 that no refresh operation is to be started. In the absence of a refresh operation and if the storage cycle counter is in the wait state, then gate 422 is satisfied to provide a logical 1 inactive signal for -BUSY.

Under these conditions, the NAND gate 427 becomes satisfied to provide a logical 0 for the -NEW STORAGE OP signal. If -BUSY from gate 422 were as a logical 0 active then gate 427 would not be satisfied but gate 428 would be satisfied to set -SET STOR AGE OP PENDING active as a logical 0. the next clock cycle after time C3, the outputs from gate 427, 428, and 429 are clocked, by the positive-going transition of +CLK, into the D1, D2 and D3 inputs respectively, of the first three stages of the flip-flops 431. That clocking occurs at time C5. Accordingly at C5 time, either the Q1 or the Q2 output and the Q3 output of flip-flops 431 are clocked to a logical 0.

Both the Q1 and Q2 outputs connect as inputs to the NAND gate 423. A logcial 0 from Q1 or Q2 of flip-flops 431 forces the output of gate 423 to a logical 1 which in turn enables the NAND gates 584 and 585. Another input to both gates 584 and 585 is the seven stage Q7 output of the D-type flip-flops 417. The Q7 output is normally a 1 except when an operation is to be aborted. The third input to gate 585 is from INVERTER gate 512 which inverts the Q8 output from flip-flops 417 to form the -BUS OPER(3) signal. The Q8 output of flip-flops 417 is the +BUS OPER(3) signal which is the positive-going transition of +CLK. The D8 input connects from the output of the AND-OR-INVERT gate 418.

The AND-OR-INVERT gate 418 functions to receive the bus op code bit 3 as the +OP IN(3) signal appearing on line 467 which is derived, through decoder 212, from the driver 203 of Figure 3. In Figure 5, the lower AND gate portion also receives the inverted output from AND gate 584. The upper AND gate portion of gate 418 receives the direct output from AND gate 584 and the +BUS OPER(3) signal drived from gate 512 and the Q8 output from the eighth stage of flip-flops 417. In the present example, when a fetch operation is specified, after C3 time when +OP IN(3) is a logical 1 ,the output from gate 584 is still a logical 0 since gate 584 has not yet been enabled by the output of gate 423 (which will not occur until after C5 time).Therefore, prior to C5 time, the input to both inputs to the lower AND gate portion of gate 418 are logical 1's. Those 1's cause a logical 0 output from gate 418 to appear on the D8 input of flip-flops 417. AT C5 time, the positive-going transitionof +CLK causes the 0 to be stored in the eighth stage of flip-flops 417 and causes a 0 to appear on the Q8 output. That 0 from the Q8 output indicates that the -BUS OPER(3) signal is active. The INVERTER gate 512 inverts the -BUS OPER(3) signal to form the +BUS OPER(3) signal.

After C5 time, the +BUS OPER(3) signal is a logical 1 and forms one input to the upper AND portion of gate 418. The other input to the upper AND portion of gate 418 is the output from the AND gate 584 which, after C5 time, switches to a logical 1. Gate 418 holds the D8 input to eighth stage of the flip-flops 417 as a logical 0 as long as the gate 584 is satisfied, that is, as long as the +MEMORY BUSY OUT signal is being generated as a logical 1. In Figure 6, the -MEMORY BUSY signal is the inverted +MEMORY BUSY OUT signal of Figure 5 and they remain active between C5 and C13 time.In the event that at C5 time the -OP IN(3) signal on line 467 was a logical 0, the outputfrom gate 418 would remain as a logical 1.

This logical 1 would continue to be clocked into the eighth stage of flip-flops 417 on each positive-going transition of +CLK until a 0 again appeared for +OP IN(3).

At C5 time, both inputs to gate 584 are logical l's so that the output +MEMORY BUSY OUT in Figure 5 is a logical 1 and -MEMORY BUSY in Figures 3 and 6 is a logical 0. At C5 time, the output from inverter 512 goes to a logical 1. The 1 from inverter 512 enables gate 585 so that in Figure 5 +BUS BUSY OUT goes to a logical 0. In Figures 3 and 6, the -BUS BUSY signal after C5 time remains a 0, as a result of the logical 1 from +BUSY OUT signal from gate 585 in Figure 5, regardless of the operation of the busy signal from the requesting unit.Note that the logical 0 for -BUS BUSY between time C3 to C5 determined by a requesting unit, is passed to the requested unit after time C5 without any intervening time period.

At time C5, the -MEMORY BUSY signal switches from 1 to 0 as a result of the operation of gate 584 which switches +MEMORY BUSY OUT to a logical 1 causing -MEMORY BUSY to go to a logical 0.

After C5 time, gates 584 and 585 remain satisfied until the output from NAND gate 423 goes to a logical 0. The output from gate 423 goes to 0 whenever all its inputs are logical 1. After C5 time, the line 466 from decoder 212 to gates 427 and 428 returns to a logical 0 so that -START NEW STORAGE OP and -SET STORAGE OP PENDING both go to logical 1's. Accordingly at C7 time, Q1 and Q2 of flip-flops 431 are clocked to logical 1's. The third input to gate 423 is the Q5 output of the flip-flops 431.

The Q5 output is maintained as a logical 0 as long as a storage operation is pending or in progress. The status of the storage operations and the refresh operations are stored in the flip-flops 432. If a storage operation is pending, the Q3 output, +STORAGE OP PENDING, is a logical 1. If a storage operation is in progress, the Q4 output, +STORAGE OP IN PROGRESS, is a logical 1. If either Q3 or Q4 is a logical 1, the NOR gate 443 provides a logical 0 to the D5 input of the fifth stage of flip-flops 431. On the next positive-going transition of +CLK, the output from gate 443 is clocked into the flip-fiops 431 and appears on the Q5 output.As long as a storage operation is in progress or pending, Q5 remains a logical 0 forcing the output of gate 423 to a logical 1 and thereby holding gates 584 (-BUS BUSY) and 585 (-MEMORY BUSY) enabled.

The manner in which the third and fourth stages of flip-flops 432 are clocked to set or reset the status occurs as follows.

At C5 time when Q1 of flip-flops 431 goes to 0, that 0 causes the output of NOR gate 598 to go to 0 provided the storage card addressed by the address from -SY BUS(0-31) between C3 and C5 has the particular address and hence provided a logical 0 for -STORAGE CARD SELECTED appears as an input to Figure 5. In accordance with the present invention, a logical 0 will be provided for -STORAGE CARD SELECTED prior to the positive-going transition of -HOLD ADDRESS at C4 time, if one of the modules 670-0, 670-1 670-N contains the address on bus 37-1.Assuming that the address is found in one of the modules 670, INVERTER gate 549 inverts that logical 0 to a 1 which is stored in the address-match D-type flip-flop 505 in response to a positive-going transition from the output of AND gate 425 at C5 time. At C5 time, the 1 on the Q output of flip-flop 505 is inverted in gate 506 to provide another 0 input to the OR gate 598. Provided there is an address match and a new storage operation started, the output from OR gate 598 is a logical 0 thereby forcing the output from NAND gate 438 to a logical 1. The output from gate 438 is the +SET STG OP IN PROG signal which is connected to the J4 input of the fourth stage of flip-flops 432. The operation after C7 time continues in the manner described in the above crossreferenced application entitled DATA PROCESSING APPARATUS AND METHOD WITH ENCODED SYS TEM BUS.

ACKNOWLEDGE. The function of the acknowledge signal, -ACKNOWLEDGE, is to communicate to the requesting unit that the requested unit has stared the action which was requested. In the present example of Figure 6, the requested action was a fetch operation identified from the op code field decode.

In Figure 5 when the fetch operation was decoded to provide a logical 1 on the output line 466 from decoder 212, inverter gate 429 provided a logical 0 for -STORAGE BUS OP. At C5 time, that 0 is stored in the third stage of flip-flops 431 to provide a 0 on the Q3 output. That 0 from Q3 is inverted in INVERTER gate 510 as a 1 input to AND gate 586. The other input to gate 586 is from the Q output of flip-flop 505 which has a logical 1 output when a proper storage card address is recognized. In the example, of Figure 6, a proper address is recognized and a logical 1 output is clocked into the eighth stage of flip-flops 470 on the positive-going transistion of +CLK which occurs at C7 time.Accordingly, at C7 time a +ACK NOWLEDGE OUT signal from the Qa output of flip-flops 470 is a logical 1 in Figure 5 and which is inverted to form the -ACKNOWLEDGE signal in Figures 3 and 6.

Storage card selected. The -STORAGE CARD SELECTED signal is a signal received back from the memory unit 404 of Figure 3 whenever the address transmitted to the memory unit is a valid address for some module 670-0,670-1 670-N. As described in connection with Figures 1 and 2, each module receives the same address, but only one of the modules should return a logical 0 for the -STORAGE CARD SELECTED signal. The logical 0 signal in the example of Figure 6 is returned after C3 time during the period that the address on -SY BUS(O-31) is present.The -STORAGE CARD SELECTED signal is inverted in inverter 549 of Figure 5 which in turn connects as the D input to the flip-flop 505. Flip-flop 505 stores an address match signal clocked into the flip-flop bythe negative-going transitions of outputs from AND gate 425. Gate 425 will have a negativegoing output whenever a new storage operation is to start or a storage operation is set pending. The Q output of flip-flop 505 is inverted in inverter 506 as an input to OR gate 598. If no module in storage unit 35 has the address, inverter 506 will provide a logical 1 to the gate 598 thereby preventing the circuitiry of Figures 4 and 5 from commencing a storage operation for that storage unit.One or more additional storage units, like unit 25 of Figure 1, may be placed in parallel with unit 35 and connected to the system bus in the same manner as unit 35. One storage unit and the corresponding circuits of Figures 4 and Swill be valid and will therefore return a logical 0 for the -STORAGE CARD SELECTED signal for any given address placed on the -SY BUS(O-31) bus. In the event that the storage address is not recognized by any storage unit, AND gate 586 will prevent the operation from being acknowledged.

Hold address. The -HOLD ADDRESS signal is a signal which is transmitted to the memory unit 404 of Figure 3 whenever an address is supplied over the bus -SY BUS(0-31). The -HOLD ADDRESS signal is maintained active for as long as it is necessary for each module of memory unit 404 to hold that address. The address is held in each module in the address register 659. In Figure 5, the -HOLD ADDRESS signal is generated by the NAND gate 439 and is inverted in inverter 537. Gate 439 will provide a logical 1 output inverted to a logical 0 whenever it receives a 0 input. Normally, gate 439 oscillates between 1 and 0 levels as the clocking signal, +CLK +30, goes between 0 and 1. That clocking signal is delayed 30 nanoseconds after the +CLK signal.

Whenever a storage operation is pending, in progress, or is to be started new, or set pending, gate 439 will have a 0 input from the Q1, Q2 or Q5 outputs of flip-flops 431 holding the output to a 1 and inverrted in inverter 537 to a 0. In the example of Figure 6, the -HOLD ADDRESS signal stays low at a logical 0 from a C4 +30 time until a C13 +30 time. That period is essentially the same period that -MEMORY BUSY is a logical 0 between C5 time and C13 time plus the 30 nanoseconds while the pulse +CLK +30 remains a logical 0.

Rowaddressstrobe. The -ROW ADDRESS STROBE signal (-RAS) is a signal transmitted from the Figure 4 apparatus to the memory unit 404 of Figure 3 and is used for the internal operation of the memory. In Figure 4, the -ROW ADDRESS STROBE signal is inverted by NAND gate 463 and causes the -ROW ADDRESS STROBE line to go low whenever a -PENDING OP STARTED signal from the Q4 output of flip-flops 431 of Figure 5 is a logical 0 or the -STORAGE OP STARTED signal from the Q1 output of flip-flops 431 is a logical 0.

In the example of Figure 6, the -ROW ADDRESS STROBE goes negative at C5 time in response to the O on the Q1 output of flip-flops 431. In Figure 4, at the same time, the -START signal clears the storage cycle counter 450 and is inverted in inverter 534 for storage in the first stage of the flip-flops 455. At the same time, the output from AND gate 595 is a logical 1 so that gate 455 stores a 1 on its Q1 output at the next positive-going transition of -CLK which occurs at C6 time. NAND gate 593 therefore receives two logical 1 inputs so that its output is a logical 0. This logical 0 appears at about C6 time and continues to hold the output of NAND gate 463 as a logical 1 even after -STORAGE OP STARTED goes to a logical 1 at C7 time.The 0 output from NAND gate 593 is also loaded into the second stage of the flip-flops 455.

The output from the gate 593 is known as the -CAS TIMING signal which functions to hold the row address strobe and the column address strobe signals for the appropriate duration even after the initiating signals have ceased to be present.

Column address strobe. In Figure 4, the -COLUMN ADDRESS STROBE (-COL ADDR STROBE) signal is generated by NOR gate 464 and inverter 535 for transmission to and internal operation of memory 404.

The -CAS TIMING signal from gate 593 returns to a logical 1 after the AND gate 595 has a logical 0 output. Gate 595 will have a logical 0 output whenever a fetch is to be aborted by a 0 for the -PRESET 6 signal from gate 531 (inverting the output from gate 587) or one cycle after the -T5 signal is decoded from the decoder 454. The one-cycle delay for a -T4 logical 0 is provided by the second stage 470-2 in Figure 4 of flip-flop 470 of Figure 5. When the output from gate 595 goes to a 0, the outputfrom NAND gate 593 is forced to a 1. That 1 then disables NAND gate 463 so that the -ROW ADDRESS STROBE signal returns to a logical 1 as shown as C13 time in Figure 6.

In Figure 4, NOR gate 464 senses a 0 for the -CAS TIMING to provide a 0 after inversion by gate 535 for the -COLADDR STROBE signal except when a refresh operation is called for, that is a logical 1 for the +REFRESH signal. If a refresh operation is called for, then the column address strobe is inhibited. The -COLADDR STROBE signal returns to a logical 1 at C13 time in Figure 6 at the same time as the -ROW ADDRESS STROBE signal.

Gate data from storage. The -GATE DATA FROM STORAGE signal is always inactive low in Figure 6 since only a fetch operation is being described.

Write strobe. The -WRITE STROBE signal in Figure 6 is similarly not active since only a fetch operation is being described.

Refresh. The -REFRESH signal does not occur during the fetch operation between C3 time and C15 time of Figure 6. A typical refresh operation is described in detail in the above cross-referenced application entitled DATA PROCESSING APPARATUS AND METHOD WITH ENCODED SYSTEM.

Load data out. The +LOAD DATA OUT signal from Figure 4 connects to the latches 207-1 and 207-2 in Figure 5 to load the data transmitted from the memory unit 404 through the bidirectional drivers 406. The +LOAD DATA OUT signal is generated by an inverter gate 533 in Figure 4 which receives the Q6 output of the sixth stage of flip-flops 431. The D6 input to flip-flops 431 is the -T1 decoded output from the decoder 454 of Figure 10. The 0 for the -T1 signal is stored in the flip-flops 431 in Figure 11 at the next positive-going transition of +CLK which occurs at C9 time. The storage cycle counter 450 in Figure 10 is advanced to the next count (-T4 is active) in the sequence at C10 time so that the -T1 output at that time returns to a logical 1.That logical 1 is again loaded into the sixth stage of flip-flops 431 and appears on the Q6 output at C11 time. At C11 time, the +LOAD DATA OUT signal returns to a logical 0 as shown in Figure 6.

At the time when -T4 is decoded as a logical 0, the flip-flop 504 in Figure 5 is loaded to provide a 0 on its Q output to form the -GATE DATA OUT(0-31) signal which connects to multiplexer 410 in Figure 3 at the negative-going transition of -CLK which occurs in Figure Sat C11 time. Therefore the data from the latch 207-1 is selected by multiplexer 410 for place ment on the -SY BUS(O-3l) between C11 and C13 times of Figure 6. At C12 time, the -T4 decoded output switches back to a logical 1. That logical 1 is effective to load a logical 1 on the Q output of flip-flop 504 on the next negative-going transition of -CLK which occurs at C13 time in Figure 6. Between C13 and C15 times, the multiplexer 410 in Figure 3 functions to select the data bits 32 through 63 from the latch 207-2 for placement on the bus -SY BUS(0-31).

At this time, the fetch operation which commenced at C3 time has been completed, that is, it is complete at C1 5 time. Note that the -BUS BUSY signal was returned to an inactive logical 1 one cycle, earlier, at C13 time, then the completion at C15 time.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that those changes in form and details may be made therein without departing from the spirit and the scope of the invention.

Claims (14)

1. In a data processing system having a storage unit with memory locations addressable by memory addresses where said memory addresses are formed of a high-order address and a low-order address, the memory apparatus comprising, address bus means for carrying to said storage unit memory addresses each including a high-order address and a low-order address, data bus means for carrying data to and from said storage unit, a plurality of memory modules, each of said modules including, module address means connected to said address bus for receiving said high-order address and said low order address, module identifier means for providing a module identifier address, comparator means for comparing said module identifier address with said high-order address to provide an identifier signal when said addresses match, memory means having a plurality of said memory locations, control means for enabling said memory means, in response to said identifier signal, to read or write data at locations determined by said low-order address, module bus means for connecting data between said memory means and said data bus.

2. The apparatus of Claim 1 wherein a first one of said modules has said high-order address with "H" bits and said low-order address with "L" bits and wherein a second one of said modules has said high-order bits different then "H" and said low-order bits different then "L".

3. The apparatus of Claim 1 wherein each of said modules has means for selecting the number "H" of bits in said high-order address and the number "L" of bits in said low-order address.

4. The apparatus of Claim 1 wherein each of said modules includes register means for storing identifier signal and wherein said memory apparatus includes means connected to each of said register means to sense an identifier signal for any of said modules and thereby indicate the presence of said memory address within said storage unit.

5. The apparatus of Claim 4 wherein said memory apparatus includes hold address means connected to each of said register means and operative, when a new memory address is carried on said address bus means, to store said identifier signal.

6. In a data processing system having a plurality of storage units with memory locations addressable by memory addresses where said memory addresses are formed of a high-order address and a low-order address, each of said storage units including memory apparatus comprising, address bus means for carrying to said storage unit memory addresses each including a high-order address and a low-order address, data bus means for carrying data to and from said storage unit, a plurality of memory modules, each of said modules including, module address means connected to said address bus for receiving said high-order address and said low order address, module identifier means for providing a module identifier address, comparator means for comparing said module identifier address with said high-order address to provide an identifier signal when said addresses match, memory means having a plurality of said memory locations, control means for enabling said memory means, in response to said identifier signal, to read or write data at locations determined by said low-order address, module bus means for connecting data between said memory means and said data bus.

7. The apparatus of Claim 6 wherein a first one of said modules in each of said storage units has said high-order address with "H" bits and said low-order address with "L" bits and wherein a second one of said modules in each of said storage units has said high-order bits different then "H" and said low-order bits different then "L".

8. The apparatus of Claim 6 wherein each of said modules has means for selecting the number "H" of bits in said high-order address and the number "L" of bits in said low-order address.

9. The apparatus of Claim 6 wherein each of said modules in one of said storage units includes register means for storing said identifier signal and wherein said memory apparatus in said one of said storage units includes means connected to each of said register means to sense an identifier signal for any of said modules and thereby indicate the presence of said memory address within said one of said storage units.

10. The apparatus of Claim 9 wherein said memory apparatus for said one of said storage units includes hold address means connected to each of said register means and operative, when a new memory address is carried on said address bus means, to store said identifier signal.

11. A data processing system including a plurality of units, including a system bus for connecting said units, and where at least one of said units is a storage unit with memory locations addressable by memory addresses where said memory addresses are formed of a high-order address and a low-order address, the memory apparatus comprising, address bus means connected to said system bus for carrying to said storage unit memory addresses each including a high-order address and a low-order address, data bus means connected by interface means to said system bus for carrying data to and from said storage unit, a plurality of memory modules, each of said modules including, module address means connected to said address bus for receiving said high-order address and said low order address, module identifier means for providing a module identifier address, comparator means for comparing said module identifier address with said high-order address to provide an identifier signal when said addresses match, memory means having a plurality of said memory locations, control means for enabling said memory means, in response to said identifier signal, to read or write data at locations determined by said low-order address, module bus means for connecting data between said memory means and said data bus.

12. The data processing system of Claim 11 wherein, said system bus has operation code field means for transmitting an encoded system operation code and has system information field means for transmitting associated system information including said memory addresses and said data where the associated system information has a function determined by the system operation code, said plurality of units includes one or more first units connected to said system bus, said first units including means for generating system operation codes specifying said memory addresses and said data for transmission by the operation code field of said system bus and including means for generating associated system information including said memory addresses and said data for transmission by the information field of said system bus, said plurality of units includes one or more second units connected to said system bus, said second units including means for accepting a predetermined system operation code and associated system information from said system bus and including means for decoding the predetermined system operation code to perform a function with the associated system information, and, access control means for controlling the access of said units to said system bus.

13. The data processing system of Claim 12 wherein one of said second units is said storage unit connected to said system bus for transferring information between said storage unit and one of said first units.

14. The system of Claim 12 wherein said system bus includes means for transmitting a system clock signal to each of said units and wherein each of said units includes a system bus interface, said interface including means for latching information from said bus under control of said system bus clock signal and including means for gating information onto said system bus in synchronism with said system clock signal.