DE3808193A1 - Computer system with printed circuit boards for extension slots - Google Patents

Abstract

A personal computer system has a main circuit board with a central unit (1) and extension slots (29 - 34), each of which can take one printed circuit board (50). The main circuit board has a memory (2), a 32-bit address bus (10) and an input-output circuit (7). Each slot is connected to the 32-bit address bus (10), which is in the form of a NuBus bus, and has special means of identification control, which provide the slot with an identification number (S9) in the computer system. The computer system reserves 256 megabytes of memory space, from position SX0000000 to position SXFFFFFFF, as memory on a card with special number SX in a slot. The card contains decoders, which are connected to the slot to receive the identification number, and have the effect of reserving 256 megabytes of memory space for the card in the slot. <IMAGE>

Description

The invention relates generally to computer systems Expansion slots on a mother card (main circuit card) and in particular on personal computers with such Slots and printed circuit boards included in such Slots can be inserted and connected to a bus, wherein part of the address memory space in the computer for the Schlit ze is reserved.

Computer systems with expansion slots are capable of Technology known. For example, the Apple IIe is a be Known personal computer that out with expansion slots is equipped; Storage space is for the slots in the computer reserved. However, the memory of a card in this Computer not accessed by first entering the address there, but by choosing a special pen in the Slot (along with the address), using the special pen the card in the slot says that from the microprocessor called address somewhere in the for this peripheral card reserved memory. In addition, the one for cards in memory space reserved for these systems is relatively small (e.g. 16 bytes or 256 bytes). This means that the address itself is not usually used alone to indicate when a card address space is addressed. Different pressure Writings are known in the prior art, which the genes relate to the real nature of such computer systems. These include for example: The Apple II Reference Manual, Apple Com puter 1981; From Chips to Systems: An Introduction to Micro processors, Rodnay Zaks, Sybex, Inc., 1981; An Introduction to Microcomputers, Adam Osborne and Associates, 1975; and The Apple II Circuit Description, Winston Gayler, published by Howard, W. Sams & Co., Inc. (1983).

The present invention relates in particular to Com computer systems with system buses, which are essentially NuBus Specifications will follow. These specifications describe the Protocols (e.g. logical, electrical and physical stan  dards) and general standards of a synchronous (10 Mhz), Multiplex multimaster buses, the general one decision mechanism provides. NuBus was created at MIT (Massachusetts Institute of Technology). It was subsequently revised and exists in certain Texas Instruments publications, Inc. (including Texas Instruments Publication No. 2242825-0001 and Texas Instruments Publication No. 2537171-0001). Recently a committee of the institute of Electrical and Electronic Engineers (IEEE) specifications proposed for a system bus as IEEE standard, which in is essentially a NuBus bus, although it is opposite the one from Texas Instrument published specifications modified has been. The proposed IEEE bus becomes the IEEE 1196 bus designated. A copy of the proposed specification for the IEEE 1196 bus (draft 2.0) becomes this application Reference assigned by the specialist. The IEEE 1196 bus is essentially a NuBus bus according to the original specification in the Texas Instruments publications.

In a NuBus system, there are 4 gigabytes of physical memory address space because there is a 32-bit address bus that is coupled to a CPU, which CPU 2 can generate ³² different addresses. In its simplest embodiment, a computer using the NuBus architecture is essentially a main circuit card with slots into which cards (sometimes referred to as modules) are inserted that have microprocessors, memory and other general microprocessor-related circuitry. In fact, each card can itself be a microcomputer that uses NuBus to communicate with other cards in other slots that are also connected to NuBus. For example, a NuBus system can have a card with a CPU (central processing unit) microprocessor, a memory management unit, a memory in the form of a random access memory (RAM) and a read-only memory (ROM), and a card-specific bus that matches the card located microprocessor allows to read the ROM on the card and to read in or out of the RAM on the card. In addition, an input and output (IO) circuit may be provided on the card that allows the card to connect to parts of the rest of the system, including peripheral devices, such as disk drives, printers, video systems, and other peripheral devices, through card-internal connectors communicate. The card has a typical design with an edge with electrical connections in the form of pins, via which electrical connections with cooperating connections are made in a slot. Such a card equipped with a microprocessor is suitable for controlling the NuBus bus by executing certain signals to initiate a NuBus transaction, whereby information about the NuBus is transmitted and received on the main circuit card. Therefore, this card could write information to a memory located on other cards via the NuBus (one transaction) and read this information via the NuBus (another transaction). In the NuBus system, memory space is reserved for each of the slots. In NuBus system, there may be up to 16 slots, which storage space is in the top ¹ / _16th of the total 4-gigabyte address space NuBus zugeord net. This upper _^sixteenth means 256 megabytes of storage space and is divided into 16 regions of 16 megabytes, the abge forms will have 16 possible NuBus cards, slots, and on the basis of a slot identification number, which generates a certain number at each slit and a card in the slot gives the opportunity to "read" the particular identification number to determine the slot number of the slot in which the card is inserted. Reference is generally made to pages 30-32 of the proposed specification of the IEEE 1196 bus. Each card receives a "slot space" of 16 megabytes. In the conventional NuBus system, a "slot space" of a card is reserved by a card's own facility which maps the specific number (expressed as a hexadecimal number) of the slot (where the card is located) to the second highest rated hexadecimal number (second MSHD ) one adapts the address appearing on the NuBus bus if the highest valued hexadecimal digit (MSHD) is $ F. Therefore, the device determines when MSHD = $ F and then determines whether the slot number (slot identification number) matches the second highest hexadecimal digit. If there is a match, the device allows the card to be addressed. Of course, the actual comparison is done by the map in the binary system; however, for purposes of illustration, it is easier to assume that the comparison would be made in the hexadecimal system.

This NuBus system provides considerable flexibility because the vast majority of the memory address space is unre remains served. In addition, the apparently large (16-Me gabytes-) spaces reserved for the slots (the Slot spaces) considerable data storage ("data" includes computer programs in the present use). Each however, too much flexibility increases mismatches between cards that are on the same motherboard be used. This means that the flexibility is possible makes a map that covers most of the remaining address space reserved in the NuBus system, however would compete with another card that Developed using part of the same storage space has been. Of course, switches and patch cords can be used to configure the system such that Memory space overlaps can be avoided; such solution conditions, however, are complex and disruptive in many ways, especially since they irritate newcomers who have a computer system  pull that the user simply inserting the card into a slot and thoughtless further use light.

The invention solves these problems by automatically assigning ¹ / _16th of the entire memory address space to each slot in the NuBus system. It is therefore an object of the invention to provide a system which is self-configured and is nevertheless flexible, but because of this flexibility does not punish or burden the user. In particular, the invention provides a main circuit board (motherboard) with slots which enables greater automatic computing power due to the increased storage space for each card. The invention also provides printed circuit cards (modules) which automatically configure for their storage space and have reserved an enlarged storage space for each of the cards.

The invention comprises a computer system with expansion slots, which are coupled to a NuBus system and have increased storage space available and reserved for the memory on cards (modules) in the expansion slots, the reservation of the increased memory using special identification line means occurs, which deliver a special number via a special signal, which identifies the slot number for each card in the slot. In addition, the invention provides a card with a decoding device which is suitable for receiving the special signals supplied via the special identification line. A decoding device compares the special number supplied by the special signal with an address appearing on NuBus. The comparison results in 256 megabytes of memory space being reserved for the card in a slot, the memory space being in the range from $ X 000 0000 to $ XFFF FFFF and the slot number being X.

The decoder compares the special number with the highest valued hexadecimal digit on the NuBus bus address to determine if the special number in the hexadecimal system equal to the highest rated hexadecimal digit in the address. If the Decoder determines the match, it gives a Spei on the card for addressing based on the address appearing on the NuBus bus. The comparison takes place binary instead of course; for the purposes of the explained However, it is easier to do the comparison process in this way as if it were in the hexadecimal system.

In the following the invention based on one in the drawing schematically illustrated embodiment. In the drawing shows:

Fig. 1 is a block diagram of a general computer system according to a preferred Ausführungsbei game of the invention wherein slots 6 are coupled to a NuBus bus;

Fig. 2 is an illustration of the physical address memory space of an embodiment of the invention;

Fig. 3 is a physical address memory space map showing the memory space allocation for a preferred embodiment of the invention;

Figure 4 is a printed circuit card according to the inven tion, which is intended for use in connection with a motherboard or card according to the invention.

Figure 5 is a block diagram of the NuBus interface with a microprocessor on the main circuit board.

Figure 6 is a block diagram showing various NuBus clocks for use with the NuBus bus.

Fig. 7 th, the phase relationship of the various NuBus-Tak;

Fig. 8 is a block diagram of the interface between the mother card processor (CPU 1) and the NuBus Kar th in NuBus slots;

Fig. 9 is a block diagram showing the interface of the NuBus to the mother card processor bus;

Figure 10 shows an address memory space map seen from a card in a NuBus slot, the card accessing the ROM portion of the memory by addressing the top portion of the small space for a zero slot;

Figure 11 is a perspective view of the main control processing board (mother board) of the invention designed according to the computer system.

Fig. 12 is a schematic circuit diagram of an embodiment example of a decoding device used on a card formed according to the invention;

FIG. 13 is a block diagram of a computer system according to the invention; and

Fig. 14 is a printed circuit card according to the inven tion for use in the main circuit card according to the invention.

Numerous details are given in the following description give e.g. B. circuits, block diagrams, memory locations, Logic values or, in order to make the invention easier to understand chen. However, it will be apparent to those skilled in the art that the invention can be realized without these special details. In other cases are known components and coaster systems me not described in detail to the present inven not burdened with unnecessary details.

Fig. 1 shows the general structure of a computer system according to the invention. The system has a central processing unit 1 (CPU 1 ), which is usually designed as a microprocessor and is coupled to a memory 2 , from and into which the CPU 1 can read and write data. The CPU 1 provides addresses of memory locations via a processor 5, which serves as an address bus and transfers addresses from the CPU 1 to the memory 2 . Data (which include computer program instructions) from the addressed memory locations are transferred from memory 2 to a processor bus 6 , which serves as a bidirectional data bus. The CPU 1 can thereby write into the memory 2 by first creating an address via the processor bus 5 , which addresses memory locations in the memory 2 corresponding to the address signals via the processor bus 5 , and then by transferring data via the processor bus 6 to the memory 2 writes in the latter. As is known, certain signals via the CPU 1 , which are transmitted via the processor bus 5 , indicate whether the CPU 1 is writing to the memory 2 or reading from it.

The processor bus 5 is a 32-bit address bus and therefore has 32 address lines which supply the address signals. The processor bus 5 also transmits control signals (e.g., R / W) (read / write) and chip select signals indicating whether the CPU is reading (from memory) or writing (into memory) and other associated control signals, including control signals for the microprocessor currently used and timing signals (e.g. column address strobe signals and row address strobe signals), as is known in the art and therefore not explained in detail here are needed. The processor 7 contains a 32-bit data bus (with 32 data lines for transmitting the data signals) and associated control signals for the particular microprocessor used, which are typically associated with the data buses, as is known in the art (e.g. Write activation signals, etc.). In the embodiment according to the invention, the CPU 1 has an address generation device for generating 2 ³² different addresses from location $ 0000 0000 to location $ FFFF FFFF (the $ denotes the hexadecimal notation); this address generation device is coupled in a typical embodiment to the processor bus 5 and is part of the CPU 1 , such as the microprocessors 68020 (Motorola) and 80386 (Intel).

The computer system also has input and output circuits which are known to serve the computer as an interface for receiving data from and for transmitting data to peripheral units. The details of this circuit are known. The input / output (I / O) circuit 7 is connected to the CPU 1 and the memory 2 via a connection bus 13 and the processor bus 6 and the processor bus 3 . The I / O circuit 7 can be used to access peripheral devices, e.g. B. disk drives, printers, modems, video displays and other peripheral devices used in connection with the computer system can be used. As shown in Fig. 1, a disc drive 8 by a processing between the I / O scarf 7 and the disk drive 8 is arranged interconnect O circuit coupled to the I /. The I / O circuit is coupled to the memory 2 via the processor bus 6 in order to supply data to the memory and to obtain it from the memory and the CPU 1 ; the bus 3 enables the CPU to address the peripheral units connected to the I / O circuit 7 and the I / O circuit 7 to address the memory 2 . The I / O circuit 7 is also coupled to the CPU in order to be able to receive data and control signals from the CPU 1 . Therefore, the peripheral units, e.g. B. the disk drive, data (including programs) with the CPU 1 and the memory 2 ; they can also exchange data with any data and the slots coupled to the NuBus 10 , such as slot 29, which slot has a specific number, $ 9, in the computer system of FIG. 1.

In a typical transaction, CPU 1 provides an address via bus 5 . The memory 2 , which is connected to the bus 5 , receives the addresses and supplies a value via the bus 6 on the basis of the space addressed on the bus 5 in accordance with the address. The data from the memory 2 are transferred to the CPU 1 via the processor bus 6 . The memory 2 typically contains a RAM and can also contain a ROM (read only memory). The processor bus 6 is coupled to the NuBus 10 via the interface 9 and connecting buses 11 and 12 .

The computer system shown in Fig. 1 has 6 "expansion" slots, which are designed to receive printed circuit boards and electrical connection to the circuit on the cards, for. B. cards 50 and 50 a in Figs. 4 and 14 respectively. This system contains slots 29, 30, 31, 32, 33 and 34, each of which is coupled to another Sy stembus, NuBus 10, on the motherboard or card. Accordingly, slot 29 is coupled to NuBus 10 via connection bus 19 . Each of the slots has cooperating connections, each of which is electrically coupled to a special signal line of the NuBus bus 10 via the connecting buses. Therefore, each of the slots 29, 30, 31, 32, 33 and 34 contains a set of cooperating connectors that provide electrical connection to the NuBus bus 10 . A card according to the invention has connections 51 , which are suitable for establishing electrical connections with corresponding cooperating connections in the slot, in order to enable circuit components on the card to receive all signals of the NuBus bus 10 .

A card in one of the slots 29, 30, 31, 32, 33 or 34 can connect to the memory 2 via the NuBus interface 9 , and the CPU 1 can connect to any memory on the card via the NuBus interface 9 communicate; the latter is described below. For example, the NuBus interface receives 9 addresses for the memory on a card in the slot from the CPU 1 via the bus 25 and supplies these addresses via the connection bus 11 to the NuBus 10; The interface 9 is used for the assignment and synchronization of the processor buses 5 (over 25 ) and 6 between the CPU 1 and any CPU on a card (which is a read operation from the NuBus bus or a write operation from the NuBus bus to the memory on a card) can look for taxes). Similarly, the interface 9 receives addresses for the memory 2 from a CPU on a card ("NuBus device") via NuBus 10 and the connection bus 11; After synchronization to the processor buses and determination that the NuBus device (which generates the address) can take over control of the processor buses (by applying address signals via bus 25 to the processor address bus 5 ), the interface 9 delivers the address signals to the bus 25 connected to the memory 2. The memory 2 responds with data from the addressed memory location. These data are given on the bus 6 coupled to the interface 9 and transmitted via the NuBus 10 to the NuBus device.

The computer system shown in Fig. 1 uses the NuBus bus as an expansion bus for a computer system on a main circuit board, the CPU 1 processor buses on the main circuit board need not be NuBus buses. The slots connected to the NuBus 10 therefore offer the option of expanding the system, for example to include additional storage capacity or an additional processor card. However, it is possible to use the invention in a NuBus architecture in which there is no CPU on a main circuit card and no memory on this card. Such a system is shown in Fig. 13 and is described below.

FIG. 13 shows a general example of the invention for a computer system with a NuBus bus 120 on a main circuit board, which each has slots coupled to the NuBus bus 120 . The main circuit board of such a system, as shown schematically in FIG. 13, can be the NuBus bus 120 and 15 with 130, 131 . . . Have 144 designated slots. Each of the slots is coupled to NuBus bus 120 by a connection bus; accordingly slot 130 is coupled to the NuBus bus 120 through connection bus 150 , which normally contains all lines of the NuBus bus 120 and additional four lines which serve as special identification line means. These four lines typically carry binary values, which together can indicate any number from 0 to 15. Each of the slots receives a special identification line means which applies a different number to each of the slots. That is, a special identification line means as part of the connection bus 150 carries a special signal equal to zero. Slot 144 (slot $ E ) has special identification line means as part of connection bus 164 which provides a value (a special signal) = $ E. It can be seen that there is no sixteenth slot since the NuBus standard uses the top 256 megabytes (shown as area 40 in FIG. 2) for the small slot spaces (16 megabytes each) associated with slots 0-15 . This can be seen more clearly in FIG. 2, which shows the physical address memory space of a system, e.g. B. desje nigen according to FIG. 13. Each of the slots $ 0 to $ E has a "super space" of 256 megabytes: For example, slot 0 has a super space of 256 megabytes that was reserved for it from the memory locations $ 0000 0000 to $ 0 FFF FFFF . This space is generally designated by reference number 41 in FIG. 2. This system shown in Figures 13 and 2 includes a slot $ 0 with memory space reserved for that slot; however, since many microprocessors favor storage in area 41 (slot $ 0 superspace), a typical application of the present invention (e.g., Fig. 13) may not have slot $ 0 for convenience, and no reservation of memory 41 for any special slot is made. Therefore any cards in the remaining slots (e.g. in slots $ 1 to $ E ) can use the memory in area 41 . Any number of slots smaller than 15 can of course be implemented in the invention. As required by the NuBus standards, each of the slots $ 0 to $ E has a reserved space of 16 megabytes in the 40 -megabyte 256-megabyte range; this range extends from space $ F 000 0000 to space $ FFFF FFFF. Identification signals, such as the four special identification lines, are used to assign the "small spaces" in area 40 to each of the cards. Each of the small spaces in area 40 is also referred to as a slot space in the NuBus standard. Addresses of the form $ FSiXX XXXX denote address space that belongs to the slot space of the card in slot Si . Reference is made to pages 30-31 of the IEEE 1196 specification, draft 2.0, to which reference is made here.

FIG. 2 illustrates the general physical address memory space of the system generally shown in FIG. 13. The main circuit board with the NuBus 120 contains neither a CPU nor a memory. The system clock signals 170 on the main circuit board provide the NuBus signals and are coupled to the NuBus 120 via lines 175 ( FIG. 13). The supply circuit for the NuBus signals is not shown, but is understandable to a person skilled in the art. It is also clear that the main circuit board of the system in Fig. 13 should contain other NuBus auxiliary circuits which are not arranged on the cards, for example the NuBus timeout circuits.

The computer system shown in Fig. 13 typically includes two printed circuit cards, one in one slot and the other (a second card) in another slot. For purposes of illustration, assume that the first card is inserted into slot $ 0 (ie slot 130 ) and the second card is inserted into slot $ 1 (ie slot 131 ). The cards are shown generally in FIGS. 4 and 14. They contain a printed circuit card 50 or 50 a and connections 51, which are coupled to various components and signal lines on the card 50 or the card 50 a . The connections 51 are on a part of a printed plate which projects into a receptacle in the slots, which contain cooperating connections for making electrical connections with corresponding connections on the card. The physical standards of the connections are specified by the NuBus standard. The cooperating connections in the slots are coupled to various lines and components on the main circuit board; for example, many of the cooperating connections in the slots are electrically coupled to the NuBus bus signal lines. These interacting connections enable the components on the card to receive various signals present on the NuBus bus 120 and that a card in one slot with another card in another slot through NuBus 120 via the connecting buses, e.g. B. ren the buses 115 and 151 traffic.

In the example of FIG. 13, the first card 50 (which is to be arranged in slot $ 0) has a CPU, e.g. B. CPU 61 in Fig. 4, and a memory, for. B. RAM 62 and ROM 62 , which are switched together via a card bus 65 on the first card 50 . The CPU 61 and the memory 62 are coupled via the connections 51 on the card 50 to the system bus, which is the NuBus 120 . The second card 50 a ( Fig. 14) in slot $ 1 has a memory 62 ( Fig. 14), e.g. B. a RAM, but has no CPU. Such a card is called an auxiliary card and cannot take control of bus 120 . The second card typically has a card bus 65 that contains most (if not all) of the signals on NuBus 120 . Some of the address (and data) lines of the NuBus 120 (which are referred to as AD (31 ... 0) in the IEEE 1196 specification, draft 2.0, because the addresses and data are multiplexed over the same lines) are applied to the decoder 60 . Bus 66 in Fig. 4 usually carries the full NuBus address and data signals and control signals as well as supply signals. In the present description, the 32 address lines of NuBus (which also serve as the 32 data lines on NuBus) are referred to as A31 to A0, although they are the NuBus signals AD (31 ... 0). Essentially, the decoding device 60 of the card 50 a enables addressing of the memory 62 on the second card 50 a if the addresses on the NuBus 120 are in the reserved address space of the second card, which in this case is from space $ 1000 0000 to space $ 1 FFF FFFF is addressed. When the addresses are in the reserved memory space, the decoder 60 activates the chip selection (CS) lines (which are coupled to the line 64 from the decoder 60 ) of the memory 62 on the card 50 a, whereby the various RAM and ROM chips on this card are indicated that they are addressed, whereby the memory 62 on the card 50 a in slot $ 1 is addressed. Therefore, the memory on the second card receives 50 a addresses from the system bus when the decoding device by the chip selection pins activates the memory chips.

Therefore, the CPU on the first card 50 delivers $ 0 in the slot. which has an address generator for generating 2 ³² different addresses for memory addressing, via the connections of the card in slot $ 0 on NuBus 120 of an address. Parts of this address appear in the decoder 60 on the second card 50 a. If this address is in the range $ 1000 0000 to $ 1 FFF FFFF , the memory on the second card responds and supplies 120 data on NuBus during a suitable time cycle.

The decoder 60 on the second card in slot $ 1 of FIG. 13 compares the particular number of slot $ 1, which is $ 1, with the highest hexadecimal number of the address appearing on the system bus (NuBus 120 ) to determine if the particular number is in the hexadecimal system is the highest hexadecimal digit of the address. If this occurs, the decoder activates the second memory to be addressed in order to transfer data to the system bus. Therefore, the 256 megabyte "super space" for the second card in slot $ 1 is reversed. As will be explained further below, the decoder also performs the function of reserving the 16 megabyte storage space required in the specifications of the NuBus systems. It will be appreciated that slot $ 1 of FIG. 13 is coupled to a particular identification line means which provides a particular signal to the slot for identifying a particular number of that slot. This applies to each of the other slots in Fig. 13 (e.g. slot 144 has a particular signal of $ E which is the particular number of that slot). Typically, a specific identification line contains 4 conductors which carry binary values. In slot $ 1, only one of the four lines carries binary value 1, while all others carry binary value 0, with 1 in the lowest binary digit. Therefore, the particular identification line means provides the particular signal 1 to slot $ 1, and this signal identifies that slot as having a particular number $ 1. It will be appreciated that other means of identification may be provided for a particular number, for example the delivery of an identification number which, by arithmetic conversion, creates the special number of the slot. Alternatively, a conductor with multi-level logic can be provided as a specific identification line means. A preferred embodiment of the invention with six slots is described below with reference to FIGS. 1, 3, 11 and 12. Fig. 11 shows a 14 (also referred to as mother board or card) per-perspective view of a main circuit board that includes a CPU 1, a memory 2 with a read-only memory (ROM), an I / O circuit 36 and six slots with the reference numeral 29 to 34 has. The motherboard 14 also has connection means for establishing a connection with a keyboard. As with all other PC systems, the motherboard 14 also contains various other circuits, e.g. B. power supplies, lat ches and buffers, drivers and video circuits, Taktschal lines and other components, as they are typically PC-Sy systems associated with known design. Each of the slots 29, 30, 31, 32, 33 and 34 has cooperating connectors which make electrical connections to connectors 41 on a card inserted into the slot. Each of the slots 29-34 receives practically all NuBus signals of the NuBus 10 according to the NuBus standard ( Fig. 1). The slots receive the NuBus signals via connecting buses 19, 20, 21, 22, 23 and 24 ( Fig. 1). These connections are common to each of the slots except for the particular identification line means which identifies each of the slots with the particular number associated with the slot.

In this particular embodiment, slot 29 is assigned a specific number $ 9 by four binary value leading conductors, which is shown in the table below. These four conductors are part of the connecting bus 19, although they do not have to be physically present over the entire length of the lines in the NuBus 10 . Since they can be locally located in the immediate vicinity of slot $ 9. This applies accordingly to slots 30, 31, 32, 33 and 34. The geographical address shown in Table 1 is of course the special number of each of the slots.

Table 1

NuBus slot numbers for the Figure 1 system

Each of the lines in the particular identification line means for each of the slots is coupled to a circuit which attempts to raise the lines to the +5 V operating voltage signal. These circuits typically include a boost resistor according to NuBus standards on each of the particular identification lines, and this resistance boosts the open signals to practically +5 V while the ground signals remain substantially at ground potential. In the circuit shown in FIG. 12, which will be described below, it is assumed that the open signals are already raised (before being applied to the decoder 60 ) to the operating voltage potential of +5 V and the NuBus signals (including the GA3... GA0 signals and address signals (A31... A0) have been logically inverted by an inverter. In addition, each of the NuBus signals on NuBus bus 10 must be logically inverted (via one on the cards inverter) before it is connected to the circuit on the NuBus cards (e.g. cards 50 and 50 a ); in a similar way, signals from the cards on NuBus bus 10 must be logically inverted (via an inverter). In a typical embodiment, these inverters are integrated in the input and output buffers on the cards, on the interface 9, which switches the interface between NuBus bus 10 and the motherboard circuit (ie CPU 1 , memory 2 , I / O circuit 7, the various buses s 5, 6, 25, etc. forms) are inverted to the NuBus bus 10 and current signals from the NuBus bus 10 signals coming. For example, the GA3 NuBus signal (GND) applied to the slots is inverted to a logic one ("1") on the card and then applied to the circuitry in decoder 60 ( Fig. 12). These inversions are known in the art. If the CPU 1 and the circuit and buses assigned to it (eg buses 5, 6, 25 ) use the NuBus system, standards and signals, no inversion at the interface 9 is required.

It can be seen in this embodiment (shown in Figures 1, 11 and 3) that slot 30 has the particular number $ A; Slot 31 has the particular number $ B and slot 32 has the particular number $ C in the computer system; the specific number for slot 33 is 01.01.80E. 34 has the specific number $ E. In the specification for the NuBus proposed by IEEE, as specified in the IEEE 1196 bus specification, the specific identification line means are referred to as card slot identification and are identified by the symbol "ID (3... 0 ) ", which represents the geographical addresses GA3, GA2, GA1 and GA0. As stated in this specification of the IEEE on page 6, these four lines are not bus-linked but binary coded in each position to indicate the card position in the computer.

In accordance with the present invention, a computer system as generally shown in FIG. 1 results in a physical address memory space as shown in FIG. 3, each of the six slots having a "super space" with 256 megabytes of reserved memory space. Therefore, for example, slot $ 9 has a reserved super space that starts at $ 9000 0000 and ends at $ 9 FFF FFFF . In addition, slot $ 9 may also have reserved a small space ("slot space") according to the NuBus specification; According to these specifications, slot $ 9 has a small space reserved for it, starting at space $ F 900 0000 and ending at space $ F 9 FF FFFF . As shown in FIG. 3, the 256 megabyte area 42 contains the small spaces for the various slots. There is an unreserved NuBus memory address space 43 that can be used by additional expansion slots that can be added to a system built according to the invention. The lowest 256 megabyte memory space, designated 45, is the local address space for CPU 1 , which is assigned the special number $ 0 as if it were $ 0 on a card in the slot. The CPU 1 can be designed so that it "occupies" additional slots, ie it can be assigned to specific numbers $ 1, 2 and 3 and therefore have reserved the entire area 44 as in the specific example according to FIG. 3; as a result, the motherboard becomes a four-slot card ($ 0, 1, 2, and 3). If the designer wants to completely isolate the superspace slot $ 0 for use by CPU 1 (ie prevent NuBus access to this superspace $ 0), the NuBus interface 9 is designed to prevent such access, but access to data in super space $ 0 by alias that is replicated in super space $ 1 or $ 2 or $ 3. Therefore, NuBus addresses on NuBus 10 in super space $ 0 can be decoded to the same corresponding place (ie $ 0 XXX XXXX to $ 1 XXX XXXX in super space $ 1. In such a situation, NuBus cards (in the current physical slots $ 9 to $ E ) access slot $ 0 super space by addressing super spaces $ 1, 2 or 3, which can be designed to contain aliases of the data stored in super space $ 0. The address space $ 0000 0000 to $ 1000 0000) is also the local address space space for cards that operate completely and without a NuBus card; that is, a card like that of FIG. 4 with a CPU can address its local RAM locally on the card in this same address space 45 , provided that the CPU does not initiate a NuBus transaction. Such an arrangement for purely local transactions on the card is implemented in a known manner by address decoders on the card.

The particular exemplary embodiment shown in FIG. 1 also reserves additional memory space for the I / O circuit and the read-only memory (ROM), which is part of the memory 2 in FIG. 3. In particular, address memory space is reserved in the range of $ 4,000,000 to space $ 4 FFF FFFF . In addition, memory address space is reserved for I / O operations and circuits in the range from space $ 5000 0000 to space $ 5 FFF FFFF . Fig. 3 shows an embodiment of the invention, wherein the I / O, and ROM memory space in the range of $ 4000 to $ 0000 5 FFF FFFF is provided. Therefore, access to ROM or I / O information from CPU 1 or from a second CPU 61 can be gained by addressing these locations in the range of $ 4000 0000 to $ 5 FFF FFFF . Another embodiment of the invention is shown in FIG. 10, where the motherboard I / O and ROM storage space with respect to the NuBus cards is arranged from $ F 000 0000 to $ F 0 FF FFFF . In this example, the memory space accessible by the NuBus cards (in NuBus slots) of the motherboard I / O information and the system ROM (on the motherboard) is limited to 16 MB (megabytes) while the CPU 1 is still can access the range $ 4000 0000 to $ 5 FFF FFFF . However, many systems can be constructed in which this limited 16 MB space is sufficient for ROM and I / O use.

Therefore, in the case of a NuBus card, the ROM which forms part of memory 2 on the mother card can be accessed by creating addresses in the range $ F 000 0000 to $ F 0 FF FFFF on the NuBus bus, thereby providing access this ROM is effected. This is implemented in a known manner with the interface 9 , which addresses NuBus bus addresses in the $ F 000 0000 to $ F 0 FF FFFFF area in the ROM and I / O area of the motherboard ($ 4000 0000 to $ 5 FFF FFFF ) decoded. The CPU 1 need not be subject to similar restrictions, but can seek to reach the motherboard ROM or I / O memory by addressing the range defined by $ 4000 0000 to $ 5 FFF FFFF . This means that CPU 1 a may have additional ROM or I / O memory (as part of memory 2 ) for the NuBus card (which is limited to access to the essential system ROM and I / O on the motherboard ) are not available. These embodiments of the invention, as shown in Fig. 10, are consistent with the NuBus standards, which require that a configuration ROM be placed on top of the 16 MB small (slot) space; therefore, the ROM space of slot $ 0 is located at the top of space $ F 000 0000 to $ F 0 FF FFFF .

The card according to the invention is described below with reference to FIGS. 4, 12 and 14. Fig. 4 shows a card according to the invention, which can be included in the described computer system by inserting them into one of the system slots, for example in slot 29 . The card has a printed circuit board 50 on which different lines, e.g. B. the card bus 65 and the connec tion buses 67, 68 and 69 forming electrical Verbindungsmit tel are arranged. Similarly, Figure 14 shows. A card 50 a according to the invention, which practically coincides with the set in Fig. 4 Darge card, except that it contains no CPU 61, which is the map 50 allows be züglich of NuBus- Bus 10 to act as a master, while the card 50 a in Fig. 14 can only serve as an auxiliary card, so it can neither take control of the NuBus 10 nor initiate a NuBus transaction. The cards 50 and 50 a have connections 51 , via which electrical connections with cooperating connections can be made in the slot in order to couple the various components on the cards with different signals appearing on the main circuit board 14 . All NuBus signals (to and from the NuBus) are buffered and inverted by buffers 59 on the cards. For example, bus 63 connects the address lines A31 to A24 of the NuBus 10 with the decoding device 60. The bus 63 also has supply and certain identification line means which, in this exemplary embodiment, contain four signal lines GA3, GA2, GA1 and GA0 which correspond to the Connections 52, 53, 54 and 55 are coupled. The signal GA3 is applied to the connector 52 through a cooperating connector in which the card 50 receives the slot. Similarly, signal GA2 is applied to terminal 53, signal GA1 to terminal 54, and signal GA0 to terminal 55 . These connections 52 . . . 55 are coupled to line means which apply the four signals (inverted) to the input 82 of the decoder 60 ( FIG. 12).

The signals present in the slot in this particular embodiment are given in Table 2 below and are NuBus signals. Of course, NuBus 10 contains a 32-bit address bus, which creates the address of the memory location searched for access in a first read cycle and acts as a data bus during a second cycle and records data stored in this memory location. During a write operation to memory, NuBus 10 carries the address of the location to be written into on its 32-bit address bus during a first cycle and delivers the data to be written into the memory location addressed in the first cycle during a second cycle. The NuBus 10 is practically an IEEE 1196 bus. The cards accept and use most of these signals, although their use depends on the specific needs of the cards and the goals of the designer.
Signal description

+5 V supply at slot. 5 volts. +12 V supply at slot. 12 volts. -12 V supply to slot. -12 volts. -5.2 VUnused in this example. All -5.2 V signals are at the slots joined together. Earth supply return line for +5 V, +12 V and -12 V. RESET signal when the collector is open. Created in case of voltage build-up by CPU 1 or by a push button RESET switch, which can be provided. Pulled up to +5 V through a 1 kOhm resistor. Slot card should send this signal to the Reset the circuit on the card to use. SPV slot parity valid. If a card Establishes parity on / SP, this becomes  Signal keyed. The ("/") indicates that the signal active at a low Level is d. H. activated his goal, when it goes low. PLC slot parity. Odd parity of / AD0- / AD31 if / SPV is pending. TM0-TM1 transaction modifier. Used during the start cycle to display the Scope of the transaction. Used while rend ACK cycle to display the status termination. AD0-AD31 NuBus address / data bits 0 to 31. Use detects addresses during the start cycle details. Used during the ACK-Zy klus for specifying data. NuBus specifications onen refer to these signals as AD0-AD31 or AD (31 ... 0) because they are the same 32 lines during a first cycle keep the address and then during data in a second cycle. PFW power failure warning. A col proofreading signal raised by one 220 W resistance at +5 V. If the signal is raised is the energy supplier activated. If the signal drops, so the energy supply is de-activated fourth. The energy supply itself expresses this signal as a drop in energy warning 2 ms before loss of change voltage down. this is a  Option under the IEEE 1196 standards. ARB0-ARB3 decision bits 0 to 3. collector-of fen signals ent in the slots speaking IEEE 1196 specifications (see e.g. table 6 of the specification) Are completed. Used for ent divorce over bus mastery between the slots according to NuBus-Spe certification. GA0-GA3 Geographic address bits 0 to 3. Fixed wired or hard coded binary address of the slot. Pens on earth fixed or open (or +5 V instead from open). START Created to queue an address to be indicated at A0-A31. Also for the start decision of bus mastery det. ACK confirmation. To the confirmation message of the Start cycle used. RQST request. Created to request the Bus mastery. NMRQNon-master requirement. A collector open signal, according to the IEEE 1196 specification (see e.g. Table 6 the specification) abge in the slot is closed. Used by the card to signal an interruption  and to interrupt the receiver. CLKNuBus cycle. Asymmetrical 10 MHz clock, which transactions on NuBus synchro nized.

The design and use of decoder 60 is known to those skilled in the art. It comprises the use of a comparator device with an activation device, the comparator comparing the NuBus address with the signal appearing on the specific line identification means and determining whether this address compares with the signal appearing on the specific line identification means and determining whether this address is within the for the memory 62 of the card is reserved memory space. The use of the decoder in this context for reserving a memory space of 256 megabytes, however, is new, and accordingly a simple decoder including a comparator and an activating device is described below. It is within the scope of expert action to provide other decoding devices which perform the functions of the invention accordingly.

In a typical transaction between the card 50 a and the CPU 1 , the memory 62 is selectively coupled to the CPU 1 via NuBus 10 and its associated interface 9 in order to obtain addresses and to supply data (or to receive data via the NuBus 10 ). The CPU 1 has a Adressenerzeugungseinrich processing for generating 2 different ³² Adressenerzeu restriction device in the range of the square $ 0000 0000 FFFF FFFF to the square $ for the production of 2 ³² different addresses. Addresses from the CPU 1 , which are 32 bits wide, leave the CPU 1 via the processor bus 5. The 32-bit address then enters the connection bus 25 and appears on the interface 9, which determines that the address within the NuBus - Address space that starts at $ 6000 0000. The memory 1 and the I / O circuit 7 are addressed by the CPU 1 below this address. The slot superspaces or the small spaces are addressed at and above this address. The interface 9 determines whether a NuBus address is selected and, after the address signals of the CPU 1 have been synchronized with the NuBus and the control of the NuBus 10 has been determined by the CPU 1, the address 1 appears on the NuBus 10 via the connection bus 11. For the purpose of explanation here it is assumed that a card shown in FIG. 14 is 50 a in slot $ 9, which has a certain number in the system of $ 9. The decoder 60 receives the address signals via NuBus 10 and determines whether the addresses are intended for the memory space of this card.

The decoder 60 has a comparator 70 which compares the most highly valued hexadecimal number of the address (for reading or writing) with the specific hexadecimal number of the slot into which the card having the decoder device 60 is inserted. The decoding device also has a control and clock signal generator 71 with connections for the NuBus clock and START and ACK signals. The decoding device can furthermore have a driver which is a component known per se in the prior art and is therefore not shown and which supplies sufficient current for driving the output signal of the decoding device 60 to sufficient levels at those outputs which lead to the chip selection ( CS) lead and pins of the memory 62 . A comparator 73, which is also part of the decoder 60 , compares the address to determine whether the small space of the slot is addressed. If one of the comparators (either 70 or 73 ) determines that the address appearing on NuBus 10 lies within the superspace or small space of the card, the special comparator together with the control device 71 activates the chip-out selection (CS) lines, connected to the memory 62 . As is known, the chip selection line (also sometimes referred to as chip activation signal line) serves to indicate to the memory, for example the memory 62 , that it is addressed either for reading or writing. The chip select lines are connected to line 64 as shown in FIGS. 4 and 14.

The comparator 70 of the decoder 60 has four exclusive OR gates ("XOR"), such as the XOR gate 76, which provides the GA3 signal (pending at input 92 ) with the most significant binary bit of 32 bits Address lines A31, entered at input 91 of XOR gate 76, are compared. As mentioned above, the NuBus signals in decoder 60 (on the card in buffers 59 ) are inverted; therefore the address signals are A31. . . A24 and START, ACK and CLK inverted in decoder 60 . Thus, the START signal in Fig. 12 is the inverted NuBus START signal. If the most significant bit of the address is equal to signal GA3, there is a logic zero at the output of XOR gate 76 , and this output signal is transmitted over line 93 to a 4-input OR gate 77 . The address signals A31 to A28 and certain signals, such as operating voltage and earth, are applied to the comparator 70 at the input 83 . These signals are then transmitted to the various XOR gates of comparator 70 ( Fig. 12). The output signal of each of the XOR gates in comparator 70 is a logic zero only if the two inputs to a particular XOR gate are identical. Therefore, each XOR gate performs a 1-bit comparison between a bit of a line carrying the bit as part of the special identification line means and one of the four top rated address lines. It can be seen that each of the exclusive OR gates generates a logic zero on the output side and causes the OR gate 77 and the node 70 a to be at a logic zero if a certain number in the hexadecimal system is equal to that on the highest rated hexadecimal digit of the address. The node 70 a is connected to the output of the OR gate 70 and also to one of the inputs to a NAND gate 90 , which is part of the control device 71 . The output of the comparator 73 is connected to the node 73 a in the Steuerein direction 71 and also to the other input of the NAND gate ter 90 . If an address is in the slot space of the card, the output of comparator 73 becomes a logic zero and node 78 (the output of NAND gate 90 ) becomes a logic one. If an address is in the slot's superspace, the output of comparator 70 becomes a logic zero and node 78 (the output of NAND gate 90 ) becomes a logic one. If the address is not in the small space of the slot and not in the super space of the card, node 78 becomes a logical zero (since node 70 a and node 73 a are each logically one). If the address is valid (during a START), the signal at the output of AND gate 87 becomes a logical one and clocked (with the next NuBus clock pulse (to the Q output of flip-flop 80, so that a logical one 1 at the node 79 occurs), therefore, if an address is valid and in the reserved space of the card (small space or super space), nodes 78 and 79 become logically one, causing line 64 to reach a logic zero, thereby activating memory 62 for addressing At the end of the period in which the address is valid, the output of AND gate 87 is clocked to a logic zero and to node 79 (via the JK flip-flop 80 ) and memory 62 is deactivated. If an address is valid START [as shown in FIG. 12] is logic one and ACK is logic zero (see the timing diagram shown in FIG. 12 of the START, ACK and CLK signals associated with device 71 ).

The ACK signal is inverted at the input to AND gate 87. Therefore, if an address is valid, the output of AND gate 87 is a logic one; if an address is invalid, START is a logic zero, causing the output of AND gate 87 to become a logic zero, a value that is clocked to the Q output of flip-flop 80 at the next NuBus clock pulse, as shown in FIG becomes. A logic zero at output Q deactivates the CS lines of memory 62 . The flip-flop 80 is a clocked JK flip-flop, the K input of which is pulled to the J ("D" -) input via an inverter. Such a flip-flop is sometimes referred to as a D-type flip-flop, where K is the complementary value of J. One end of the cycle signal can optionally be applied to the RESET input of flip-flop 80 . The signal is obtained from the control circuit on the card (e.g. CPU 61 ) and indicates the end of a transaction. The end of the cycle signal is active at a low value and is therefore inverted at the input to the RESET.

The particular output signal present on line 64 from controller 71 depends on whether memory 62 (according to the manufacturer) indicates that CS is active at a low value (ie at a low voltage similar to earth) or high (+5 Volt). In the example described here it is assumed that the memory 62 has an active low CS ("/ CS") and is therefore driven for addressing when the output signal of the device 71 is a logic zero. The activation of line 64 therefore occurs when the output signal from NAND gate 72 is a logic zero (low), causing CS to be virtually pulled to ground and thereby indicating through the memory chips (memory 62 ) that it is address be settled.

If there is no match between the particular number and the highest valued hexadecimal digit of the address, at least one logical one appears on one of the four outputs of the XOR gates in comparator 70, causing a logical one at the output of OR gate 77 and so that arises at node 70 a . This means that the address is not in the card's super space. In this case, the memory 62 can only be addressed by the NuBus 10 if the address is in the area 42 (small spaces).

The decoding device 60 also includes a comparator 73, who is responsible for the reservation of "slot space" for the 'specific card, located in the upper ¹ / _16th of the physical address space of the system (z. B. 42 in Fig. 3) is . In particular, the comparator 73 allocates sixteen megabytes of memory space for the card based on the special number of the slot in which the card is inserted. The comparator 73 has a NAND gate 85 , which determines when addresses pending on the card are in the area 42 . The exclusive OR ("XOR") gates of comparator 73, e.g. B. XOR gate 88 and OR gate 89 compare the second highest hexadecimal digit to the particular slot number into which the card is inserted to determine if the particular number equals the second highest hexadecimal digit to the 32-bit address bus from NuBus 10 is the existing address. When this equality condition occurs, each of the XOR gates of comparator 73, e.g. gate 88, produces a logic zero at its output, thereby causing the output of OR gate 89 to be a logic zero. The output from OR gate 89 is one of the input signals to OR gate 75. The four most significant binary bits of the address (A31 ... A28) are applied to the inputs of NAND gate 75 ; the output signal of this gate is only logic zero if the address is in the small memory area 42 . The output signal from NAND gate 85 is one of the input signals from OR gate 75. The input signals to OR gate 75 are both at a logic zero when the address in area 42 is in the small card space. Therefore, the output from OR gate 75 is only logic zero if the address is in the small space of the card. The address lines A27, A26, A25 and A24 form the second highest hexadecimal digit of the address pending on the 32-bit address bus of NuBus 10 .

If a card, for example card 50 a, is inserted into a slot with a specific number $ X , a decoder 60 causes the card to have a memory space from space $ X 000 000 to $ XFFFF FFFF and additional storage space of $ FX 00 0000 reserved for place $ FXFF FFFF .

Transactions between the CPU 1 and NuBus 10 require typi cally certain actions of the interface 9, terface as NuBus 9, is called. The exact implementation of the interface depends on the microprocessor provided as CPU 1 and on the buses assigned to it. In its simplest form, the interface could be designed as another decoding device with six decoders of the structure of the decoder 16 . This decoder receives six different specific signals with the specified numbers $ 0, $ 1, $ 2, $ 3, $ 4 and $ 5, each of which is provided for one of the six decoders. This arrangement would result in the resulting division of the physical address storage space shown in FIG. 3 for the computer system shown in FIG. 1. The interface 9 would also be required to synchronize timing differences between the CPU and the NuBus clock signals and would determine the ownership of the requested buses (whether NuBus 10 or processor buses 5, 25, and 6 ) by the master so that only one address at a time appears on all buses 10, 5 and 25 . Therefore, there would be some decoders as shown in Fig. 12, each of which receives a different particular signal. The output signal of these decoders would be applied to the CS pins of the memory 2 . At the same time, the CPU 1 would access the slots connected to the NuBus 10 by simply applying signals to the address bus 5 coupled to the interface 9 , whereby interface 9 could enable the address signal coming from CPU 1 to be applied to NuBus 10 in a similar manner CPU 1 deliver data to NuBus slots by placing data on the data bus 6 , whereby the data signals appear at the NuBus interface 9 via the connection bus 12 and then transmitted to the NuBus 10 and depending on the immediately preceding address signal on NuBus 10 from the ent speaking slot. In fact, the CPU 1 and its associated circuitry including the NuBus 10 memory 2 would appear as if they were on a card in slot 0 or slots 1, 2 and 3 . In the following discussion of a NuBus interface, the term "processor bus" is generally used for the data bus 6 connected to the CPU 1 and the memory 2 and the address buses 5 and 25 ( FIG. 1).

The NuBus interface 9 has, as shown in Fig. 5, three state machines and the NuBus clocks on, which provide functions the interface between the six slots (29, 30, 31, 32, 33 and 24) and the NuBus 10 and the CPU 1 and the SpeI cher 2 and their associated circuit on the motherboard 14 meet. In general, the interface 9 must be the assignment of the desired bus or buses between the master machines, for. B. CPU 1 and a CPU on a card (z. B. CPU 61 ) to prevent two different addresses of two different CPUs from appearing on a bus, such as bus 5 or NuBus 10 at the same time. That is, the interface 9 must take ownership of the bus by deciding among different masters requesting the same bus in order to prevent address collisions on a bus. Similarly, during data cycles, the interface must make the decision about bus ownership among possible masters requesting the same bus in order to prevent data collisions on a bus (for example bus 6 or NuBus 10 ). Finally, the interface 9 must synchronize the signals of the requesting master with the timing of the desired bus which is controlled (for addresses or write operations) or heard (for reading data) by the master. The interface can be implemented in a programmable logic memory array by known techniques.

The signals available on NuBus are described in the 1196 specification of the IEEE and in the Texas Instruments publications mentioned above. In general, the NuBus standards specify logical, physical and electrical standards for the four types of signals present in the NuBus bus 10 . These signals include usage signals such as the clock and the particular identification line means; the address / data signals along with various control signals; the decision signals; and the operating signals. It can be seen that certain of these NuBus signals appear on the left side of the NuBus interface 9 according to FIG. 5. Signals supplied by the CPU 1 or the memory 2 flow through the interface or allow the interface to allow the CPU 1 to communicate with NuBus 10 and vice versa. The following table describes the signals used in the NuBus state machine for the NuBus interface 9. The particular implementation of the interface 9 depends on the particular CPU 1 selected for use on the motherboard, with the designer's objective.
Signal description

RQSTA NuBus signal; active low; indicates a request for bus ownership. NUBUSDecoded address from processor CPU 1 , which indicates an address reference to NuBus; active low. The address of CPU 1 is decoded in a decoder, which can be designed in a known manner by a person skilled in the art and determines when the address on bus 25 is in the NuBus address range from $ 6000 0000 to $ FFFF FFFFF . STARTNuBus signal; active low; indicates that there is an address on NuBus. ARB0-ARB3 NuBus signal; active low; Decision address of bus masters that compete for NuBus ownership. ACKNuBus "confirmation signal"; active low; NuBus secondary device confirms START transaction. RMC processor CPU 1 signal indicates that a read / modify / write operation is occurring on CPU 1 buses 6 and 25 . ASProcessor CPU-1 address strobe indicates that the address lines from CPU 1 are valid and a cycle is requested. Active low "/ AS". / BUSLOCK The processor buses 6, 5 and 25 cannot be interrupted by NuBus transactions in memory 2 . DSACKx The data stream confirmation from memory 2 . BGProcessor CPU-1 bus grant indicating that processor buses 5, 6 and 25 have been made available to the NuBus for traffic to memory 2 using the NuBus-To-Memory 2 state machine 104 . C16M The processor CPU 1 clock that is used to qualify signals from processor CPU 1 as valid. R / WRead / Write signal used to indicate a read or write operation. / B A NuBus bus request requesting control of the processor buses, primarily line 6 (via bus 12 ) and 5 and 25 . / BGACKNuBus signal from the NuBus state machine 104 that confirms the processor's assignment of the processor buses. NuBus typically requests control of the processor buses by issuing a / BR signal; the processor bus request is granted by the signal / BG, which is picked up by the NuBus-To-Memory- 2 state machine 104 which acknowledges receipt of the processor bus assignment. / BERRBus error signal from NuBus, which indicates an error in the system. This signal is typically output by the NuBus timeout state machine 105 , which looks for transactions lasting approximately 25 microseconds. Such a transaction is assumed to be faulty by the bus time-out state machine and results in the / BERR signal which is sent to the processor. / DS data strobe: A NuBus signal that indicates that data lines from the NuBus bus are valid and a cycle is requested.

The processor CPU 1 typically accesses and requests the NuBus 10 whenever the processor CPU 1 generates a physical address from $ 6000 0000 to $ FFFF FFFF . The CPU 1 -to-NuBus state machine 103 determines that such a request is present when decoder specify on the ge with bus 25 coupled mother board, that an address on bus 25, the most significant hexadecimal digit between $ 6 and $ F, including Has $ 6 and $ F. Under these circumstances, the output of these decoders causes the / NUBUS signal to be applied. The state machine 103 then synchronizes the request for the NuBus control with NuBus clock and applies the same address over the bus 10 to, after having determined that the CPU can take over 1 NuBus 10, to transmit address signals to the NuBus 10th When a card responds to NuBus, the data is transferred. If no card responds, a 14588 00070 552 001000280000000200012000285911447700040 0002003808193 00004 14469 a NuBus timeout occurs and a bus error (/ BERR) is given to the processor, which usually causes an error handling routine to be executed. The NuBus timeout state machine 105 monitors the time between START signals on NuBus and confirmation signals (ACK) on NuBus. If the time between these signals exceeds 255 NuBus clocks according to NuBus standards, the NuBus timeout state machine generates the bus error in the manner indicated above. FIG. 8 shows the processor- 1 -to-NuBus transaction via the NuBus interface 9 and in particular via the processor-to-NuBus state machine 103. The signals on the right side of block 103 in FIG. 8, which are directed to the CPU 1 side of machine 103 , are NuBus signals. The right side of machine 103 is the NuBus side of the system and has the six slots. On the left side of the interface 9 is the CPU 1 and the memory 2 section of the system. This also applies to FIG. 9. Signals that enter machine 103 from the NuBus side (ie the arrow points towards machine 103 ) are generally NuBus signals and signals exiting machine 103 on the NuBus side are generated by the CPU or the result of the interaction of CPU 1 and machine 103 . Similarly, signals on the CPU 1 side of machine 103 that enter machine 103 are signals generally from CPU 1 or memory 2 or from circuits associated with that part of the system. The signals on the CPU 1 side of machines 103 and 104 are transmitted by bus 12 of FIG. 1, and the signals on the NuBus side of machines 103 and 104 are transmitted by bus 11 .

The CPU- 1 to NuBus transaction begins with state machine 103 waiting for the / NUBUS signal to be asserted (which is synchronized with the 10 megahertz NuBus clock). If this signal is present and there are no other bus masters RQST on NuBus 10 , state A, the previous waiting state, is transferred to state B. In state B, the RQST signal is applied by NuBus and CPU 1 requests a request for NuBus 10 among other bus masters that create RQST at the same time. For decision purposes under the NuBus standards, CPU 1 is assigned to slot $ 0.

State B is followed by state C, in which the decision and confirmation (ACK) signals are sampled to check whether another NuBus transaction is in progress or whether the NuBus 10 has been assigned to another NuBus master. If a transaction is in progress and no other bus master has received control, state C is maintained. If another bus master requested the bus during state B, state D is entered. (It should be noted that the processor CPU 1 accesses the bus from slot $ 0 and therefore always loses compared to other slots, since the decision is based on the specific number under the NuBus standard). If no other master has gained bus control and no other transaction is in progress, state E is entered. In state E, the START signal of the NuBus bus 10 is applied and the address is transferred from the CPU 1 to the NuBus 10 .

It is understood that latches and buffers are used to temporarily store addresses and data in these state machines 103 and 104 and generally in the system. A state F follows state E and waits for an acknowledgment signal (ACK) from the addressed card. If the confirmation signal is present at the NuBus 10 and no other masters claim the bus, a state G is entered in which DSACKx signals are generated to the processor CPU 1 in order to end the process cycle. If no other master RQST applies during state G, state H is entered, in which the NuBus is "parked", which means that a second NuBus transaction from processor CPU 1 goes directly to state E and not only to state A can go to start NuBus access. If RQST is pending during states F, G or H, a new decision must be made via NuBus in order to determine the current bus master, and state A becomes a waiting state instead of state H. These state sequences can be carried out using known state machine methods. The following table summarizes the states and signals which run in the processor CPU- 1 -NuBus interface and are executed by the CPU-On-NuBus state machine 103.

Table 4

Processor CPU 1 at NuBus states

The state machine according to FIG. 8 receives address signals of the CPU 1 (A0-A31) from the CPU 1 on the bus 25. The signals appearing on the right side of the state machine 103 are NuBus signals. Certain signals on the left side of the state machine 103 are also NuBus signals, e.g. B. the clock signals / CNS10M and C20M and / NUBUS, although the latter is caused by the CPU 1 by generating a NuBus address.

The NuBus-On-CPU- 1 bus state machine 104, shown in FIG. 9, is used to access memory 2 (which may include RAM, ROM, and I / O) from the NuBus. In one embodiment, when an address in the range of $ 0000 0000 to $ 5 FFF FFFF is applied to the NuBus, the state machine 104 requests the processor buses from the CPU 1 and performs address access. An alternative embodiment ( Fig. 10) is also described in which access to the RAM of memory 2 by addressing $ 0000 0000 to $ 3 FFF FFFF and accesses to the ROM or I / O of the motherboard by addressing $ F 000 0000 to $ F 0 FFF FFFF take place. After the data has been transferred to or from the NuBus master (ie the card in the NuBus slot), the control of the processor buses 5 and 6 is normally returned to the processor CPU 1 .

The following table describes the states and signals in the NuBus-To-CPU- 1 bus transaction.

Table 5

The NuBus-To-CPU- 1 bus transaction begins with the state A1 shown in Table 5, in which the state machine 104 is in idle mode and to an address on NuBus 10 in the memory space of memory 2 (e.g. $ 0000 0000 to $ 5 FFF FFFF; or, in the alternative embodiment shown in FIG. 10, $ 0000 0000 to $ 3 FFF FFFF and $ F 000 0000 to $ F 0 FFF FFFF ). NuBus access to the processor buses can be prevented by applying the bus lock signal, which causes all NuBus transactions in this address space to be confirmed with a "try again later" response. If the address is within memory 2 space and buslock is not created, state B1 is entered.

In state B1, CPU 1 enables the processor buses by specifying a bus assignment signal (BusGrant), which is used to respond to a bus request. The bus grant is confirmed by the NuBus device with a bus grant actuation signal in the next state C1. The addresses are placed on the processor address buses and the data is transferred in states D1 or E1. The transaction is completed in F1 when the NuBus ACK signal is present on NuBus 10 .

In the alternative embodiment according to FIG. 10, the NuBus devices access the RAM of memory 2 by applying addresses in the range from $ 0000 0000 to $ 3 FFF FFFF . NuBus devices in this embodiment access part of the motherboard ROM storage space and part of the motherboard ROM storage space and part of the motherboard I / O storage space (which is usually a secondary physical ROM for I / O use ) indirectly by creating addresses on NuBus 10 in the range $ F 000 0000 to $ F 0 FF FFFF (slot space $ 0). In this embodiment, addresses on NuBus 10 in the range of $ 4000 0000 to $ 5 FFF FFFF do not access ROM or I / O; however, addresses on CPU 1 buses (e.g., bus 5 ) access the full motherboard ROM and I / O memory space in this area. In accordance with NuBus standards, that part of the ROM of the motherboard (at least allocated to slot $ 0) that is accessible to NuBus is arranged at the top of the slot space $ 0. The particular allocation of memory in slot space $ 0 between motherboard ROM and motherboard I / O depends on the needs of the designer. In a preferred embodiment, slot space $ 0 is divided in half so that an address from $ F 080 0000 to $ F 02 F FFFF on NuBus 10 provides access to an 8 megabyte area of the ROM of the motherboard (ie, ROM of the memory) 2 ), and an address on $ F 000 0000 to $ F 07 FF FFFF on NuBus 10 causes access to an 8 MB (megabyte) area of the I / O memory space. The special 8M areas of ROM and I / O memory space depend on which memory areas NuBus devices need and want. Often, the entire system (motherboard) ROM and motherboard I / O memory fits into the 16 MB area of slot space $ 0. Known decoders can be used to effect decoding from the NuBus address in slot space $ 0 to the appropriate ROM and I / O location.

Claims (21)

1. Computer system with a main circuit board ( 14 ) having a central unit ( 1 ) and slots ( 29 ... 34; 130 ... 144 ) for receiving a printed circuit board ( 50; 50 a ), further with one with the CPU ( 1 ) coupled memory ( 2 ) for receiving addresses of the memory locations from the CPU and for supplying data to the CPU, the memory ( 2; 62 ) on the main circuit board ( 14 ) and / or at least one card ( 50 , 50 a ) is arranged and the main circuit card ( 14 ) has an input / output circuit ( 7 ) with the memory ( 2; 62 ) for entering data in this memory and with the CPU ( 1 ) for recording of control signals from the CPU is coupled,
characterized,
that the main circuit board ( 14 ) has fewer than 16 slots and has a 32-bit address bus ( 5, 10; 120 ) which is coupled to the CPU ( 1 ) and the memory ( 2 ) for addressing the memory,
that the CPU ( 1 ) has an address generating device for generating 2 ³² different addresses for addressing the memory via the 32-bit address bus ( 5 ),
that the 2 ³² different addresses are in the range from place $ 0000 0000 to place $ FFFF FFFF , the place being provided in hexadecimal notation,
that each of the slots ( 29 ... 34; 130 .... 144 ) has a special number in the system, is coupled to the bus ( 5, 120 ) for addressing the memory and to a special identification line means on the main circuit board,
that each of the special identification line means gives a special signal to the slot coupled to the special identification line means, the special signal for a particular slot identifying the specific number of the particular slot and the special number of a particular slot (ID) , and
that the special number reserves 256 megabytes of memory space for each of the slots such that the 256 megabyte memory space begins at location $ (ID) 000 0000 and ends at location $ (ID) FFF FFFF, thereby giving each card in slot X a memory space reserved that starts at location $ X 000 0000 and ends at location $ XFFF FFFF and that the locations are in hexadecimal notation. 2. Computer system, in particular a personal computer system, with a main circuit board ( 14 ) which has a central unit ( 1 ) and slots ( 29 ... 34, 130 ... 144 ) for receiving a printed circuit card ( 50; 50 a ) , further comprising a memory ( 2, 62 ) coupled to the CPU ( 1 ) for receiving addresses of the memory locations from the CPU and for supplying data to the CPU, the memory ( 2, 62 ) on the main circuit board ( 14 ) and / or at least one card ( 50, 50 a ) is arranged and the main circuit card ( 14 ) has an input / output circuit ( 7 ) which is connected to the memory ( 2 ) for entering data into this memory and to the CPU ( 1 ) is coupled to receive control signals from the CPU, characterized in that
that the main circuit board ( 14 ) has fewer than 16 slots and has a 32-bit address bus ( 5, 10; 120 ) which is coupled to the CPU ( 1 ) and the memory ( 2 ) for addressing the memory,
that the CPU ( 1 ) has an address generator for generating 2 ³² different addresses for addressing the memory via the 32-bit address bus, the 2 ³² different addresses having a memory address space in a range from space $ 0000 0000 to space $ FFFF FFFF Define the area and the places are in hexadecimal notation,
that each of the slots ( 29 ... 34; 130 ... 144 ) has a special number in the system with the 32-bit address bus for receiving addresses for one on the card ( 50 ) located in the slot arranged memory ( 62 ) and is coupled to a special identification line means on the main circuit board,
that each of the special identification line means gives a special signal to the slot coupled to the special identification line means, each of the special signals providing the special number of the slot receiving the special signal, and that 256 megabytes of memory space ranging from space $ X 0000 0000 to Space SXFFF FFFF are reserved for a memory on a card ( 50; 50 a ) in a slot ( 29 ... 34 ) that has a special number equal to $ X , where $ X is an integer from $ 0 to $ E. 3. Personal computer system according to claim 2, characterized in that $ X is an integer in the range from $ 9 to $ E and the main circuit board ( 14 ) has six slots ( 29 ... 34 ). 4. Computer system according to one of claims 1 to 3, characterized in that the special identification line ( 4 ) contains binary lines each carrying lines and that the 32-bit address bus also transmits control signals and is essentially a NuBus bus. 5. Computer system according to one of claims 1 to 4, characterized in that 16 megabytes of memory space in the range of $ FX 00 0000 to $ FXFF FFFF are reserved for memory on a card in a slot with the special number equal to SX . 6. Computer system with a main circuit board ( 14 ) having a substantially as a NuBus system bus including a 32-bit address bus for the transmission of address, data and control signals and slots for receiving a printed circuit board, each slot with the system for receiving address and data signals on the bus and for delivering address and data signals to the bus is coupled, the main circuit board further comprising fewer than 16 slots, a first card ( 50 ) in one of the slots and a second card ( 50 a ) are inserted in another slot, the first card is coupled via the one slot and the second card via the other slot to the system bus, the first card ( 50 ) also being a CPU ( 61 ) and one has the first memory ( 62 ) coupled to the CPU via a card bus ( 65 ) and the CPU and the first memory are coupled to the system bus, the second card ( 50 a ) has a second memory ( 62 ) and a decoding device ( 60 ) which couples the second memory to the system bus in order to enable the second memory to receive addresses from the system bus and to supply data to the system bus, characterized in that that the CPU has an address generation device for generating 2 ³² different addresses for addressing the first ( 62 ) and the second ( 62 ) memory, that the 2 ³² different addresses define a memory address space in the range from space $ 0000 0000 to space $ FFFF FFFF that each of the slots has a special number in the system, is coupled to special identification line means on the main circuit board ( 14 ), that each of the special identification line means applies a special signal to the slot coupled to the special identification line means, the special signal for one slot the special number mer of the particular slot provides that furthermore the other slot is a special number equal to $ X with $ X equal to an integer from $ 0 to $ E , that the decoder ( 60 ) the special number with the highest hexadecimal number one appear on the system bus Address compares to determine when the particular number in the hexadecimal system is equal to the highest hexadecimal number of the address, that the decoder releases the second memory for addressing, in order to then supply data when the special number in the hexadecimal system is equal to the highest hexadecimal number of the Address, and that the second memory is addressed whenever addresses between $ X 000 0000 and $ XFFF FFFF appear on the system bus, resulting in 256 megabytes of memory space, starting at location $ X 000 0000 and ending at location $ XFFF FFFF be reserved as memory on the second card. 7. Printed circuit card with connections that are suitable for the manufacture of an electrical connection with suitable connections at a card-receiving slot on a main circuit board of a computer system, the main circuit board being a central processing unit (CPU), one for receiving addresses of the memory locations the CPU and for supplying data to the CPU with the memory coupled to the latter, a 32-bit address bus which is coupled to the CPU and the memory for addressing the memory, and an input / output circuit which is connected to the memory for Delivery of data to the memory and coupled to the CPU for receiving control signals from the CPU, the slot being coupled to the 32-bit address bus, characterized in that the CPU has an address generator for generating 2 ³² different addresses in the range from place $ 0000 0000 to place $ FFFF FFFF , the places in hexadecimal notation vo It is seen that the slot has a special number in the computer system and is coupled to special identification line means on the main circuit board, that the special identification line means deliver a special signal to the slot which identifies the special number of the slot that the card one with the special Identification line means for receiving the special signal coupled decoder which compares the special number with an address appearing on the 32-bit address bus and a reservation of 256 megabytes of memory space for this slot causes such that X is equal to the special number of the slot the 256 megabytes of storage space begin at space $ X 000 0000 and end at space $ XFFF FFFF , with the spaces in hexadecimal notation . 8. Printed circuit card according to claim 1, characterized in that the card located in slot X has a second memory arranged on the card itself, which with the CPU via the 32-bit address bus for receiving addresses of the memory locations from the CPU and coupled to provide data to the CDU, the second memory is coupled to the 32-bit address bus, which provides an address during a first cycle and receives data arranged at the address during a second cycle, and that the second memory reserves Has memory locations that begin at location $ X 000 0000 and end at location $ XFFF FFFF, where X is an integer between 1 and 14. 9. Printed circuit card with connections, which when plugged into a slot on a main circuit board of a personal computer system with suitable slot connections can produce electrical connections, the main circuit card being a central processing unit (CPU), one with the CPU for receiving addresses of the memory locations from the CPU and for supplying data to the CPU coupled first memory, a 32-bit address bus, which is coupled to the CPU for taking over addresses from the CPU, and an input / output circuit, which has a first memory for Supply of data to the first memory and coupled to the CPU for receiving control signals from the CPU, the slot being coupled to the 32-bit address bus, characterized in that the CPU has an address generator for generating 2 ³² different addresses in the Range from place $ 0000 0000 to place $ FFFF FFFF in hexadecimal notation of the places shows that de r slot has a special number in the computer system and is coupled to special identification line means on the main circuit board, that the special identification line means give a special signal to identify the special slot number to the slot, that the card has a second memory arranged on the card, which that the second memory is coupled to the 32-bit address bus, which supplies an address during a first cycle, is selectively coupled to the CPU via the 32-bit address bus for receiving addresses of the memory locations and for supplying data via the address bus and receives data located at the address during a second cycle, that the card also has a decoding device, which is coupled to the special identification line means for receiving the special signal, compares the special number with the most highly valued hexadecimal number of the address, to see if the special number in the hexadecimal system is equal to the highest-valued hexadecimal number of the address, and the second memory is activated for addressing to provide data if the special number in the hexadecimal system is equal to the highest-valued hexadecimal number of the address, so that the second memory in If X is addressed as the slot's special number, whenever addresses in the range of $ X 000 0000 to $ XFFF FFFF appear on the 32-bit address bus, thereby reserving 256 megabytes of memory space for the card in the slot and the 256 megabytes of reserved storage space begin at space $ X 000 0000 and end at space $ XFFF FFFF. 10. Printed circuit card according to claim 9, characterized in that the 32-bit address bus also contains control signals and is practically designed as a NuBus bus and that the second memory ( 62 ) has at least one RAM and one ROM. 11. Printed circuit card according to claim 9, characterized ge indicates that the 32-bit address bus also control signals contains and is essentially an IEEE 1156 bus and that the second memory has a RAM. 12. Printed circuit card according to claim 9, characterized in that the second memory has a RAM, that the special identification line means contain four lines each transmitting binary values, that the main circuit board six slots with the special numbers $ 9, $ A, $ B, $ C, 01.01.80E, each of which has its own special identification line means for transmitting its own special signal for identifying the special slot number, wherein a slot with the special number $ 9 is a slot $ 9 and the special identification line means coupled to the latter is the value Delivers $ 9 to the $ 9 slot. 13. Printed circuit card according to claim 12, characterized in that the 32-bit address bus also contains control signals and is essentially designed as a NuBus and is angeord net and that the decoder ver the special number with an address appearing on the 32-bit address bus equals and causes a reservation of 16 megabytes of memory space for the slot, such that when X is equal to the special number, the 16 megabytes of memory space begin at location $ FX 00 0000 and end at location FXFF FFFF. Printed circuit card according to claim 13, characterized in that the decoder determines when the highest valued hexadecimal number is $ F , that the decoder compares the determined number with the second highest hexadecimal number of the address to determine when the specific number in Hexadecimal notation is equal to the second highest hexadecimal digit, the decoder further addresses the second memory so that it supplies data when the specific number in hexadecimal notation is equal to the second highest hexadecimal digit and when the highest hexadecimal digit is $ F , so that X is equal to special slot number the second memory is addressed whenever addresses between $ FX 00 0000 and $ FXFF FFFF appear on the 32-bit address bus, whereby the 16 megabyte memory space begins at location $ FX 00 0000 and at location $ FXFF FFFF ends. 15. Printed circuit card according to one of claims 12 to 14, characterized in that the card also has a second Central unit (second CPU) having the second Memory for addressing the second memory and for opening Taking data from the second memory is coupled. 16. Printed circuit card according to claim 15, characterized ge indicates that the second CPU with the 32-bit address bus for Execution of NuBus transactions via the 32-bit address bus is coupled and that the card acts as bus master for the NuBus Transactions are appropriately trained. 17. Printed circuit card according to claim 16, characterized ge indicates that the second CPU with the Inten 8088 micropro  processor is essentially compatible. 18. Printed circuit card according to claim 16, characterized ge indicates that the second CPU with the Intel 8086 micropro processor is essentially compatible. 19. Printed circuit card according to claims 16, characterized ge indicates that the second CPU with the Intel 80286 micro processor is essentially compatible. 20. Printed circuit card according to one of claims 15 to 19, characterized in that the second memory by the second CPU without a NuBus transaction locally on the card is addressable. 21. Printed circuit card according to one of claims 15 to 20, characterized in that the decoding device ( 60 ) has comparator means which determine whether addresses are present on the card from the second CPU in the local address space of the card, that the decoding device is a NuBus - Transaction prevented when the addresses are within the local card address space, and that the local card address space when the card is arranged in slot X, the positions $ 0000 0000 to $ 1000 0000, $ X 000 0000 to $ XFFF FFFF and $ FX 00 0000 to $ FXFF FFFF contains.