JPS5897944A - Data transfer system among microprocessors - Google Patents

Abstract

PURPOSE:To reduce processing with reference to change of connection of a queue and to improve the performance of bucket switching, by providing a hardware queue for storing addresses of software queues generated in a common memory. CONSTITUTION:A bucket switchboard consists of a microprocessor CPU, local memory LM, local bus LB, circuit control unit LCU, common bus CB, and a bus interface unit BIU, and bucket switching processing is performed by plural communication control processor modules CCP. The CCPs are connected mutually through the common bus CB; and a common memory CM for buffering data during data transfer among processors, and a hardware pointer queue HQ stores address of software data queues in the common memory and is connected to the common bus.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for transferring data between multiple processors using a hardware pointer key when performing data transfer between the microprocessors via a common memory in a packet switching equipment configured with multiple microprocessors. Regarding data transfer method.

Conventionally, in a packet switch constructed of multiple microprocessors having local memories that transfer data via a common memory, queue ink is sent to a software queue on the destination route side by a transfer source microprocessor onto a common memory, and The strategic light microprocessor
Data was transferred between microprocessors by scanning the common memory and, if there was data destined for itself, removing the queue and taking the data. That is, data to be transferred to the strategy side is queued on the common memory, and an empty queue is also queued. Each key has the same data length, and is usually composed of tens to hundreds of bytes. Therefore, the head pointer indicating the memory address of the first queue and the tail pointer indicating the address of the last queue are stored in a predetermined area in the common memory for each queue system for each route (for 1 free key). Must be set. For all keys except the last key, the address of the next key is placed at the head of the queue.

When a microprocessor transfers data to a certain microprocessor, the head pointer of the free queue is rewritten from the address of the first queue to the address of the second queue, and the data to be transferred is written to the first queue. . Next, the tail pointer of the strategic queue corresponding to the destination microprocessor is read to determine the address of the final queue. Rewrite the head part of the final queue and the tail pointer of the route-specific key to the address of the queue into which the data was just written. At this time, a test and set function is required to prevent miscommunication between microprocessors that operate asynchronously. It's loud.

In terms of the operation up to the queue ink to the key for each strategy, when writing data to an empty queue, one microprocessor may read the head pointer of the empty key. If a microprocessor that has issued a request to write data to another free queue reads the head pointer before updating the contents of the head pointer, the microprocessor that read the head pointer first will write the head pointer. Although the microprocessor that read the head pointer later uses the key island of the address indicated by the head pointer, the contents of the head pointer have not been updated, so it reads the same address as the previous one. Attempt to use -key. In this case, double writing of data to the same queue occurs, and the previously written data is lost. A similar misunderstanding phenomenon occurs when reading and writing the tail pointer to the strategic queue. If a mismatch occurs, phenomena such as data loss or mismatch between the contents of the head pointer or tail pointer and the actual address of the first queue 1 final key occur, making data transfer impossible. For this reason, we provide a set of registers that correspond to a series of pointers that indicate whether or not reading and writing of pointers are permitted, and test the corresponding registers when reading and writing pointers. It determines whether the pointer is available or not by reading the pointer, and if it is possible, it sets a register, reads the contents of the pointer, performs a series of updating processes, and then resets it. The above is a function called test and set. As mentioned above,
Queuing data on a common memory requires very complicated procedures. Since the above processing is performed by the microprocessor, when the amount of data to be transferred is large, the microprocessor is busy with these processes, resulting in a reduction in the actual packet switching processing capacity.

An object of the present invention is to reduce the processing related to the above-mentioned queue reconnection by providing a hardware queue that stores the addresses of software caches created on a common memory. An object of the present invention is to provide a data transfer system between multiple microprocessors with improved packet switching capability.

A data transfer method between multiple microprocessors of the present invention,
A microprocessor accommodating a plurality of microprocessors that accommodates a plurality of data lines and performs packet switching processing, an area for storing a program that defines the operation of the microprocessors, and a work area for packet switching processing. a local memory connected to the microprocessor, a local bus that individually connects the data line to the local memory and the data line through an interface circuit, a common bus that interconnects the microprocessor in a manner similar to that; A common memory is connected to the path, is accessible from any microprocessor, and buffers data when transferring data between microprocessors; a plurality of hardware pointer queues that store the addresses of software queues in common memory, and a hardware pointer queue that stores the addresses of free keys among the software keys created in common memory; When data is transferred between microprocessors via the common memory in a packet switch consisting of a queue and After reading and writing, the address of the empty key is known, and after writing the transfer data to the previous P empty key in the common memory, it is written to the key corresponding to the destination microprocessor in the hardware pointer queue on the strategy side. , writes the address of said queue. Furthermore, the destination microprocessor learns the address of the queue from the contents of the hardware pointer queue destined for itself. It is characterized in that data is transferred via the common memory by writing the address of the queue from which the data was received into a-.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a dormitory embodiment of the present invention.

The packet switch in this embodiment accommodates a microprocessor CPU, a four-dimensional memory LM having a work area for executing programs and programs, and a plurality of data lines, and is directly connected to the microprocessor. - A bus interface unit that interfaces between the local bus LB and the data line (LCU), a bus interface unit (BIU) that interfaces between the local bus LB and the local bus LB, and multiple controllers that perform packet switching processing. Two cage control processors and seven Sierra CCPs are provided. Furthermore, each control processor module CCPφ0 to CCP reference n has a common path CB.
The common memory CM, which buffers data during data transfer between processors, and the address of the software data queue inside the common memory are stored on the common path CB, and are connected to the common path CB. It consists of a hardware pointer and a hardware pointer HQ.

FIG. 2 shows in detail the state of the hardware pointer -HQ and the software data queue inside the common memory CM. In Figure 1, the communication control processor module and CCP range from 1 to Ni.
Suppose there are N pieces.

Hardware pointer & 1.21~2N consists of multiple first-in first-out, and can be read and written by each microprocessor through a common path. Stores the key pointer address. Free software data key &-1 and strategy-side software data key corresponding to the destination microprocessor, -2
There are N+1 in total, corresponding to 1 to 2N. Inside the common memory 3゜41 to 4N, an empty queue and a data queue are stored at the address indicated by the hardware pointer queue.
has been ing. 5. Arrows indicate microprocessors corresponding to queues and pointers.

Next, an example of actual operation will be explained. In order to transfer data held by microprocessor 1 between microprocessors, microprocessor 1 first points to the first pointer of hardware pointer queue 1 that stores the address of an empty queue. Take over. Next, the data to be sent is written to the queue on the common memory indicated by the retrieved pointer. After writing is completed, the destination pointer is written to the end of the hardware pointer -JM of the route corresponding to the microprocessor M. This completes the inking of the data. Keys on common memory, - are free keys & -3
This means that the strategy queue 4M addressed to Michael Pursessa M is laid out from the beginning. ! The PC processor M sometimes reads the status of 2M and goes to the DK, and can know whether there is a data queue addressed to it or not. If you have a data queue addressed to you! Iku p The data in the queue on the common memory indicated by the pointer read from the hardware pointer -2M for the route addressed to processor M is taken.

After the read and write is completed, the previous pointer is written to the end of the hardware pointer queue that stores the address of the empty key. This completes the data transfer from the microphone IL processor 1 to the microprocessor M via the common path.

Data can be transferred in the same way between other microphones. Therefore, compared to the conventional system, the processing by the microprocessor associated with reconnecting the data queues inside the common memory can be greatly reduced by simply reading, writing, and writing to the node-ware pointer queue.

As described above, in the present invention, when data is transferred between multiple microprocessors constituting a packet switch via a common memory, the processing associated with updating the pointer accompanying writing and reading of the queue in the common memory is performed. This eliminates the need for test and set processing when updating pointers. This has the effect that the processing by the microprocessor due to data transfer is reduced, and the efficiency of the packet switching processing is improved accordingly.

[Brief explanation of the drawing]

FIG. 1 is a pull diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration of a hardware pointer queue and common memory of the embodiment in correspondence with a microprocessor.

Claims (1)

[Claims] A microprocessor that accommodates a plurality of data lines and performs packet switching processing, an area for storing memory that defines the operation of the microprocessors, and a work area for packet switching processing. a four-cal memory provided to support the p-scenario; the microprocessor; a p-cal memory;
A local path that connects the data lines individually through an interface circuit, a common path that interconnects the microprocessors in an intuitive manner, and a data transfer between the microprocessors connected to the common path. , a common memory for buffering data, a plurality of node-ware pointer queues provided on the strategic side corresponding to the microprocessor and written to and read from through a common path, and created on the common memory. When data is transferred between microprocessors via the common memory in a packet exchange system consisting of a software pointer and a hardware pointer that stores a pointer to an empty queue,
The contents of the hardware pointer that stores the address of the queue in the free state on the common memory are transferred to the hardware pointer on the route side, and the microprocessor that received the data indicates the free state from the hardware island on the route side. Data transfer method between multiple micro processors characterized by transferring data via a common memory, 1