JPH06284453A - Atm cell switch - Google Patents

Abstract

PURPOSE:To suppress the scale of a hardware constitution, and to reduce cell loss by providing a common buffer in which surplus cells further transmitted from input buffers to output buffers whose cell storage capacities are fulfilled are temporarily saved. CONSTITUTION:When the cell storage capacities of specific output buffers 131-13n are fulfilled, a control part 15 transfers the surplus cells further transmitted to the buffers 131-13n, to a common buffer 14, and prepares the list of a header. The buffer 14 writes the cells in a memory 4 according to a writing signal transmitted through a signal line 18n+1. The control part 15 monitors the empty states of the buffers 131-13n. When the empty capacities are generated at the buffers 131-13n the control part 15 retrieves whether or not the surplus cells to the buffers 131-13n are stored in the buffer 14, and when they are stored in the buffer 14, the control part 15 reads the surplus cells from the buffer 14 to the buffers 131-13n. The reading of the surplus cells is operated at random regardless of a writing sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a digital telecommunication switching device. In particular, it relates to a technology for downsizing an ATM (asynchronous transfer mode) switching device.

[0002]

2. Description of the Related Art A conventional ATM cell switch will be described with reference to FIG. FIG. 4 is a block diagram of a conventional device. The input buffers 11 _{1 to} 11 _m are connected to the input ports I ₁ to
The cells input from I _m are temporarily stored. Multiple bus 12
It is transferred to the output buffer 13 ₁ to 13 _n a cell outputted from the input port I ₁ ~I _m for each destination. The output buffers 13 _{1 to} 13 _n temporarily store cells output from the output ports P _{1 to} P _n . These operations are controlled by the control unit 15.

When cells are input to the input buffers 11 _{1 to} 11 _m , the destination information of the cells is extracted from the header information of the cells and transmitted to the control unit 15 via the signal lines 16 _{1 to} 16 _m . Control unit 15 recognizes the destination of cells stored in the input buffer 11 ₁ to 11 _m, to transmit the read signal to the input buffer 11 ₁ to 11 _m via a signal line 17 ₁ to 17 _m. The input buffers 11 ₁ to ₁ 1 to which this read signal is transmitted
1 _m sequentially reads cells according to this read signal.
The output buffer 13 ₁ -corresponding to the destination of the read cell
13 _n writes the cell transferred from the multiplex bus 12 by the write signal transmitted from the control unit 15 via the signal lines 18 ₁ to 18 _n . When cell transfer concentrates from a plurality of input ports I _{1 to} I _m to one output port P ₁ , P ₂ , ..., P _n , or the ATM communication line of the output destination of the output ports P _{1 to} P _n is in a stopped state. Output buffer 13 ₁ to 1
The cell is accumulated in 3 _n and the output is waited for.

However, the output buffers 13 _{1 to} 13 _n filled with the cell storage capacities change their states by the signal lines 19 ₁ to ₁ 1.
The control unit 15 is notified via 9 _n . In response to this, the control unit 15 causes the output buffer 1 that has the cell storage capacity filled.
When cells are read from 3 _{1 to} 13 _n , even if cells are read from the input buffers 11 _{1 to} 11 _m , writing to the output buffers 13 _{1 to} 13 _n is stopped and the cells are discarded. In this specification, cells read from the input buffers 11 _{1 to} 11 _m even though the cell storage capacities of the output buffers 13 _{1 to} 13 _n have no free space are called surplus cells.

[0005]

In order to prevent cell discard in such a conventional device, there is no other measure than increasing the capacity of the output buffer corresponding to the output port.

However, even when the number of accumulated cells temporarily concentrates on a specific output port for a long period, it is necessary to always prepare a buffer capacity commensurate with the number of cells, resulting in a large hardware configuration. . In addition, the utilization efficiency of the buffer is poor.

The present invention has been made against such a background, and an object thereof is to provide an ATM cell switch system with a small hardware loss and a small cell loss.

[0008]

According to the present invention, an input port to which a cell of an ATM communication line arrives, an input buffer provided for each input port for temporarily storing an input cell, and a cell for each destination are transferred. And an output buffer which is provided for each output port and temporarily stores cells output to the ATM communication line.

Here, the feature of the present invention resides in that the output buffer filled with the cell storage capacity is further provided with a common buffer for temporarily saving the surplus cells sent from the input buffer.

The means for transferring cells for each destination is preferably a multiplex bus in which a plurality of input buffers and a plurality of output buffers are commonly connected.

It is desirable that the common buffer is a memory means that is written in the order of arrival and is read according to control regardless of the order of arrival.

It is desirable to provide a means for managing the surplus cells based on the header information of the surplus cells temporarily stored in the common buffer.

[0013]

The surplus cells sent from the input buffer are temporarily stored in the common buffer with respect to the output buffer whose cell storage capacity is filled. When the output buffer becomes empty, the cells stored in the common buffer and addressed to the output buffer are preferentially read from the common buffer and transferred to the output buffer. That is, the cell loss is reduced by temporarily saving the cells having no destination. In the memory of the common buffer, writing is performed according to the cell arrival order, but when reading, it is read randomly regardless of the writing order.

As a result, it is possible to realize an ATM cell switch which does not require a redundant buffer capacity, has a small hardware configuration, and has a small cell loss.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

According to the present invention, the input ports I _{1 to} I _{m to} which cells of the ATM communication line arrive and the input ports I _{1 to} I _{m are provided.}
The input buffers 11 _{1 to} 11 _m provided for each of the cells to temporarily store the input cells, the multiplex bus 12 for transferring the cells of each destination, and the ATM communication lines provided for each of the output ports P _{1 to} P _n The ATM cell switch includes output buffers 13 _{1 to} 13 _n for temporarily storing output cells.

The feature of the present invention is that the surplus cells sent from the input buffers 11 _{1 to} 11 _m are temporarily saved to the output buffers 13 _{1 to} 13 _n filled with the cell storage capacity. It is provided with a common buffer 14.

Next, the configuration of the common buffer 14 will be described with reference to FIG. FIG. 2 is a block diagram of the common buffer 14. In the memory 4 of the common buffer 14, writing is performed according to the cell arrival order, but when reading, it is read randomly regardless of the writing order.
The read signal is transmitted from the control unit 15 via the signal line 17 _{m + 1} . Further, the write signal is transmitted from the control unit 15 via the signal line 18 _{m + 1} .

Next, the operation of the apparatus of the present invention will be described with reference to FIG. FIG. 3 is a flowchart showing the operation of the control unit 15. Specific output buffers 13 ₁ , 13 ₂ ,
_If the cell storage capacity of 13 _n is satisfied, the control unit 15
Transfers the surplus cells further sent to the output buffers 13 ₁ , 13 ₂ , ..., 13 _n to the common buffer 14 and creates a header list (S1). The common buffer 14 writes this cell into the memory 4 by a write signal transmitted via the signal line 18 _{m + 1} .

The control unit 15 manages which input ports I _{1 to} I _m are written in which order with respect to the surplus cells stored in the common buffer 14, and the specific input ports I ₁ to I _m.
Cell transfer from the common buffer 14 to the output buffers 13 _{1 to} 13 _n is performed so as not to change the order of cells for I _m and the specific output ports P _{1 to} P _n . This transfer control is
This is performed by the read signal transmitted from the control unit 15 via the signal line 17 _{m + 1} .

The control section 15 includes output buffers 13 _{1 to} 13
The occurrence state of _n vacant spaces is monitored (S2). When the output buffers 13 _{1 to} 13 _n have available capacity, it is searched from the list whether or not the surplus cells addressed to the output buffers 13 _{1 to} 13 _n are accumulated in the common buffer 14 (S
3) If stored, the surplus cells are preferentially read regardless of the writing order (S4). The header information of the read surplus cells is deleted from the header list to recreate the header list (S5).

Write / read control circuit 2 of common buffer 14
Inputs the read signals of the input buffers 11 _{1 to} 11 _{m and} the write signals of the output buffers 13 _{1 to} 13 _n from the control unit 15 via the signal lines 17 _{m + 1} and 18 _{m + 1} . Input buffer 1 by a write signal input from signal line 18 _{m +} 1
The surplus cells read from 1 _{1 to} 11 _m are stored in the common buffer 1
Write to 4. The surplus cells are read out to the output buffers 13 _{1 to} 13 _n in which a vacant capacity has been generated by the read signal input from the signal line 17 _{m + 1} . Reading is performed randomly regardless of the writing order.

[0023]

As described above, according to the present invention, an AT having a small cell configuration and a small cell loss can be realized.
An M cell switch can be realized. The use efficiency of the buffer is improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a common buffer.

FIG. 3 is a flowchart showing the operation of the control unit.

FIG. 4 is a block diagram of a conventional device.

[Explanation of symbols]

2 write / read control circuit 4 memory 11 _{1 to} 11 _m input buffer 12 multiplex bus 13 _{1 to} 13 _n output buffer 14 common buffer 15 control unit 16 _{1 to} 16 _m , 17 _{1 to} 17 _m , 18 ₁ to 18 _n , 1
9 ₁ ~ 19 _n signal lines I ₁ ~I _m input ports P ₁ to P _n output ports

Claims (4)

[Claims] 1. An input port to which a cell of an ATM communication line arrives, an input buffer provided for each input port for temporarily storing an input cell, means for transferring the cell for each destination, and each output port. ATMs provided respectively
In an ATM cell switch equipped with an output buffer for temporarily storing cells output to a communication line, a common buffer for temporarily saving surplus cells sent from the input buffer to an output buffer with a cell storage capacity filled An ATM cell switch characterized by comprising: 2. The ATM cell switch according to claim 1, wherein the means for transferring a cell for each destination is a multiplex bus in which a plurality of input buffers and a plurality of output buffers are commonly connected. 3. The ATM cell switch according to claim 1, wherein said common buffer is a memory means which is written in the order of arrival and is read according to control regardless of the order of arrival. 4. The ATM cell switch according to claim 1, further comprising means for managing the surplus cell based on header information of the surplus cell temporarily stored in the common buffer.