JPH0426249A - Common cell buffer type switch - Google Patents

Abstract

PURPOSE:To suppress the capacity of a RAM in a common cell buffer part to be small, as well by preferentially outputting a distributed cell while suppressing the capacity of a cell storage address control part to be small, and speedily turning the distributed cell storage address to an dile address. CONSTITUTION:A cell storage address control means is divided into the general cells, which are connected at the ratio 1:1, and distributed cells which are connected at the ratio 1:N, and a general cell storage address control means 11 and a distributed cell storage address control means 12 are provided. Then, a distributing destination identifier control means 13 is provided to control the distributing destination identifier indicating the N output ports 2 distributedly connected in the distributed cells. When the distributed cells are stored in a common cell buffer 32, the distributed cell storage address of the cell is preferentially supplied to the common cell buffer 32, and the distributed cells are outputted. After outputting the distributed cells to all the output ports to be connected, the distributed cell storage address is moved from the distributed cell storage address control means 12 to an idle address control means 10. Thus, the capacity of the RAM in the common cell buffer part can be suppressed to be small, as well.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a common cell buffer type switch that develops a distribution connection function, and is applicable to a switch device or a cell multiplexing device using an asynchronous transfer mode. The present invention relates to a common cell buffer type switch, and particularly to a common cell buffer type switch having an l-to-N distribution connection function that allows efficient use of memory and has a plurality of output ports for one input port.

[Conventional technology]

FIG. 3 shows the structure of the cell. A cell is composed of a header area 60 and an information area 61, and the header area 60 always contains information indicating the cell type (general cell, distribution cell, etc.) and the input/output connection relationship of the switch.

FIG. 4 shows an example of a conventional common buffer type switch.

30 is a block dividing section, 31 is a header reading section, 32
33 is a common cell buffer, 33 is a write address control unit,
34 is a cell storage address, 35 is a cell storage address writing section, 36 is a cell storage address reading section, 37-L
37-2, 37-3 is an address adder, 38 is a block combiner, rl, r2. r3. r4 is RAM memory, f
7, f8. f9. flO is FIFO memory, if~i4
is the input port, 1cl-ic4 is the input cell, ol-o4
output ports Oc1 to oc4 indicate output cells, ibl
~ib4 is a set of the first to fourth blocks, obl~ob4
indicates a set of the first to fourth blocks.

The number of input ports and the number of output ports are equal, input ports 4,
At the output port 4, cells i c 1 - i c 4 are sent to the block dividing unit 3 at the same time from each input port iI to i4.
It is input to 0. Therefore, in FIG. 4, it is divided into four parts. The first, second, third, and fourth blocks from the beginning of the cell are respectively 10+, 10t, 10s, in the case of input cell icl.
104, and the time of each block is t, (i==0.1
, 2, 3. j=0.1.2.3). The unit of time is 1 block of time, and in principle, the input/output ports of each part are port 1 from top to bottom in Figure 4. 2. 3.
Set it to 4.

FIG. 5 shows the configuration of the block dividing section 30. In Figure 5, the input ports are 1. from the top. 2. 3. 4, and the output ports are 4. from the top. 3. 2. Set to 1. 4
I is a barrel shifter, and in FIG. 5, barrel shifter 41
This figure shows changes in the connection relationship between input ports and output ports over one cycle. The connection relationship goes through one cycle every four blocks, and is shown in FIGS. 5(a), (b), (c), and (d) in chronological order. 40-
1 to 40-3 respectively! , is a delay circuit that provides a delay of 2.3 blocks. Input cell ic2. with reference to input cell icl. ic3. IC4 is delayed by a delay circuit, input cell IC2 is delayed by one block by delay circuit 40-1, input cell IC3 is delayed by two blocks by delay circuit 40-2, and input cell IC4 is delayed by three blocks by delay circuit 40-3. After that, each block of each cell is transferred to the block dividing section 30 by the barrel shifter 41.
output to output ports 1, 2.3.4.

For example, when the first block 10+ of the input cell ic2 is #t3. Therefore, the first block 20 of IC2 is outputted to the output port l of the block division unit 30 at time tl+, one block later than that, and the second block 20. is time t,! is output to the output port 2 of the block dividing section 30, and the third block 20. is time t1
The fourth block 204 is output to the output port 3 of the block dividing section 30 at time t14, and the fourth block 204 is output to the output port 4 of the block dividing section 30 at time t14.

Therefore, to the output ports 1 to 4 of the block division unit 30, ib4 from ibl of the set of the first to fourth blocks of cells input from each input port at the same time is outputted with a time difference of one block. .

The common cell buffer section 32 in FIG. 4 is composed of four rl-r4 RAM memories, the same number as the number of block divisions, and each has a first block, a second block, a third block,
The fourth block is stored.

The write address control section 33 is the common cell buffer section 32
All addresses (0, 1, 2...
・It is composed of a cyclic counter whose period is -n), and counts up by 1 every block time. The value of this counter is simultaneously given to the RAM memories r1 to r4 constituting the common cell buffer section 32 as a write address in the RAM memory. For example, at a certain time τ, ib
Block 40 in i. is input to the common cell buffer section 32, and at that time the write address! If address “23” is given from the control unit 33, the RAM memory rl
to address “23” of r4, respectively block 40
+, 30t, 20t.

104 is written. As for the blocks 101 to 104 that constitute the input cell ICL, RA is applied at time (τ-3).
The first block IL of the input cell icl is written to the address "20" of the M memory r1, and at time (τ-2) the RA
The second block 10. is stored at address "21" of M memory r2.
is written, and at time (τ-1), the third block 10. is written to address "22" of RAM memory r3. is written,
At time τ, the fourth
Block 104 is written.

That is, the first block of input cells is the RAM memory rl.
If the second and third
, the fourth block is written to address "a+1" of RAM memory r2, address "a+2" of r3, and address "a+3" of r4, respectively. On the other hand, the address of the RAM memory r1 into which the first block has been written is sent to the cell storage address management section 34, and the cell storage address writing section 35 uses the output port number read from the first block by the header reading section 31 to write the address to the corresponding FIF. ○ Sorted into memory and stored.

f7. of the cell storage address management unit 34. f8. f9,fl
O is respectively output) ol, o2. .

3.04 FrFO memory for address storage is shown. Therefore, if the input cell icl is output to the output port 03, the address "20" of the RAM memory r1 into which the first block 101 has been written is stored in the FIFO memory f9 of the cell storage address management section 34.

The read address from the common cell buffer unit 32 is given from the cell storage address read unit 36. The cell storage address reading unit 36 is a FIFO memory f7 to flo.
Addresses are read out periodically one block at a time in this order. When the read address is a'', the first block is read from the address “a” of the RAM memory r1 of the common cell buffer 32. After one block time, the address “a” is incremented by 1 in the address adder 37-1. and the address “a+!” of RAM memory r2 is The second block is read out from ". Further, after one block time, the address "a+1" is incremented by 1 in the address adder 37-2, and the third block is read out from the address "1a+2" of the RAM memory r3. Finally, after l block time, the address "a+2' is incremented by 1 in the address adder 37-3, and the fourth address is added from address "a+3" of the RAM memory r4.
The block is read.

In FIG. 4, if address "22" is read from the FIFO memory f8 at time tll, the RA
First block 30 from address “22” of M memory r1
1 is read out, the second block 30. is read out from address "23' of RAM memory r2 at time 111, and the third block 30. is read out from address "24'" of RAM memory r3 at time t.
Block 30 is read out from RAM at time M t .
Fourth block 304 from address “25” of memory r4
is read out.

Therefore, the first, second, third, and fourth blocks constituting a certain cell are outputted to output ports 1 to 4 of the common cell buffer unit 32 with a delay of one block time, respectively, and The block set obl-ob4 is input to the block combiner 38. FIG. 5 shows the block connecting section 38.
The configuration is shown below.

The input ports are 1.2.3.4 from the top, and the output ports are 4.3.2.1 from the top.

Similarly to the block dividing unit 30, a barrel shifter 41 and a delay circuit 50- which provides a delay of 3.2 blocks, respectively.
1 to 50-3. Each block is connected to the corresponding output port by the barrel shifter 4I, and the first to
The fourth block is combined and returned to the cell form, and the delay circuits 50-1 to 50-3 match the leading times of the cells, which are shifted between the output ports, and output them to the output ports. The delay circuits 50-1 to 50-3 may not be provided, in which case the leading time is shifted by one block time and output to the output port.

Writing to and reading from the RAM memory is performed once every l block time.

In this way, a switching operation from an arbitrary input port to an arbitrary output port is performed using the common cell buffer 32.

Cells that are connected one-to-N (hereinafter referred to as "distributed cells"). Cells that are connected one-to-one are referred to as "general cells". The types of general cells and distributed cells are determined by information written in the header area of the cell. ) is input, the cell is stored in the common cell buffer 32 as described above, but the address of the RAM memory r1 that stores the cell is sent to the cell storage address management unit 34, and the header is The reading section 31 reads out the first block of cells and stores them in all the corresponding FIFO memories according to the destination output port number.

Input cell IC2 in FIG. 4 is an output port.

1.02.04, the storage address "21" in the RAM memory r1 of the common cell buffer 32 of the input cell ic2 is stored in the FIFO memory f7° f8. stored in flO. The cell read operation is realized in the same manner as in the case of 1-to-1 connection.

[Problem to be solved by the invention]

However, in the conventional method of connecting multiple cells in a 1:N ratio using a common cell buffer type switch, addresses are stored in the FIFO memory of all cell storage address management units 34 corresponding to N output ports, so the storage area is limited to 1. It is necessary for each cell to correspond to the number of connected output ports, and as the number of distributed cells increases, the area for storing storage addresses of general cells becomes compressed.

To avoid being overwhelmed, a large amount of storage memory is required.

In addition, the time required for the distributed cell storage address from the time it is written (h) to the time it is read out differs depending on the number of addresses stored in the cell storage address management FIF○ memory corresponding to each output port, so each port The timing at which the same distribution cell is output is not constant, and the output is completed,
There is a problem in that the RAM memory of the common cell buffer unit 32 needs to have a large capacity so that the storage address of the distributed cell is not used as a storage address of another cell until it becomes a free address. In particular, if there are cells that take a long time to read when priorities are set between output ports, a considerable amount of memory is required.

The present invention has been made in view of the above points, and by reducing the capacity of the cell storage address management section, outputting distributed cells with priority, and quickly making the distributed cell storage address a free address, the RAM of the common cell buffer section can be reduced. An object of the present invention is to provide a common cell buffer type switch having a distribution connection function with a small capacity.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. Free address management means IO, which includes an input port, an output port, and a common buffer 32, and manages free addresses of the common cell buffer 32 in which cells input from the input ports are to be stored, and the common cell buffer 32 in which cells are stored. cell storage address management means for managing the addresses of the common cell buffer 32 given by the free address management means 10, cells inputted from the input port are stored in the free addresses of the common cell buffer 32 given by the free address management means 10, and the common address given by the cell storage address management means 10 is In a common cell buffer type switch that performs a switching operation between input and output ports by reading cells from the address of the cell buffer 32 and supplying them to a predetermined output port, the cell storage address management means is divided into l pairs! 1:N with the general cell to be connected
A general cell storage address management means 11 for the general cell and a distribution cell storage address management means 12 for the distribution cell are separated from those related to the distribution cell to be connected. A distribution destination identifier management means 13 is provided for managing distribution destination identifiers indicating N output ports 2 to be distributed, and when the distribution cell is stored in the common cell buffer 32, priority is given to the distribution cell storage address of the cell. After the distribution cell is outputted to all the output ports to which the distribution cell is to be connected, the distribution cell storage address is sent from the distribution cell storage address management means 12 to the distribution cell storage address management means 12. A common cell buffer type switch characterized in that distribution connections are made by transferring vacant addresses to a vacant address management means 10.

[Effect]

In the present invention, distributed cell storage addresses are managed separately from general cell storage addresses, and even if the number of connected output ports is plural, they are not stored in areas other than the 1 storage area. Furthermore, since the distribution cell connection process is performed by interrupting the general cell connection process, it is possible to quickly make the storage address a vacant address.

〔Example〕

FIG. 2 shows an embodiment of the invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. Reference numeral 10 denotes a free address management unit that manages free addresses in the common cell buffer and supplies the common cell buffer 32 with an address for writing an input cell.

fO is a FIFO memory that stores free addresses in the free address management unit IO.

Reference numeral 11 denotes a general cell storage address management section, which stores and manages storage addresses of input general cells in the common cell buffer 32 in correspondence with connection output ports.

fl to f4 are FIF memories that store general cell storage addresses of the common cell buffer section 32 in correspondence with the respective output ports 1 to 4 in the general cell storage address management section 11.

Reference numeral 12 denotes a distribution cell storage address management unit, which commonly manages storage addresses of input distribution cells in the common cell buffer 32 regardless of the connection output port. f5 is an FIF that stores the distribution cell storage address of the common cell buffer 32.
- It is a memory, and the read signal and read pointer movement signal can be supplied independently, and the data read by the read signal is the same until the read pointer movement signal is applied.

13 is a distribution destination identifier management unit that manages distribution destination identifiers indicating connection output ports of distribution cells, and f6 is a FIFO that stores distribution destination identifiers in the distribution destination identifier management unit I3.
It's memory.

14 is a cell storage address write control section, and 15 is a cell storage address read am section.

16-1 to 16-4 are write address registers, 17
-1 to 17-4 are read address registers.

First, the operations of writing cells into the common cell buffer 32 and reading cells from the common cell buffer 32 will be described. The write address of the input cell is given by the free address management unit lO, and is written in the write address register 16-
It is held at 1 and supplied to the RAM memory rl, where the first block of cells is stored. After one block time, the write address is shifted from the write address register 16-2 to 16-2 and held, and the same ATOS is supplied to the RAM memory r2 to store the second block. R.A.
M memory r3. Similarly, for r4, the third and fourth blocks are written at the same address! be done.

The cell read address from the common cell buffer 32 is supplied from the general cell storage address management section 11 or the distributed cell storage address management section 12, held in the successive address register 17-1, and supplied to the RAM memory r1 to read the output cell. The first block is read. After one block time, read address register 17-■ to l7
The read address is shifted to -2 and held, the same address is supplied to the RAM memory r2, and the second block is read out. RAM memory r3. Similarly, the same address is supplied to r4, and the third and fourth blocks are read out.

The above write and read operations are performed once every l block time. Further, the write address register 16 and the read address register 17 described above can be realized by the same address register.

Next, descriptions of cell write operations to the common cell buffer 32 and cell read operations from the common cell buffer 32 will be omitted, and operations related to cell storage address management will be described. The number of input ports and the number of output ports may be any number. In the embodiment, a case is shown in which the number of input ports is 4 and the number of output ports is 4.

A general cell is connected from any one input port to any one output port, and a distribution cell is connected from any one input port to any plurality of output ports. The type of general cell/distribution cell and the connection relationship between the outgoing ports can be obtained from the information in the header area 60 of the cell.

It is assumed that the address "3.24.20..." is stored from the beginning of the FIFO memory fO of the free address management unit 10.It is assumed that the input cell icl is a general cell connected to the output port 03.The input cell The header area of iel is read by the header reading section 37 and given to the cell storage address write control section 14, where it is recognized that it is a general cell connected to the output port 03. “3” is given R
Input cell ie to address “3” of AM memories r1 to r4
The first to fourth blocks 101 to 104 of 1 are stored. Based on the recognition information from the header area mentioned above, a storage command is output to the FIFO memory IJ f 3 corresponding to the output port 03 of the general cell storage address management section 11, and the address "3" is stored. The general cell is output by reading the cell from the address of the common cell buffer section 32 read out from the general cell storage address management section 11 to the cell storage address readout control section 15 and outputting it to the corresponding output port.

If the distributed cell is not stored in the common cell buffer section 32, the general cell storage address management section 1! is sent from the cell storage address readout control section 15! FIFO memory fl-f4
Address read commands are output in order. The read address is given to the common cell buffer section 32, and the cell stored at that address is read out, and outputted to the output port by the block coupling section 38 according to instructions from the cell storage address readout control section 15. .

Further, when the output ports of to 04 are regularly circulated in order, the block coupling unit 38 does not need to issue any instructions from the cell storage address readout control unit 15 as long as it operates synchronously, and If the address is not stored in the FIFO memory, nothing is executed. Since the address of the common cell buffer that outputs the cell becomes a free address after one output, its management is transferred from the general cell storage address management section 11 to the free address management section 10.

Next, input cell ic2 is assumed to be a distribution cell connected to output ports O1, 02, and o4. The header area of the input cell IC2 is read out by the header reading unit 31 and given to the cell storage address write control unit 14, where the output port o
It is recognized that it is a distribution cell connected to 1, o2.04. "24" is given as the cell storage address from the PIFO memory fO, and the first to fourth blocks 201 of the input cell IC2 are stored at address "24" of the RAM memories r1 to r4.
204 are stored. F of the distribution cell storage address management unit 12 based on the recognition information from the header area mentioned above.
A storage command is output to the IFO memory f5 and the address “2” is
4" are stored and the distribution destination identifiers indicating the output ports o1, o2, o4 are stored in the FIFO of the distribution destination identifier management unit 13.
It is stored in memory f6.

Here, an example of a distribution destination identifier is shown. The distribution destination identifier is composed of 4 bits, and each bit is made to correspond to each output port, and the bit corresponding to the output port to be connected is set to "1", and the bit not corresponding to the connected output port is set to "0".

Therefore, when indicating output ports 01 and o2.04, the bits of output port o3 do not correspond, so “1101
". In FIG. 2, the bits corresponding to output caps ()of, o2, o3.04 from the top of the FIFO memory f6 are shown.

The output of the cell is to read the cell from the address of the common cell buffer unit 32 read from the distributed cell storage address management unit 2 in accordance with the read command from the cell storage address readout control unit 5, and output it to the corresponding output port. This is done by

When the distribution cell is stored in the common cell buffer 32, the distribution destination identifier corresponding to the cell is read from the distribution destination identifier management section 13 to the cell storage address readout control section 15, and the cell storage address readout control section 15 reads out the distribution destination identifier corresponding to the cell. It is determined whether the FIFO memory of the general cell storage address management unit 11 that is about to output an address read command corresponds to the output port of the distributed cell by referring to its distribution destination identifier, and if it is not the distributed cell output port, As described above, a general cell is output, and in the case of a distributed cell output port, an address read command is output to the distributed cell storage address management unit 12 instead of the general cell storage address management unit II, and the distributed cell is output.

The distributed cell storage address differs from the general cell storage address in that it does not become an empty address with a 1@ read operation, but becomes an empty address after cells are output to all output ports to be connected. Therefore, it is determined by the following method that the distribution cells have been output to all corresponding output ports.

In the first method, each time a distribution cell is output to one output port, the corresponding bit of the distribution destination identifier is set to 0, and when all bits become 0, it is determined that the address is empty.

The second method utilizes the fact that distribution cells are output with priority over general cells.
It is determined that if connection processing is performed in - ways for all output ports regardless of whether or not there is an output from the distribution cell, the address becomes a vacant address.

When it is determined that the distributed cell storage address has become a vacant address as described above, the management of the address is transferred from the distributed cell storage address management section 12 to the vacant address management section 10.

Next, a specific example will be shown. The distribution cells connected to the output ports ol and o3゜04 are waiting for output, and their storage address is set to "4", and the cell storage address read control unit 15
Assume that the user is trying to output an address read command to the FIFO memory f1 corresponding to output port 1. The cell storage address read control unit 15 is the distribution destination identifier management unit 1
Output port 0 due to distribution destination identifier “1011” from 3.
1 is the distribution cell output port, and outputs an address read command to the distribution cell storage address management section 12 instead of the FIFO memory fl of the general cell storage address management section 11. According to this command, the address "4" is read out from the distributed cell storage address management section 12 to the cell storage address readout control section 15, applied to the common cell buffer 32, and outputted to the output port 01 by the block combination section 38.

Next, the cell storage address read control unit 15 checks whether the output port 02 is a distribution cell connection port, and since it is not a connection port, the general cell storage address management unit 11
An address read command is output to the FIFO memory f2 of the FIFO memory f2, and the address "l" is read out from the output port as described above. 2, the cell storage address readout control unit 15 repeats the same operation in the order of output ports o3 and o4, and since each is an output port of a distribution cell, it is processed in the same way as the output port of, and the output port 03,
A distribution cell is output to o4.

The first method is to determine whether the address is free or not by setting the distribution destination identifier to “1” after outputting a cell to the output port of.
011" to "0011", and the same goes on to the output port. After outputting the cell to 3, change it to "000work", and after outputting the cell to output port 04, change it to "000o", and at this point change the distribution destination. Since all bits of the identifier become "0", it is determined that the address is empty.

The address “4” that has become a vacant address is stored in the vacant address management unit 10 and is stored in the distribution cell storage address management unit 12.
, and the management is transferred to the free address management section 10.

Also, FIFO memories f5 and f6 have the same write and read operations, so they are configured as one FIFO memory, and one word is divided into a distribution cell storage address (f5 area) and a distribution destination identifier area (f6 area)). May be used separately.

In addition, in the above embodiment, in the common buffer type switch, addresses are used cyclically, so if an error occurs in the address, the erroneous address will remain permanently, causing an abnormality in the switch operation. Storage address is output port or cell type (general cell/distribution cell)
Because it is managed by different FIFO memories,
Regarding the detection, discarding, and repair of error addresses, the patent application law "Method for Detecting Address Errors in Data Storage Devices" (Japanese Patent Application No. 1-231699) and "Common Buffer Type Switch" have already been proposed.
(Japanese Patent Application No. 1-261505) can be applied.

Therefore, it is not necessary to increase the number of distributed cells and compress the storage addresses of the general cells or to use a large capacity memory, and it is possible to judge when an address becomes free, so the common cell buffer 32 It is easy to secure free space.

〔Effect of the invention〕

As described above, according to the present invention, in order to manage distributed cell storage addresses separately from general cell storage addresses, the cell storage address management section is used to store storage addresses in only one storage area regardless of the number of connection output ports. The amount of memory to be configured can be reduced, and even if distribution cells are input intensively, the storage address storage area of the general cells will not be overwhelmed. In addition, since connection processing of distributed cells is performed by interrupting connection processing of general cells, it is possible to quickly make the storage address free. The capacity of the RAM in the buffer section can also be kept small, which is useful for improving the performance of the device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing the structure of a cell, and FIG. 4 is an example of a conventional common buffer type switch. FIG. 5 is a diagram showing the configuration of the block dividing section, and FIG. 6 is a diagram showing the configuration of the block combining section. IO...Free address management unit, II...-General cell storage address management unit, 12...Distribution cell storage address management unit, I3...Distribution destination identifier management unit, 14...Cell storage address writing Control unit, 15... Cell storage address readout control unit, 32... Common cell buffer, 3
4... Cell storage address management section, 35... Cell storage address writing section, 36... Cell storage address reading section, 37-1 to 37-3... Address addition section, 3
8 block joint. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Scope of Claims] Free address management means comprising an input port, an output port, and a common buffer, and managing free addresses of the common cell buffer in which cells input from the input port are to be stored;
cell storage address management means for managing the address of the common cell buffer where the cell is stored; the cell storage address management means stores the cell input from the input port at the free address of the common cell buffer given by the free address management means; In a common cell buffer type switch that performs a switching operation between input and output ports by reading cells from the address of the common cell buffer given by the management means and supplying them to a predetermined output port, the cell storage address management means is one-to-one. It is separated into a general cell to be connected and a distribution cell to be connected 1:N, and includes a general cell storage address management means for the general cell and a distribution cell storage address management means for the distribution cell, The distribution cell is provided with a distribution destination identifier management means for managing distribution destination identifiers indicating N output ports to be distributed and connected, and when the distribution cell is stored in the common cell buffer, the distribution cell storage address of that cell is provided. is given priority to the reading common cell buffer, the distributed cell is outputted, and after the distributed cell is output to all output ports to which the distributed cell is to be connected, the distributed cell storage address is sent from the distributed cell storage address management means. A common cell buffer type switch characterized in that distribution connections are made by moving the vacant addresses to the vacant address management means.