JP2964958B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch used in an asynchronous transfer mode (ATM) communication method, and more particularly to a memory address management for a shared buffer type ATM switch.

[0002]

2. Description of the Related Art A conventional ATM switch will be described with reference to the following known documents. (1) Japanese Patent Application Laid-Open No. 03-001633
P3 line 14 to P4 line 2, drawings Fig. 1 and Fig. 2 (2) Ozaki et al. "Study on switching control of common buffer ATM switch", IEICE Technical Report SSE92-127, pp.1
3-18, 1993 Explanation page P14 lines 31-43, drawing Figure 1 (3) Kenneth J. Schultz et al, “CAM-Based Single
-Chip Shared Buffer ATM Swich ", ICC'94, pp.1190-119
5,1994 Explanation Page P1190-P1193 Section 3, Drawing Fig.2

The ATM switch generally has a cell buffer memory for storing cells, and several types of ATM switches have been proposed depending on the arrangement of the cell buffer memory. Among them, all output ports of the switch are logical output queues (FI) on a single memory.
FO), and there is a shared buffer type ATM switch that uses a memory space shared between output ports (Reference (2)).

A shared buffer type ATM switch logically divides an address space of a memory to form a plurality of FIFO queues. The maximum length of each FIFO queue is the sum of all FIFO queue lengths. Can be accommodated within a range not exceeding the address space of the memory, and the memory can be used effectively. Furthermore, FIFO
Even when the queue is composed of smaller units, for example, the output port is further divided into a plurality of service classes, and the output priority control is performed between the service classes, the memory can be effectively used. it can.

In general, a shared buffer type ATM switch has a cell multiplexing unit 10 for multiplexing cells 81 of each input port and a cell buffer memory 11 for storing cell multiplexed cell data 84, as shown in FIG. And a memory control unit 9 for controlling the cell buffer memory 11, and the cell data 87 from the cell buffer memory 11 to the cells 88 for each output port.
And a cell separation unit 8 for separating the cells. The clock 82 and the cell clock 83 are provided to the cell multiplexing unit 10, the memory control unit 9, and the cell separation unit 8.

The memory control unit 9 is an address management unit that constructs a logical FIFO queue in the address space of the cell buffer memory based on the output control signal 85 from the cell multiplexing unit 10. A logical FIFO queue is constructed by a method of expressing a chain (output order) of memory addresses constituting the FIFO in a linked list format (pointer indicates the next data storage address by a pointer). There is a method of storing the address data itself in a separate FIFO memory, and a method of using a CAM (associative memory) having the same size as the address space of the cell buffer memory (references (1) and (3)).

Among them, a memory control unit 9 using a CAM
FIG. 6 is a block diagram of an example of the configuration, and FIG. 7 is a timing chart of a representative signal of the memory control unit 9. In the method using the CAM, a bit indicating use / non-use, a number for identifying a FIFO, and a sequence number indicating an order in the FIFO are stored in a data area of the CAM (references (1) and (3)). )).

First, when storing (writing) the cell data 84 (when setting the cell buffer memory W / R control signal 95 in FIG. 7 to W), an unused address of the CAM 13 is searched to obtain an address (FIG. 7). S = Search area of the CAM control signal 92 and WA of the cell buffer memory Write / Read address 94), the cell data 84 is stored in the cell buffer memory 11 indicated by the address, and bits used in the data area of the CAM 13 The FIFO number and the sequence number are stored (U = Update area of the CAM control signal 92 in FIG. 7).

The CAM control circuit unit 12 manages the start and end of the sequence number for each FIFO. When the cell data 87 is read from the cell buffer memory 11, the bits used, the FIFO number and the start sequence are used. CAM number
Given as data 91, the CAM 13 is searched to find the corresponding address (S = Sea of the CAM control signal 92 in FIG. 7).
RA of rch area and cell buffer memory Write / Read address 94. The address 94 is provided to the cell buffer memory 11 via the latch circuit 14. After reading, the address is returned as the address 93, and the data of the CAM is rewritten as unused (U = Upda of the CAM control signal 92 in FIG. 7).
te area).

As described above, when writing to and reading from the cell buffer memory 11, the CAM 13
Access twice (one search and one update),
It is necessary to make a total of four accesses to one cell.

The method of using a CAM as a memory control unit can change the number of output ports and the number of service classes relatively easily by rewriting the contents written in the CAM, for example, a FIFO number. This is an advantageous implementation. In addition, since the free address can be expressed only by the used / unused bits, there is an advantage that a free address storage FIFO (a linked list format memory) which is required in a linked list format or the like is not required (see Document (1)). 3)).

[0012]

The problem with the conventional memory management technique using the CAM of the shared buffer type ATM switch described above is that the throughput (maximum processing speed) of the ATM switch that can be realized is different. This is lower than other memory management methods such as FIFO. The reason for this is that the CA for searching the address is used both when writing to and reading from the cell buffer memory.
Since search of M and update of CAM are necessary, at least four times of CAM access is required in one cell processing.
This is because a cell having a time shorter than this number of accesses times the access time (CAM search time, write / read time) cannot be processed. Generally, the CAM search time is R
This is because it is longer than the access time of AM.

Accordingly, an object of the present invention is to provide an ATM switch having a high throughput (maximum processing speed) in a configuration in which a CAM is used as a memory control section of a shared buffer type ATM switch.

[0014]

In order to achieve the above object, the present invention has a plurality of input / output ports, multiplexes ATM cells from each input port, and multiplexes the ATM cells. The cell data is stored in a first storage means common to each input / output port, and the stored cell data is read out from the first storage means and separated for each output port. A
The TM switch stores the use state of the address of the first storage means, the output port number of the written cell data, and the sequence number indicating the reading order for each output port. The empty addresses of the first storage means are searched by comparing the contents of the two second storage means with the respective stored contents of the two second storage means, and at the same time, the cell data from each output port is retrieved. Search the data storage address, and
Control means for controlling the writing and reading of cell data to and from the storage means, and the control means searches for an empty address of the first storage means by checking the storage contents of one of the second storage means. At the same time, the cell data storage address from each output port is searched by comparing the storage contents of the other second storage means, and the cell data writing / reading control to the first storage means is performed. It is characterized by.

In order to achieve the above object, the present invention has a plurality of input / output ports, multiplexes ATM cells from each input port, and outputs multiplexed cell data to each input port. The output is stored in a first storage means common to the output ports.
In the ATM switch in which the stored cell data is read out from the storage means and separated for each output port, the use state of the address of the first storage means and the output of the written cell data are described. By comparing a plurality of second storage means for storing a port number and a sequence number indicating a reading order for each output port with each storage content of the plurality of second storage means, Control means for retrieving an empty address of the first storage means, and at the same time retrieving a cell data storage address from each output port, and performing cell data write / read control to the first storage means. Wherein the second storage means is provided for each of a plurality of service classes, and the control means comprises a cell service of a different service class.
When the data is simultaneously input / output to / from the first storage means,
Each of the second storage means is simultaneously searched to obtain an empty address and a cell data storage address. When cell data of the same service class is input / output to / from the first storage means, the cell data is stored. After searching for a storage address, it is reused as a free address. Further, the size of the second storage means for each service class may be variable.

Further, a block address in units of a plurality of cell data may be defined in the first storage means, and the block address may correspond to an address in the second storage means.

[0017]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram of the memory control unit 9 according to the first embodiment of the present invention, and FIG. 2 is a timing chart showing the operation, showing typical signals of FIG. In FIGS. 1 and 2, the same reference numerals are given to the portions corresponding to FIGS.

In FIG. 1, a read CA is used as the CAM.
M13a and a write CAM 13b are provided, and the latch circuits 14a, 14 and b and the signals 91a to 93a, 91b
b to 93b are provided, and a selection circuit 15 is further provided.

Next, the operation of the above configuration will be described. Read CAM 13a and Write CAM 13 in FIG.
In the data area b, a bit indicating used / unused and a number for identifying the FIFO such as an output port number, etc.
A sequence number indicating the storage order in each FIFO is stored. Basically CAM13a for Read
And the contents of the write CAM 13b are the same. Further, the CAM control unit 12 has respective FIFOs.
Are stored in the first sequence number and the last sequence number.

First, when the cell data 84 is input, it must be stored (written) in the cell buffer memory 11. At this time, the CAM control circuit 12
The output destination of the data 84, that is, the FIFO number to be stored, is obtained from the output control signal 85. Further, the CAM control circuit 12
It instructs the write control CAM 13b to search for an unused address in the CAM. This is the CAM data 91
Only used / unused bits in b are 0 (0 indicates unused)
The search is performed by masking all other bits. The address 93b thus obtained is stored in the latch circuit.
It is latched at 14b and returned to the CAM control circuit 12.

At the next clock 82, the CAM control circuit 12
Sets the W control signal 95 of the cell buffer memory 11 to Write control and switches the selection circuit 15 to output a WA (Write Addres) 93b, and gives this as a write address 94 of the cell buffer memory 11. The cell buffer memory 11 writes the cell data 84 to the corresponding address.
At this time, the CAM control circuit 12 simultaneously writes the CAM for writing.
13b and CAM 13a for Read
Write a value obtained by adding 1 to the FIFO number and the last sequence number. In addition, the CAM control circuit 12
Is stored that the last sequence number has advanced by one.

A preparation operation for reading the cell data 87 from the cell buffer memory 11 is performed in parallel with the write operation. Reading is performed from the FIFO specified by the CAM control circuit 12. CAM control circuit 12 is FI
The FOs are circulated and specified in a predetermined order. First, CAM
The FIFO number designated by the control circuit 12, the last sequence number stored therein, and the used / unused bit = 1
(1 indicates use) as CAM data 91a and read C
Search for AM13a. The address 93a thus obtained
Are latched by the latch circuit 14a and returned to the CAM control circuit 12.

RA (Re) latched by the next clock 82
ad Address) 93a is the selector circuit 15 when the W / R control signal 95 from the CAM control circuit 12 instructs the read control.
And given as an address 94 of the cell buffer memory 11. The cell buffer memory 11 reads out and outputs the cell data 87 at the address 94. At the next clock 82, the used / unused bit is added to the corresponding address of both the read CAM 13a and the write CAM 13b.
Write = 0 and update. That is, in FIG.
U in the AM control signal 92b and the read CAM control signal 92a
In (Update), CAM13a for Write and CAM13 for Read
Update both of b simultaneously.

As described above, by preparing two CAMs and performing a search at the same time, the number of searches can be reduced, and the operation of writing one cell to the cell buffer memory and reading one cell from the cell buffer memory can be performed. Can be realized with three accesses.

FIG. 3 is a block diagram of the memory control unit 9 according to the second embodiment of the present invention. FIG. 4 is a timing chart of typical signals of the memory control unit 9. In FIG. 3, CAMs 13a to 13d for classes 1 to 4 are provided, and accordingly, latch circuits 14a to 14d and respective signals are provided.
91a to 93d and 91b to 91d are provided.

Next, the operation of the above configuration will be described. CAM13a to CAM for classes 1 to 4 in FIG.
In the data area of 13d, a bit indicating used / unused is provided,
A number for identifying a FIFO, such as an output port number, and a sequence number indicating a storage order in each FIFO are stored. Class 1 to Class 4
The FIFO for each output port is divided into service class units, and priority control is performed at the time of reading, thereby realizing a plurality of quality classes related to delay. In addition, 4
The class is an example, and the number of classes is not limited. As an example of general priority control, a low priority class FIFO is
A cell can be read out for the first time without cells stored in the FIFO of a higher priority class.

The addresses of the CAMs 13a to 13d are obtained by dividing the addresses of the cell buffer memory 11 without overlapping. However, CAM13a to CAM13
Each address space of d may be fixed or may be changeable. Dividing the addresses so that they do not match means that they can operate independently. However, in that case, the address space of the cell buffer memory 11 cannot be interchanged between the classes.

The CAM control unit 12 stores the first sequence number and the last sequence number of each FIFO of each class. First, when the cell data 84 is input, it must be stored (written) in the cell buffer memory 11. At this time, the CAM control circuit 12 obtains the output destination of the cell data 84, that is, the class number to be stored and the FIFO number from the output control signal 85.
Further, the CAM control circuit 12 determines the C of the corresponding class number.
An instruction is issued to the AM (for example, 13b) to search for an unused address in the CAM. This is the CAM data 91
Only used / unused bits in b are 0 (0 indicates unused)
The search is performed by masking all other bits.

The address 93b thus obtained is latched by the latch circuit 14b at the next clock, and the CAM
It is returned to the control circuit 12. And at the same time, the corresponding CA
At the address of M, a value obtained by adding 1 to the used / unused bit = 1, the FIFO number, and the last sequence number is written. Further, the CAM control circuit 12 stores the FIFO of the corresponding class number.
Is stored that the last sequence number has advanced by one. The latched address 93b is held until the write cycle of the cell buffer memory. In the write cycle, the CAM control circuit 12 stores the W
Set the control signal 95 to Write control and set the selection circuit 15 to WA.
(Write Addres) 93b is switched to be output, and this is given as a write address 94 of the cell buffer memory 11. The cell buffer memory 11 writes cell data at the corresponding address.

A preparation operation for reading the cell data 87 from the cell buffer memory 11 is performed in parallel with the write operation. Reading is performed from the FIFO of the class number specified by the CAM control circuit 12. The CAM control circuit 12 circulates the output ports in the determined order, performs priority control between the FIFOs of the corresponding output ports in classes 1 to 4, and designates one class number and FIFO number. The CAM control circuit 12 calculates the difference between the last sequence number and the first sequence number of each FIFO, and
The number of storage cells in O is obtained, and priority control is performed.

First, the FIFO number of the class (eg, class 1) designated by the CAM control circuit 12, the last sequence number stored therein, and the used / unused bit = 1
(1 represents use) by the corresponding class 1 CAM data.
The CAM 13a for class 1 is searched as the data 91a. The address 93a thus obtained is latched by the latch circuit 14a and returned to the CAM control circuit 12.

RA (Read A) latched by the next clock
ddress) 93a is selected by the selection circuit 15 and given as an address 94 of the cell buffer memory 11 when the W / R control signal 95 from the CAM control circuit 12 instructs read control. The cell buffer memory 11 stores the address 9
4 is read and output. At the same time, the used / unused bit = 0 is written to the corresponding address of the class 1 CAM 13a and updated.

The above description has been given of the procedure when the read class and the write class are different. However, when the read class and the write class are the same, the above-described search of the CAM for writing is omitted, and the read is performed. Is given as the next write address as it is. For example, if a class 3 cell is input when reading from a class 3 FIFO, an address 93c obtained by searching the class 3 CAM 13c by the leading sequence number in a read operation is written. Assign an address for the cell. The corresponding address is held until the write cycle of the cell buffer memory 11, during which the corresponding address of the CAM 13 c is replaced with the new cell data 84.
Then, a value obtained by adding 1 to the FIFO number and the last sequence number is written and updated. The CAM control circuit 12 stores a value obtained by adding 1 to the leading sequence number of the read FIFO, and stores a value obtained by adding 1 to the last sequence number of the written FIFO.

As described above, a plurality of CAMs whose address spaces do not match each other are prepared and independently searched and updated. In an address space where reading and writing occur simultaneously, a read address is reused as a write address. Thereby, the write and read operations can be performed simultaneously, and the number of CAM searches can be reduced, and the operation of writing one cell in the cell buffer memory and reading one cell from the cell buffer memory can be realized by two accesses. .

[0035]

The first effect of the present invention is that the address search time in the shared buffer type ATM switch can be shortened, thereby increasing the throughput (maximum processing speed) of the ATM switch. it can. Specifically, as shown in the embodiment, a switch having a throughput that is 3/2 to 2 times that of the conventional realization method using the CAM can be realized.

Further, by providing two second storage means for managing addresses and simultaneously searching for a write address and a read address, the number of searches can be reduced.

Further, a plurality of second storage means are provided by dividing the address space so that addresses do not overlap, so that reading and writing processes in different address spaces are parallelized, and reading and writing to the same address space are performed. In the case where the error occurs, the number of searches can be reduced by reusing the read address as the write address.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory control circuit of an ATM switch according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a memory control circuit of an ATM switch according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a block diagram of a conventional general shared buffer type ATM switch.

FIG. 6 is a block diagram of a memory control circuit of a conventional ATM switch.

FIG. 7 is a timing chart showing the operation of a conventional memory control circuit.

[Explanation of symbols]

 Reference Signs List 8 cell separation unit 9 memory control unit 10 cell multiplexing unit 11 cell buffer memory 12 CAM control circuit 13a to 13d CAM 15 selection circuit 81 input cell 84 input cell data 85 output control signal 86 memory control signal 87 output cell data 88 output Cell 91a-91d CM data 92a-92d CAM control signal 93a-93d Address 94 Address 95 Cell buffer memory W / R control signal

Claims (4)

(57) [Claims] An input port having a plurality of input / output ports;
Multiplexed ATM cells from the network and multiplexed cell data
Data in the first storage means common to each input / output port,
In the ATM switch in which the stored cell data is read from the first storage means and separated for each output port, the use state of the address of the first storage means and the written cell data Two second storage means for storing the output port numbers of the data and a sequence number indicating the reading order for each output port; and the storage contents of the two second storage means. To search for an empty address in the first storage means, and at the same time, search for a cell data storage address from each output port, and perform cell data writing / reading control to the first storage means. Control means for performing a search for an empty address of the first storage means by collating the storage contents of one second storage means, and at the same time, the storage contents of the other second storage means. Collate ATM switches and performs data write and read control - searching data storage address, Serude to the first storage means - Serude from bets - each output port by. 2. An input / output port having a plurality of input / output ports.
Multiplexed ATM cells from the network and multiplexed cell data
Data in the first storage means common to each input / output port,
In the ATM switch in which the stored cell data is read from the first storage means and separated for each output port, the use state of the address of the first storage means and the written cell data A plurality of second storage means for storing an output port number of the printer and a sequence number indicating a reading order for each output port; and comparing the respective storage contents of the plurality of second storage means. Control to search for an empty address in the first storage means, and at the same time to search for a cell data storage address from each output port, and to control writing and reading of cell data to and from the first storage means. Means, and the second storage means is provided for each of a plurality of service classes,
When the cell data of different service classes are simultaneously input / output to / from the first storage means, the control means simultaneously searches the respective second storage means and stores the empty address and the cell data storage address. When cell data of the same service class is input / output to / from the first storage means, an ATM is characterized by retrieving a cell data storage address and reusing it as a free address. switch. 3. The ATM switch according to claim 2, wherein the size of said second storage means is variable for each service class. 4. The method according to claim 1, wherein a block address in units of a plurality of cell data is defined in said first storage means, and said block address is made to correspond to an address of said second storage means. 3. The ATM switch according to claim 1 or 2.