JP2937333B2 - Control method of speech path switch - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Actions Embodiment I. Correspondence between embodiment and FIG. 1 II III. Configuration and operation of the first embodiment III. Configuration and operation of the second embodiment Effect of the Invention [Outline] In the ATM communication device, a switch for controlling a communication path switch between each input port and each output port. Regarding the control method, for the purpose of increasing the communication efficiency, the ATM cells supplied to any of the plurality of input ports are stored in the input cell analysis / buffer unit corresponding to each of the input ports, and the stored ATM cells are stored. ATM cell
In a switch control method for transmitting a switch to an output destination extracted from a TM cell through a switch, an input cell analysis / buffer for storing the ATM cell and sequentially transmitting control information including at least a storage location and an output destination of the ATM cell. Units are provided corresponding to the respective input ports, the control information received from the input cell analysis / buffer unit is stored corresponding to a desired output destination, and the stored control information is stored for each output destination. A switch control unit for sequentially selecting the input cell analysis / buffer in a cyclic manner and sequentially transmitting information on a desired input cell analysis / buffer unit and information on the selected output destination to the switch, wherein each of the input cell analysis / buffer units includes: It is configured by reading an ATM cell specified by the control information from the switch control unit.

[Industrial applications]

The present invention relates to a switch control method for controlling a communication path switch between each input port and each output port in an ATM communication device.

[Conventional technology]

In the broadband ISDN, a high-speed fixed-length packet (cell) communication system called Asynchronous Transfer Mode (hereinafter referred to as ATM) has been studied to provide multimedia communication such as voice, image, and high-speed data communication. I have.

ATM supplied to the input port in this ATM communication system
There are the following main methods for performing switching for outputting a cell to a desired output port.

A method of providing a buffer on the output port side (output buffer method).

A method of providing a buffer on the input port side (input buffer method).

A method in which a common memory is provided to access between input ports.

Among these methods, the method has a disadvantage that the buffer capacity is increased, and the method has a disadvantage that it takes a long time to access the common memory from each port. On the other hand, the input buffer method does not have these drawbacks and can be said to be an effective method for realizing an ATM switch.

As shown in FIG. 6A, a buffer (input buffer) for temporarily storing ATM cells is provided in each of the plurality of input ports. The ATM cell via this buffer is output to any of a plurality of output ports via a speech path switch. Also, an input control unit corresponding to each of the plurality of input ports on a one-to-one basis and an output control unit corresponding to each of the plurality of output ports on a one-to-one basis are provided. Control information is exchanged via the.

Hereinafter, an operation when a cell supplied to any input port is output to any output port will be described.

When the ATM cell reaches the input port, the input control unit transmits the input port number to the destination output control unit.

The output port receives the input port number sent at. When input port numbers from a plurality of input control units are received at the same time, one is cyclically selected.

The output control unit, to the received (selected) input control unit, by referring to the reservation table at the corresponding output port (output port side), transmits the earliest time T _m of that time or later is free all I do. In this reservation table, a time and a flag indicating whether or not a cell is transmitted from the input port at this time are stored in association with each other (see FIG. 6 (b)). flag and returns to the input control unit the time T _m which all have been reset.

Input control unit that receives the time T _m from the output control unit refers to the reservation table (input port side), the earliest time T _n at time T _m after capable of delivering the cell to the output port
Is transmitted to the output control unit. The reservation table, the time (see FIG. 6 (c)) Yes and a flag indicating the presence or absence of cells to be transmitted to the output port in this time and stores the corresponding not a only, the flag is reset at time T _m after transmitting the earliest time T _n which is the output control section.

If the buffer is configured in a double buffer format or the like and two or more cells can be transmitted to different output ports at the same time, the reservation table contains the time and the number of cells transmitted from the input port at this time. Yes stored corresponding not a only, the time T _m and the number of the transmission cell is later sent to the output control unit the earliest time T _n which is less than the number of cells that can be sent.

Output control unit which receives the time T _n from the input control unit, the time
The input port number corresponding to T _n is written, and a series of scheduling processing ends.

[Problems to be solved by the invention]

Incidentally, since in the conventional method described above, to the reception request from the input control unit, the output control unit for performing a return to the scheduling process the earliest time T _m after that time are all empty, the time Even if there is a time at which transmission is possible before T _m, cell transmission is not performed and communication efficiency is poor.

The present invention has been made in view of such a point, and an object of the present invention is to provide a switch control method for improving communication efficiency.

[Means for solving the problem]

(I) Invention of Claim 1 FIG. 1 (A) is a principle block diagram of the switch control system of the invention of claim 1.

In the figure, ATM cells supplied to any one of a plurality of input ports are stored in an input cell analysis / buffer unit 111 corresponding to each of the input ports.
Switch 121 to the output destination that extracted the TM cell from the ATM cell.
In the control method of the switch sending out through the AT, the AT
An input cell analysis / buffer unit 111 for storing M cells and sequentially transmitting control information including at least a storage location and an output destination of the ATM cell is provided for each of the input ports, and the input cell analysis / buffer unit is provided. The control information received from 111 is stored in correspondence with a desired output destination, and the stored control information is sequentially and cyclically selected for each output destination. A switch control unit for sequentially transmitting information on the selected output destination to the switch 121; and each of the input cell analysis / buffer units 111 includes an ATM cell specified by the control information from the switch control unit. Is read.

(II) Claim 2 FIG. 1 (B) is a principle block diagram of the switch control system according to the invention according to claim 2.

The ATM cells supplied to any of the plurality of input ports are stored in the plurality of input cell analysis / buffer units 111 corresponding to the respective input ports, and the stored ATM cells are extracted from the ATM cells. In the control method of the switch for transmitting to the output destination via the switch 121, the input cell analysis / buffer unit 11 for sequentially transmitting control information including the storage location of the ATM cell and the output destination for each of the input ports.
A buffer for storing the control information and an input management table for managing the presence / absence of a cell time read from the input cell analysis / buffer unit 111; and a buffer for storing the control information in the order of the read cell time. To the input cell analysis / buffer unit 111, and an input management unit 151 for sending output destination information corresponding to the read cell time to the switch unit, and a cell time for sending an ATM cell for each output destination. The output management table 161 that manages the presence or absence of the reservation is compared with the input management table corresponding to the output destination included in the stored control information and the output management table 161 corresponding to the output destination, and the same. Among the cell times, the earliest cell time for which both reservations are not made is detected, and the input method table and the output management table 161 are detected. Reservation means 171 for setting the cell time to reserved, wherein the input cell analysis / buffer unit 111 is provided for the ATM cell specified by the control information of the read cell time supplied from the input management unit 151. Is configured to operate so as to read out.

(Operation)

(I) The invention according to claim 1 includes a plurality of input cell analysis / buffer units 111 corresponding to a plurality of input ports, respectively. The ATM cells supplied to the input cell analysis / buffer unit 111 are switched control units. The output is output to the output port of the output port number extracted from the ATM cell by switching by the communication path switch 121 under the control of 191.

The switch control unit 191 is provided for each input cell analysis / buffer unit 1
A control buffer 131 prepared for each output port for sending ATM cells, and reading ATM cells stored in the input cell analysis / buffer unit 111 and communication path switch corresponding to 11
And a first control means 141 for designating the output port 121.

The ATM cell supplied from the input port is used for input cell analysis /
When stored in the buffer unit 111, the storage address is stored in the control buffer 131 specified by the output port number extracted from the ATM cell.

The first control means 141 cyclically selects each control buffer 131 so that the selection operation is not biased, and sets the output port number indicated by the selected control buffer 131 to the communication path switch 1.
21 and the selected control buffer 131
Is supplied to the corresponding input cell analysis / buffer unit 111.

Therefore, the ATM cell is read from the input cell analysis / buffer unit 111 and output from the communication path switch 121 to a predetermined output port.

According to the first aspect of the present invention, the operation of giving the read address of the ATM cell to be sent to a certain output port to the input cell analysis / buffer unit 111 is performed by cyclically selecting each control buffer 131. Since random access control of the input cell analysis / buffer unit 111 is performed, unnecessary waiting time for ATM cell transmission can be eliminated, and communication efficiency can be improved.

(Ii) The input cell analysis / buffer unit 111 corresponding to each of the plurality of input ports is provided.
The ATM cell supplied to the buffer unit 111 is
The output is output to the output port of the output port number extracted from the ATM cell by the switching by 121.

The ATM cell supplied from the input port is used for input cell analysis /
When stored in the buffer unit 111, the storage address and the output port number extracted from the ATM cell are stored in the input management unit 1.
51, output management table 161, sent to reservation means 171.

The input management table of the input management unit 151 stores information on the ATM cell transmission status corresponding to each of the input cell analysis / buffer units 111.
1 stores information about the output status of the output port.

The reservation means 171 compares these two management tables for each input cell analysis / buffer unit 111 or each output port, and finds the earliest cell time among cell times for which both reservations have not been made within the same cell time. Is reserved, and a reserved operation is performed on the input management table and the output management table 161. For example, two tables store the time and the presence or absence of a cell to be transmitted at that time, and reserve the earliest time at which an ATM cell can be transmitted to a predetermined output port.

In the buffer of the input management unit 151, the storage address from the input cell analysis / buffer unit 111 and the extracted output port number are managed in association with the cell time at which the reserved operation has been performed. The information is sequentially supplied to each input cell analysis / buffer unit 111, and the corresponding output port number is sequentially supplied to the communication path switch 121.

That is, the control of the communication path switch 121 based on the reservation result of the reservation means 171 and the corresponding input cell analysis / buffer unit 1
An instruction to read out the ATM cell to 11 is issued.

According to the second aspect of the present invention, by comparing the input management table of the input management unit 151 with the output management table 161 corresponding to each of the input cell analysis / buffer units 111, the cells which are not reserved are set. Since the earliest cell time among the times is reserved, useless waiting time can be eliminated, and communication efficiency can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a configuration of a first embodiment to which the switch control system of claim 1 is applied. FIG. 4 shows the configuration of a second embodiment to which the switch control system of claim 2 is applied.

I. Correspondence Between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be described.

The input cell analysis / buffer unit 111
1,311, corresponding to the header analysis units 213,313.

The speech path switch 121 corresponds to the speech path switches 200 and 300.

Control buffer 131 corresponds to the selector 221 ₁ ~211 _m, first-in-first-out memory (FIFO) 231 ₁₁ ~231 _mn.

The first control means 141 includes selectors 241 _{1 to} 241 _n , 251 to 251 _n ,
_{261 1 ~261 m, 281 1 ~281} m, corresponding to the selector control section 271.

The input management unit 151 corresponds to the input management unit 321 ₁ to 321 _m.

The output management table 161 corresponds to the output management table 343.

The reservation unit 171 corresponds to the control unit 351 and the bus management unit 361.

An embodiment of the present invention will be described below assuming that there is the above correspondence.

II. In the configuration and operation second view of the first embodiment, 200 channel switch, the 211 _1-211
m is the input buffer, 213 ₁ to 213 _m is the header analyzer, 2
Reference numeral 20 denotes a switch control unit.

 It is assumed that the number of input ports is m and the number of output ports is n.

The ATM cells supplied to the m input ports are stored in the corresponding input buffer units 211 _{1 to} 211 _m , then supplied to the communication path switch 200, and further output to a desired output port. These input buffer units 211 _{1 to} 211 _m
The reading of the ATM cell and the switching operation in the call path switch 200 are controlled by the switch control unit 220 (detailed control operation will be described later). Further, in FIG. _{1 to} 221 _m , n 241 ₁ to 241 _n , n 251 _{1 to} 25
Each of 1 _n , m 261 ₁ to 261 _m is a selector, m × n 231 ₁₁ to 231 _mn is a first-in first-out memory (FIFO), and 271
Indicates a selector control unit that controls the entire switch control unit 220.

When an ATM cell is input to any input buffer unit (hereinafter, denoted by reference numeral "211" not including a subscript number for simplicity) via an input port, the input buffer unit 2
The header analysis unit connected to 11 (hereinafter, for simplicity, denoted by reference numeral “312” not including a suffix number) analyzes the header of the ATM cell and outputs the ATM cell to the output port. And outputs the output port number together with the input port number to the control terminal of the corresponding select 221.

Also, the input buffer unit 211 outputs the input buffer unit 2
Reference numeral 11 outputs the address (write address) of the storage area storing the ATM cell, and this address is supplied to the input terminal of the corresponding selector 221.

Each of the selectors 221 ₁ to 221 _m, the input ports (the input buffer unit 211 ₁ ~211 _m, the header analysis unit 213 ₁ ~213 _m)
And selects an output terminal for outputting the write address supplied from the corresponding input buffer unit 211 based on the output port number supplied from the corresponding header analysis unit 213. Selector 221 _{1 to} 22
Each 1 _m has the same number of output terminals (first output terminal to n-th output terminal) as the number of output ports, and the corresponding selector 221 corresponds to the output port to which the ATM cell is to be output. The write address is output to the output terminal.

Each output terminal of the selector 221 ₁ to 221 _m, 1: 1 is connected to the m × n FIFO231 ₁₁ ~231 _mn corresponding to, these outputs write address outputted individually from the terminal corresponding (Hereinafter, for simplicity, denoted by reference numeral “231” not including the suffix number).

In this way, the ATM cells are sequentially stored in the input buffer unit 211, and correspond to the input buffer unit 211.
The write address of the input buffer unit 211 is stored in the FIFO 231 corresponding to the output port to which these ATM cells are to be output.

For example, an output port # supplied from input port # 1
The ATM cells to be output to n, the write address of the storage area of the input buffer unit 211 ₁ this ATM cell is written is stored is output from the n output terminals of the selector 221 ₁ to FIFO231 _1m. Similarly, input port #
ATM to be supplied from X and output to output port #Y
The cell, the write address of the storage area of the input buffer unit 211 _X of the ATM cell has been written, the selector
The signal is output from the Y-th output terminal of 211 _X and stored in FIFO 231 _XY .

The selectors 241 _{1 to} 241 _n correspond to n output ports, respectively, and are connected to m input terminals (first input terminal to m-th input terminal) individually provided by the selectors 241 _{1 to} 241 _n. the write address supplied from each of the m input ports mentioned above are inputted via the FIFO231 ₁₁ ~231 _mn.

For each of the FIFOs 231 _{11 to} 231 _mn , the storage status individually indicating whether or not any write address is stored is supplied to the selector control unit 271. For example FIFO2
When 31 is empty, the selector flag is notified to the selector control unit 271 by setting the empty flag.

Selector controller 271, while monitoring the empty flag of FIFO231 ₁₁ ~231 _mn, for each of the selectors 241 ₁ ~241 _n, since these selectors 241 ₁ ~241 _n performs "cyclic selection operation" Perform necessary control.

Such under the control of the selector controller 271, selector 241 ₁ ~241 _n is (as select operation is not biased) cyclically one of a FIFO231 the empty flag is not set and selected, The write address stored in the FIFO 231 is read. Here, for simplicity, it is assumed that the selector 241 selects a FIFO 231 in which the empty flag is not set and outputs a write address stored in the FIFO 231.

Therefore, each of the selects 241 _{1 to} 241 _n corresponding to each output port on a one-to-one basis outputs the write address of the input buffer unit 211 in which the ATM cell to be supplied to the corresponding output port is stored.

These write address, n-number of selectors 251 for selecting operation under the control of the selector controller 271 ₁ ~251 _n
And the m input selectors 261 _{1 to} 261 _m , the corresponding input buffer sections as read addresses.
Supplied to 211. Accordingly, the input buffer unit 211 outputs the ATM cell stored at the read address and supplies the ATM cell to the communication path switch 200.

The control signal supplied to the respective selectors 241 ₁ ~241 _n from the selector control unit 271 is also input to the channel switch 200. The speech path switch 200 performs a switching operation for outputting an ATM cell supplied from each input buffer unit 211 to a predetermined output port based on the control signal.

As described above, the FIFOs 231 _{11 to} 231 _mn are cyclically selected, the control information (write address) stored therein is read, and given as a read address to the corresponding _{one of} the input buffer units 211 _{1 to} 211 _n. The input buffer unit 21
Since 1 can be accessed at random, unnecessary waiting time can be eliminated, and communication efficiency can be improved.

That is, as compared with the conventional technology in which the output control unit corresponding to the transmission destination of the ATM cell waits for the transmission of the ATM cell until the earliest time Tm at which all subsequent times are judged to be empty after the subsequent time, the Since the resources of the buffer units 211 _{1 to} 211 _n , the communication path switch 200, and the output port are efficiently applied, the communication efficiency is improved.

In the above-described embodiment, the FIFO 231 is used. However, the FIFO 231 may be configured with a RAM, and the empty flag may be separately detected. FIFO for each output port
The configuration may be such that the 231s are collectively configured as one RAM, and an empty flag is output corresponding to the output port. In place of the m selectors 261 ₁ ~261 _m, number each input terminal can also be used m-number of OR gates is n.
Further, each of the selectors 261 ₁ ~261 _m, the output end may be formed of n tristate buffers connected to each other.

FIG. 3 shows another configuration example of the first embodiment shown in FIG. In this configuration, the switch control unit 220 in FIG. 2 is replaced with a switch control unit 290. The switch control unit 290, the input buffer to the output side of each FIFO231 switch control unit 220 connects to each of the m selectors 281 ₁ ~281 _m, corresponding to each output terminal of the selector 281 ₁ ~281 _m It is connected to the section 211 _{1 to} 211 _m .

Selector controller 271, selector 281 _1-281 input terminal number selected at each _m, i.e. performs control so that the input port number do not overlap. For example, if you select the first input terminal the selector 281 _1, so as not to select the first input terminal In another selector.
As a result, the output ports that have output one-to-one correspondence are assigned to the respective input ports, and the ATM cells are transmitted according to this correspondence.

III. Configuration and Operation of Second Embodiment In FIG. 4, reference numeral 300 denotes a communication path switch, and 311 _{1 to} 311
_m is the input buffer section, 313 ₁ to 313 _m are the header analysis section, 3
Reference numeral 20 denotes a switch control unit.

 Now, it is assumed that the number of input ports is m and the number of output ports is n.

ATM cell supplied to the m input ports, the input buffer unit 311 ₁ corresponding to each of these input ports
It is stored at 31 _m and output to a desired output port via the communication path switch 300. These input buffer units 311 ₁
Operation of reading ATM cells from ~ 311 _m and speech path switch 3
00 controls the operation of forming the communication path by the switch control unit 32.
It is performed in a time-sharing manner under the initiative of 0 (a more detailed control operation will be described later).

In FIG. 4, reference numerals “321 ₁ ” to “321 _m ” constituting the switch control unit 320 indicate an input management unit, reference numeral “341” indicates a decoder, and reference numeral “351” indicates a switch control unit 320. A control unit for controlling the whole is shown, and reference numeral “361” indicates a bus management unit.

Further, the input management units 321 _{1 to} 321 _m include two registers 331 and 333 for temporarily holding data, and two shift buffers 335 for writing data at an arbitrary position and reading data in a predetermined order. , 337 and an input management table 339.

Each component is connected to the bus, and the input buffer 311 ₁
~311 _m, header analysis unit 313 ₁ ~313 _m, the input management unit 321 _1-32
1 _m indicates that one of the operations is enabled in response to a select signal (supply line is omitted) output from the bus management unit 361, and is subject to a time-division process described below under the control of the control unit 351. Becomes

FIG. 5 shows the operation of the switching control in the second embodiment.

In the figure, “cell time” indicates a processing order, and “outputs # 1, # 2,...” Correspond to the respective output ports # 1 to #n.

Each bit data stored in the input management table 339 and the output management table 343 indicates whether or not there is a cell to be transmitted at the corresponding cell time.

For the bit data (for example, 1100100) stored in the input management table 339, a logical value “1” indicates that there is a cell to be transmitted from the input buffer corresponding to the corresponding cell time, and a logical value “0” Indicates that there is no such cell.

Further, with respect to the bit data stored in the output management table 343, a logical value “1” indicates that there is a cell to be transmitted from any of the input buffer units to the corresponding output port at the corresponding cell time. A logical value "0" indicates that no such cell exists.

Hereinafter, the operation of the second embodiment will be described with reference to FIGS. 4 and 5.

In the switch control unit 320, the bus management unit 361 performs time-division processing of “outputting selection information indicating the input ports # 1 to #m one by one cyclically as the above-described select signal”.

Therefore, in the following description of the operation, the input port #
Focusing on only 1 is performed.

Select signal input buffer 311 which is output from the bus management unit 361 _1, the period indicated the selection information corresponding only to the header analysis unit 313 ₁ and the input management unit 321 _1, the other header analysis unit 313 ₂ ~313 _m and operation of the input management unit 321 ₂ to 321 _m is restricted, and the operation corresponding only to the input port # 1 becomes effective.

Input buffer unit 311 _1, when the ATM cell is supplied from the input port # 1, reads the ATM cells. Incidentally, the functions of the input buffer unit 311 ₁ are similar to those of the input buffer unit 211 ₁ ~211 _m features in the first embodiment described above, detailed description thereof is omitted here.

Header analysis unit 313 _1, read in this way AT
By analyzing the header of the M cell, the output port number to which the ATM cell is to be transmitted (eg, number # 2)
And outputs it to the bus together with the input port number.

The decoder 341 takes in the output port number # 2 described above via the bus and generates an access signal corresponding to the output port number # 2. The output management table 343 reads out and outputs bit data (for example, 101001 shown in output # 2 in FIG. 5) relating to the output port corresponding to such an access signal.

In addition, the register 333 stores the header analysis unit 313 as described above.
₁ holds the output port number # 2 output to the bus, and the register 331 fetches and holds via the bus the write address indicating the storage area of the input buffer 311 ₁ in which the ATM cell is stored.

Next, the control unit 351 compares the bit data of the output management table 343 read in this way with the bit data stored in the input management table 339, and determines that the logical value of both is "0". Book early cell time,
The logical value of the corresponding bit data in the output management table 343 and the input management table 339 is updated to “1”. By this reserved operation, the bit string of output # 2 of the output management table 343 becomes 101101, and the bit string of the input management table becomes 1101100.

By the way, the shift buffers 335 and 337 individually have a storage area corresponding to the input management table 339 and the output management table 343 for each cell time.

The register 331 is an input buffer unit that stores ATM cells.
A register for temporarily holding the write address of the storage area 331. The area of the shift buffer 335 corresponding to the area of the input management table 339 in which the logical value is updated to “1” by the control unit 351 as described above in units of cell time. Then, the write address held in the register 331 is stored. That is, the data is stored at a position indicated by oblique lines in the area of the shift buffer corresponding to the cell time 4.

The register 333 is a register for temporarily holding an output port number to which an ATM cell is to be transmitted. As described above, the area of the output management table 343 whose logical value has been updated to “1” by the control unit 351 has a cell time unit. Then, the output port number held in the register 333 is stored in the area of the shift buffer 337 corresponding to.

As described above, the shift buffer 335 gives the write address stored in the storage area in the order of the cell time to the input buffer unit 311 via the bus sequentially as the read address of the next ATM cell.

Further, in parallel with the operation of the shift buffer 335, the shift buffer 337 similarly outputs the output port number stored in the storage area in the order of the cell time, and outputs the output port number and the bus to the communication path switch 300. A communication path for the next one cell time is formed between the input port # 1 (input buffer unit 311) corresponding to the identification information output by the management unit 361.

Then, the input buffer unit 311 and the communication path switch 300
Each ATM cell that operates in synchronization with the cell time and is stored in the input buffer unit 311 is reliably transferred to a desired output port to which the ATM cell is to be transmitted in a cell unit via the communication path switch 300. Sent out.

As described above, according to the present embodiment, the input ports # 1 to #m
Management table 339 and output port # corresponding to each
Based on a comparison with the output management table 343 corresponding to 1 to #n, “timing at which an ATM cell given to each input port should be sent to an output port” is reliably set as the earliest cell time in cell units. Therefore, communication efficiency is improved as compared with the related art. Further, the input management table 33
9 and the output management table 343 are all performed at the same time, but time-division and partial comparison is performed, and unnecessary parts (such as places where all reservations are made, places where reservations are completed, etc.) ) May not be compared.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, the storage address of the ATM cell stored in the input cell analysis / buffer unit is managed in association with the output port number, and corresponds to the number of the output port to be cyclically selected. The input cell analysis / buffer unit is given a read address to be read, so that random access control of the input cell analysis / buffer unit is performed, thereby eliminating unnecessary waiting time for ATM cell transmission and improving communication efficiency. It becomes possible.

According to the invention of claim 2, no reservation is made by comparing the input management table corresponding to each of the input cell analysis / buffer units with the output management table corresponding to each of the output ports. Since the earliest cell time among the cell times is reserved, useless waiting time can be eliminated, and communication efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the switch control system of the present invention, FIG. 2 is a block diagram of a first embodiment to which the switch control system of the present invention is applied, FIG. 3 is another block diagram of the first embodiment, FIG. FIG. 4 is a block diagram of a second embodiment to which the switch control system of the present invention is applied, FIG. 5 is an explanatory diagram of the operation of the second embodiment, and FIG. 6 is an explanatory diagram of a conventional example. In the figure, 111 is an input buffer, 121 is a call path switch, 131 is a control buffer, 141 is a first control unit, 151 is an input management unit, 161 is an output management table, 171 is a reservation unit, 181 is a second control unit, 200,300 are communication path switches, 211,311 are input buffer sections, 213,313 are header analysis sections, 220,290,320 are switch control sections, 221,241,251,261,281 are selectors, 231 is first-in first-out memory (FIFO), 271 is a selector control section, 321 is an input control section, and 321 is an input management section. Registers, 335 and 337 are shift buffers, 339 is an input management table, 341 is a decoder, 343 is an output management table, 351 is a control unit, and 361 is a bus management unit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiaki Watanabe 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kazuo Iguchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Inventor Tetsuo Soejima 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-61-127250 (JP, A) JP-A-62-247653 (JP, A)

Claims (2)

(57) [Claims] 1. A power supply provided to one of a plurality of input ports.
In a switch control method, an ATM cell is stored in an input cell analysis / buffer unit corresponding to each of the input ports, and the stored ATM cell is transmitted to an output destination extracted from the ATM cell via a switch. An input cell analysis / buffer unit for storing the ATM cell and sequentially transmitting control information including at least a storage location and an output destination of the ATM cell is provided for each of the input ports; The control information received from the buffer unit is stored in correspondence with a desired output destination, and the stored control information is sequentially and cyclically selected for each output destination, and the desired input cell analysis / buffer unit is selected. A switch control unit for sequentially transmitting the output destination information to the switches, wherein each of the input cell analysis / buffer units receives the information from the switch control unit. Control method of the switch, characterized in that it operates to read the ATM cell specified by the control information. 2. A power supply provided to one of a plurality of input ports.
In a switch control method, an ATM cell is stored in an input cell analysis / buffer unit corresponding to each of the input ports, and the stored ATM cell is transmitted to an output destination extracted from the ATM cell via a switch. An input cell analysis / buffer unit for storing the ATM cells and sequentially transmitting control information including at least a storage location and an output destination of the ATM cells for each of the input ports, and reading from the input cell analysis / buffer unit An input management table for managing the presence / absence of cell time reservation, and a buffer for storing the control information; and sequentially supplying the control information from the buffer to each input cell analysis / buffer unit in the order of the read cell time; An input management unit that sends output destination information corresponding to the read cell time to the switch unit; An output management table that manages whether or not there is a reservation of a cell time for transmitting an ATM cell; an input management table corresponding to an output destination included in the stored control information; and an output management table corresponding to the output destination. And a detecting unit that detects the earliest cell time for which both are not reserved among the same cell times, and sets the cell time as reserved in the input management table and the output management table. The input cell analysis / buffer unit operates to read an ATM cell specified by the control information of a read cell time supplied from the input management unit.