JPH02179141A - Switch control system - Google Patents

Abstract

PURPOSE:To improve communication efficiency by controlling plural control buffers storing the storage address of an ATM cell and a speech path switch and an input buffer based on the plural control buffers corresponding to the transmission destination of each input buffer and an asynchronous transfer mode(ATM) cell. CONSTITUTION:When an ATM cell is supplied to an input buffer 111, the storage address of the ATM cell to the input buffer 111 is stored to a control buffer 131 prepared by the output port with the ATM cell sent therefrom corresponding to each input buffer. A 1st control signal 141 reads the storage address data of the input buffer 111 stored respectively to the control buffer 131 in the unit of the output ports, applies the selection to control the speech path switch 121. Moreover, the storage address data of the input buffer 111 selected by the selection is supplied to the corresponding input buffer 111 to read the ATM cell. Thus, since waiting time can be eliminated, the communication efficiency is improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Example 1 Correspondence between the Example and FIG. 1 Structure and operation of the first embodiment ■ Structure and operation of the second embodiment Effects of the invention [Summary] Switch control for controlling communication path switches between each input port and each output port in an ATM communication device Regarding the method, in a switch control method in which ATM cells supplied to multiple high-power buffers are sent out to a predetermined output port via a communication path switch, with the aim of increasing communication efficiency, each input buffer and ATM cell a plurality of control buffers corresponding to the sending destinations of the ATM cells and storing storage addresses of the ATM cells; and a first control buffer that controls the communication path switch and the input buffer based on the plurality of control buffers.
and a control means.

Further, a first reservation table stores the ATM cell sending status of each input buffer and each output port.

The apparatus is configured to include a second reservation table, a reservation means for performing a reservation operation according to each of these reservation tables, and a first control means for controlling a communication path switch and an input buffer based on the reservation result.

[Industrial application field]

The present invention relates to a switch control method for controlling communication path switches between each input port and each output port in an ATM communication device.

[Conventional technology]

Wideband 15DN uses asynchronous transfer mode (85 synchronous transfer mode) to provide multimedia communication such as audio, video, and high-speed data communication.
fixed-length packets (hereinafter referred to as ATM)
A high-speed communication system (cell) is being considered.

In this ATM communication method, the A supplied to the input port is
There are mainly the following switching methods for outputting TM cells to desired output ports.

■A method of providing a buffer on the output port side (output buffer method).

■A method in which a buffer is provided on the input boat side (input buffer method).

■A method in which common memory is provided and accessed between each input/output board.

Among these methods, the method (2) has a disadvantage of having a large buffer capacity, and the method (2) has the disadvantage of requiring a long access time because the common memory is accessed from each port. On the other hand, the input buffer method (2) does not have these drawbacks and can be said to be an effective method for realizing an ATM switch.

As shown in FIG. 6(a), each of the plurality of input ports is provided with a buffer (input buffer) for temporarily storing ATM cells. ATM via this buffer
The cells are output to any one of a plurality of output ports via a communication path switch.

In addition, each of the plurality of input ports described above is provided with an input control section that corresponds to one to one, and each of the plurality of output ports is provided with an output control section that corresponds to one to one. Control information is exchanged via.

The operation when a cell supplied to any input port is output to any output port will be described below.

(2) When an ATM cell arrives at the input port, the input control section transmits the input port number to the destination output control section.

■The output boat receives the input boat number sent in ■. If input port numbers are received from multiple input control units at the same time, one is selected cyclically.

■The output control unit refers to the received (selected) input control unit by referring to the reservation table (output port side) for the corresponding output port, and selects the earliest time T at which all periods after that time are free. Send. This reserved table has
The time and a flag indicating whether or not a cell is sent out from the input port at this time are stored in a corresponding manner (see Fig. 6).
(b)), the time T at which all flags after that time have been reset is sent back to the input control unit.

■The input control unit, which has received time T1 from the output control unit, refers to the reservation table (input boat side) and selects the time T at which cells can be sent to the output port, and the earliest time T7 thereafter, to the output control unit. Send to. This reservation table stores the time and a flag indicating whether or not there are cells to be sent to the output port at this time (Fig. 6 (c)).
), time T. From then on, the earliest time T7 at which the flag is reset is transmitted to the output control section.

In addition, if the buffer is configured in a double buffer format, etc., and two or more cells can be sent to different output ports at the same time, this reservation table contains the time and the number of cells to be sent from the input port at this time. The time T which is the earliest after time T and at which the number of cells to be transmitted is less than the number of cells that can be transmitted is transmitted to the output control unit.

■Time T from the input control unit. The output control unit that has received this writes the corresponding input port number at time T7, and ends the series of scheduling processes.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional method, in response to a transmission request from the input control section, the output control section performs scheduling processing by returning the earliest time T that is available after that time. T. Cells are not transmitted even if there is a time when they can be transmitted earlier, resulting in a problem of poor communication efficiency.

The present invention was created in view of these points, and an object of the present invention is to provide a switch control method that improves communication efficiency.

[Means for Solving the Problems] 11J11-1 FIG. 1(A) is a principle block diagram of the switch control system of the invention of claim 1.

In the figure, in a switch control system in which ATM cells supplied to a plurality of input buffers 111 corresponding to each of a plurality of input ports are sent to a predetermined output port via a channel switch 121, a plurality of control The buffer 131 provides AT to each of the input buffers 111.
When an M cell is supplied, the address for storing this ATM cell in the large capacity buffer 111 is stored in correspondence with each input buffer 111 and the destination of this ATM cell.

The first control means 141 receives the stored address data stored in the plurality of control buffers 131, performs a selection operation for each output port, controls the communication path switch 121, and also controls the output port as a result of this selection operation. The storage address data is supplied to the corresponding input buffer 111.

As a whole, a control buffer 131 corresponding to an output port is provided at each input port, and control is performed in accordance with this control buffer 131.

FIG. 1(B) is a principle block diagram of the switch control system of the invention according to claim 2.

In the figure, in a switch control system in which ATM cells supplied to a plurality of input buffers 111 corresponding to each of a plurality of input ports are sent to a predetermined output port via a channel switch 121, a first reserved The table 151 corresponds to each of the plurality of input buffers 111 and stores information regarding the sending status of ATM cells from the corresponding input buffer 111.

The second reservation table 161 corresponds to each output port and stores information regarding the sending status of ATM cells to be sent to the corresponding output port.

The reservation means 171 performs time division processing corresponding to each of the input buffers 111 or each output port, compares the two reservation tables 151 and 161, and makes a reservation for the operation of the communication path switch 121.

The second control means 181 controls the communication path switch 121 based on the reservation result by the reservation means 171 and instructs the reading of ATM cells from each of the power buffers 111.

As a whole, the first reservation table 151 corresponding to each of the input buffers 111 is compared with the second reservation table 161 corresponding to each output port to reserve the operation in the communication path switch 121. There is.

[For production]

(i) A plurality of input buffers 111 corresponding to each of the plurality of input ports of 8-inch x 1 Kazuaki are provided, and the ATM cells supplied to the input buffers 111 are switched to a predetermined output by a channel switch 121. output to the port.

When an ATM cell is supplied to this input buffer 111,
The storage address of the ATM cell in the input buffer 111 is stored in a control buffer 131 that corresponds to each input buffer and is prepared for each output port that sends out this ATM cell.

The first control means 141 reads out the stored address data of the input buffer 111 stored in each of the control buffers 131 in units of output ports and performs a selection operation.
Controls the communication path switch 121. Further, the storage address data of the input buffer 111 selected by this selection operation is supplied to the corresponding person cover buffer 111,
Reading of the ATM cell is performed.

In the invention of claim 1, the input buffer 111 and the AT
A to each control buffer 131 corresponding to the destination of the M cell.
By storing the storage address of the TM cell and performing a selection operation for each output port, unnecessary waiting time can be eliminated, and communication efficiency can be improved.

A plurality of input buffers 111 are provided corresponding to each of a plurality of input ports, and the ATM cells supplied to the input buffers 111 are transferred to a predetermined output port by switching by a channel switch 121. is output to.

The first reservation table 151 stores information regarding the sending status of ATM cells corresponding to each input buffer 111, and the second reservation table 161 stores information regarding the sending status of ATM cells corresponding to each output port. Stored.

The reservation means 1.71 makes a reservation by comparing these two reservation tables for each large-power buffer 111 or for each output port. For example, the two tables store times and whether or not there are cells to be sent at those times, and the earliest time at which an ATM cell can be sent from a predetermined high-power buffer 111 to a predetermined output port is reserved. .

This reservation result is supplied to the second control means 181, which controls the communication path switch 121 and the corresponding power buffer ill.
An instruction to read an ATM cell is given to the ATM cell.

In the invention of claim 2, by comparing the first reservation table 151 corresponding to each of the input buffers 11 and the second reservation table 161 corresponding to each of the output ports, unnecessary waiting time is eliminated. Since it can be eliminated, communication efficiency can be improved.

【Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows a first switch control system to which the switch control method of claim 1 is applied.
The configuration of an example is shown. Further, FIG. 4 shows the configuration of a second embodiment to which the switch control method of claim 2 is applied.

(1) Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The power buffer 111 includes an input buffer section 211゜311
, corresponds to the header analysis units 213 and 313.

The communication path switch 121 is the communication path switch 200.30.
Corresponds to 0.

The control buffer 131 has selectors 221 . ~2211.
This corresponds to first-in first-out memory (FIFO) 231, to 231□.

The first control means 141 includes a selector 241. ~241,.
251. ~251. ．． , 261. ~261,. 28t,
~281 corresponds to the selector control section 271.

The first reservation table 151 includes input management units 3211 to 32
This corresponds to the input management table 339 in 11.

The second reservation table 161 corresponds to the output management table 343.

The reservation means 171 controls the control unit 351. It corresponds to the bus management section 361.

The second control means 181 includes input management units 3211 to 321,
This corresponds to the shift buffers 335 and 337 and the control section 351 within the control section.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■, l In Figure 2, 200 is the communication path switch, 2111 is the
~2111I is the input buffer section, 213, ~213.
220 indicates a header analysis section, and 220 indicates a switch control section.

Now, assume that the number of input boats is m and the number of output boats is n.

The ATM cells supplied to the m input ports are sent to the input buffer sections 211 . ~211, and then supplied to the communication path switch 200, and further output to a desired output port. These input buffers 2111
The reading of ATM cells from ~2111I and the switching operation in the communication path switch 200 are controlled by the switch control unit 220 (detailed control operations will be described later).

In addition, in FIG. 2, m pieces 22L to 221a and n pieces 241+ to 24 forming the switch control unit 220 are shown.
In, n 2511~251゜m 2611~
261. each of which selects mXn 231 .
1-231. , l is first-in first-out memory (FIFO)
and 271 indicate a selector control section that controls the entire switch control section 220.

A to either input buffer section 211 via the input port.
When a TM cell is input, the header analysis unit 213 connected to the input buffer unit 211 analyzes the header part of the ATM cell, extracts the output port number for outputting this ATM cell, and selects the output port number of the corresponding selector 221. Supplied to control terminal.

Further, the input buffer section 211 outputs an address (write address) in which the ATM cell is stored, and is supplied to the input terminal of the corresponding selector 221.

Each of the selectors 2211 to 2211 has a one-to-one correspondence with each input port (each input buffer section 211 and each header analysis section 213), and selectors 2211 to 2211 have a one-to-one correspondence with each input port (each input buffer section 211 and each header analysis section 213). Then, the output terminal that outputs the write address supplied from the corresponding large-power buffer section 211 is selected. Selector 221
．． ~221, each is the output terminal of the number of output ports (
The corresponding selector 221 outputs the write address to the output terminal corresponding to the output port that outputs the ATM cell.

Selectors 2211-221. mXn FIFOs 231, . . . ~2 FIFOs 231, .
31. ．． are connected, and the write address output from the output terminal is stored in the corresponding FIFO 231.

In this way, each input buffer section 211 is sequentially provided with an ATM.
The write address of the input buffer section 211 is stored in the PIF0231 which corresponds to the input buffer section 211 and the output port number to be outputted.

For example, in response to an ATM cell supplied from input port #1 and output to output port #n, input buffer section 211 . write address is selector 22
It is output from the nth output terminal of 11 and FIFO231,,
is stored in Similarly, in response to an ATM cell supplied from input port #X and output to output port #Y,
The write address of the input buffer section 211x of this ATM cell is the selector 221. It is output from the first output terminal of and stored in FfFO231xy.

Further, each of the selectors 2411 to 241+ corresponds to each of the n output ports, and each of the m
m input terminals (first input terminal to m-th input terminal)
Write addresses supplied from each of the input ports are input via the FIFO 231.

Further, the storage status of write addresses by each FIFO 231 is supplied to the selector control unit 271. For example, when the FIFO 231 becomes empty, an empty flag is set and the selector control unit 271 is notified.

The selector control 1 section 271 monitors the empty flag of each FIFO 231 and controls the selectors 2411 to 241.
, are supplied with a control signal for performing a cyclic selection operation.

Under the control of the selector control unit 271, the selector 2411 first cyclically (selection operation is biased) selects the items in the FIFO 231 (FIFO 231 corresponding to the first output terminal of each selector 221) for which the empty flag is not set. ) and outputs the write address stored in this FIFO 231.

In each selector up to selector 2417, the FIFO (each selector 221
Among the FIFOs 231) corresponding to the corresponding output terminals, the FIFO corresponding to the already selected output port
One is selected cyclically from those excluding FO 231, and the stored write address is output.

In this way, selectors 241 . ~241. ．． Each outputs a write address of the input buffer 1 section 211 in which the ATM cell to be supplied to the corresponding output port is stored.

These write addresses are written to n selectors 251 .
~251. % and m selectors 261, ~261. are supplied to the corresponding high-power buffer sections 211 as read addresses. The input buffer section 211 to which the read address is supplied outputs the ATM cell stored at this read address,
The signal is supplied to the communication path switch 200.

In addition, the selector control unit 271 selects the selectors 2411 to 2411 to 2412.
The control signals supplied to each of the input buffers 417 are also input to the channel switch 200, and the channel switch 200 outputs the ATM cells supplied from each input buffer section 211 to a predetermined output port based on this control signal. Performs switching operations for

In this way, the A output from each input buffer section 211
The write address of the TM cell is set by the selectors 221, ~22.
1. FIFO 23 according to the destination of the ATM cell
1 sequentially. Thereafter, these FIFOs 231 are cyclically selected for each output port, and one write address corresponding to each output port is output. This write address is sent as a read address to the corresponding input buffer unit 211, and the corresponding ATM cell is read out and output to a predetermined output port via the communication path switch 200.

Therefore, by storing control information (write address) in the FIFO 231 and cyclically selecting this control information, it is possible to eliminate unnecessary waiting time and improve communication efficiency.

In addition, in the above-mentioned embodiment, F I FO231
is used, but it may be constructed from RAM and configured to detect the empty flag separately. The FIFO 231 corresponding to each output port may be configured in one RAM, and an empty flag may be outputted corresponding to the output port. In addition, m selectors 261. ~261. Instead of , it is also possible to use m OR gates, each with n input terminals. Furthermore, selector 2611
~261. n, whose output ends are connected to each other
It may also be configured with three tri-state buffers.

Further, FIG. 3 shows another configuration example of the first embodiment shown in FIG. 2. The configuration is such that the switch control section 220 in FIG. 2 is replaced with a switch control section 290. This switch control unit 290 controls each FIFO 23 of the switch control unit 220.
1 is connected to each of the m selectors 2811-2811, and the output side of the selector 2811-281. Each input buffer section 211.corresponds to each output terminal of 211. ~211. It is connected to.

The selector control unit 271 controls the selector 281. ~281□
Control is performed so that the selected input terminal numbers, that is, the input port numbers, do not overlap. For example, when the first input terminal is selected by the selector 2811, the first input terminal is not selected by the other selectors.

As a result, output ports corresponding to each input port are assigned in a one-to-l ratio, and ATM cells are transmitted according to this correspondence.

I [1, 2] In Fig. 4, 300 is the communication path switch, 3111
~311. 3131 to 313 . 320 indicates a header analysis section, and 320 indicates a switch control section.

Now, assume that the number of input ports is m and the number of output ports is n.

The ATM cells supplied to the m input ports are stored in the corresponding input buffer sections 3111 to 311, then supplied to the channel switch 300, and further output to a desired output port. These input buffers 3111
~311. Reading of ATM cells from the ATM cell and switching operations in the communication path switch 300 are controlled in a time-sharing manner by the switch control section 320 (detailed control operations will be described later).

In addition, in FIG. 4, there are m pieces 3211 to 321. which constitute the switch control section 320. 341 is an input management unit, 341 is a decoder, 343 is an output management table, 351 is a control unit that controls the entire switch control unit 320, and 361 is a control unit that controls the entire switch control unit 320.
indicate the bus management section.

Furthermore, each input management section 3211-321. includes two registers 331 and 333 for temporarily holding data, and two shift buffers 335 and 33 for writing data to arbitrary positions and reading data in a predetermined order.
7 and an input management table 339.

Each component is connected to a bus, and each input buffer section 31
1. Each header analysis unit 313. Each input management unit 321 enables one operation in response to a select signal (supply line is omitted) supplied from the bus management unit 361, and enables time-sharing processing under the control of the control unit 351. .

Further, FIG. 5 shows the operating procedure of switching control in the second embodiment.

In the figure, "cell time" indicates the processing order,
"Output #1. #2. . . ." indicates that each corresponds to each output port.

Input management table 339. Each bit of data in the output management table 343 indicates the presence or absence of a cell to be transmitted at the corresponding cell time.

The bit data lltfl in the input management table 339 is stored in the input buffer section 311 corresponding to the corresponding cell time.
The bit data "O" indicates that there are cells to be transmitted, and the bit data "O" indicates that there are no cells to be transmitted.

Further, bit data “1” in the output management table 343 indicates that the bit data “1” in the output management table 343 indicates that the input buffer unit 31
Bit data 1 indicates that there is a cell to be sent to the corresponding output port, and bit data 0° indicates that there is no cell.

The operation of the second embodiment will be described below with reference to FIGS. 4 and 5.

Since the control operation by the switch control unit 320 is performed by time-sharing processing, attention will be paid to input port #l, for example.

The select signal output from the bus management section 361 is output from the large buffer section 311. ．． Header analysis section 3131 and input management section 321. When supplied to input port #1, only control operations related to input port #1 are valid.

When an ATM cell arrives, the input buffer section 3111
The header analysis unit 313 reads the M cell and simultaneously reads the A
The header section of the TM cell is analyzed to extract the output port number for sending this ATM cell, and the extracted output port number is output to the bus.

The output port number output to the lotus is supplied to the decoder 341. The decoder 341 supplies an access signal corresponding to the input output port number to the output management table 343. In response to this access signal, bit data regarding the corresponding output port of the output management table 343 is read.

Further, the output port number output to the bus at this time is stored in the register 333, and the output port number of the large power buffer section 3111 is stored in the register 333.
The write address of the M cell is sent to the register 33 via the bus.
1 and stored.

Next, the control unit 351 compares the bit data of the output management table 343 read out in this way with the bit data stored in the input management table 339, and determines that neither of them is reserved (both of them are '0'). Reserve the earliest cell time (where ゛ is stored) and change the corresponding bit data to °°1''.

In addition, the register 33 is placed in the corresponding area of the shift buffer 335.
1 stored data (AT in the input buffer section 331)
M cell write address) is stored. Similarly, the data stored in the register 333 (the output port number for sending the ATM cell) is stored in the corresponding area of the shift buffer 337.

Note that the storage areas of the shift buffers 335 and 337 are allocated one to one for each cell time of the input management table 339.
When comparing the bit data between the input management table 339 and the output management table 343, the area corresponding to the cell time where the bit data was changed to "1" is
Write the data stored in register 331 or 333.

Similarly, corresponding to other input ports, a comparison operation between the input management table 339 and the output management table 343, a bit data change operation, a shift buffer 33
5,337 data storage operations are performed for the corresponding areas.

Further, in parallel with the above-described operation, switching processing by the communication path switch 300 is controlled in accordance with the order of cell times. Shift buffer section 33 in each input management section 321
5 is supplied to the corresponding input buffer section 311 as a read address, and
The output port number stored in each shift buffer 337 is supplied to the communication path switch 300. Call path switch 30
0 is the input management section 3211-321. The power buffer section 31
The ATM cells read from each of 11 to 3111 are output to a desired output port.

In this way, for each input port, the input management table 33
9 and the output management table 343, and a reservation is made for the earliest cell time that is not reserved for both.

This reservation operation is performed on a time-division basis for each input port.

Therefore, by making a reservation according to the comparison result of these two tables, it is possible to eliminate unnecessary waiting time and improve communication efficiency.

Note that in the embodiment described above, the shift buffer 33
5.337 is used, but a configuration using RAM and pointers may also be used. Further, although the processing related to each input port is performed in a time-sharing manner, the input management table may be accessed simultaneously for each output management table. Furthermore, an input management table 339 and an output management table 3
All comparisons with 43 are performed at the same time, but the comparison is done time-divisionally and in parts, so as not to compare unnecessary parts (parts where all reservations are made, parts after reservations are completed, etc.) It can also be done.

〔Effect of the invention〕

As described above, according to the invention of claim 1, the input buffer and ATM-! ! By storing the storage address of the ATM cell in each control buffer corresponding to the destination of the cell and performing selection operations for each output port, it is possible to eliminate unnecessary waiting time and improve communication efficiency. Become.

Further, in the invention of claim 2, by comparing the first reservation table corresponding to each of the input buffers and the second reservation table corresponding to each of the output ports, unnecessary waiting time can be eliminated. This makes it possible to improve communication efficiency.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the principle of the switch control method of the present invention, Fig. 2 is a block diagram of a first embodiment using the switch control method of the present invention, and Fig. 3 is a block diagram of the first embodiment of the switch control method of the present invention. Another configuration diagram of the example, FIG. 4 is a configuration diagram of the second embodiment to which the switch control method of the present invention is applied, FIG. 5 is an explanatory diagram of the operation of the second embodiment, and FIG. 6 is an explanatory diagram of the conventional example. be. In the figure, 111 is a power buffer, 121 is a communication path switch, 131 is a control buffer, 141 is a first control means, 151 is a first reservation table, 161 is a second management table, 171 is a reservation means, and 181 is a second control means, 200.300 is a communication path switch, 211.311 is an input buffer section, 213.313 is a header analysis section, 220.290, 320 is a switch control section, 221.2
41, 251, 261, 281 are selectors, 231 is a first-in first-out memory (F I FO), 271
is a selector control section, 321 is an input management section, 331.333 is a register, 335.337 is a shift buffer, 339 is an input management table, 341 is a decoder, 343 is an output management table, 351 is a control section, 361 is a bus management section It is. Layer of the sun and moon of this Sanskrit, 17'017 Figure 1 (A) False of the factory attack, 1l-1'"o = 17 Figure 1 (B) 452 Tsugi Ago Muitali's meeting Figure 5

Claims (2)

[Claims] (1) In a switch control system in which ATM cells supplied to a plurality of input buffers (111) corresponding to each of a plurality of input ports are sent to a predetermined output port via a channel switch (121). , when each input buffer (111) is supplied with an ATM cell, each input buffer (111) and this A
a plurality of control buffers (131) corresponding to the destinations of the TM cells and storing storage addresses of the ATM cells in the input buffers (111); and storage addresses stored in the plurality of control buffers (131). Data is introduced, and a selection operation is performed for each output port to control the communication path switch (121), and the storage address data output as a result of this selection operation is supplied to the corresponding input buffer (111). A switch control method comprising: a first control means (141); (2) In a switch control system in which ATM cells supplied to a plurality of input buffers (111) corresponding to each of a plurality of input ports are sent to a predetermined output port via a channel switch (121). , a first reservation table (1) corresponding to each of the plurality of input buffers (111) and storing information regarding the transmission status of ATM cells from the corresponding input buffer (111);
51), a second reservation table (161) corresponding to each of the output ports and storing information regarding the sending status of ATM cells to be sent to the corresponding output port, and each of the input buffers (111) or the output. Perform time-sharing processing corresponding to each port, compare the two reservation tables (151, 161),
a reservation means (171) for reserving an operation in the call path switch (121); and a reservation means (171) that controls the call path switch (121) based on the reservation result by the reservation means (171), and controls the input buffer (111). ) second control means (181) for instructing readout of ATM cells from each of the switch control systems.