JPH08251173A - Data exchange device - Google Patents

Abstract

PURPOSE: To obtain a data exchange device which is capable of making a unit switch have a multistage constitution, exapaning scale and simultaneously and efficeintly handling multi-address data, and is capable of storing plural low-speed interfaces and high speed interfaces. CONSTITUTION: This device is composed of the multistage connection part P provided with plural of first unit switches S1 and second unit switches S2 having 8 input lines and 2 output lines. The first unit switches S1-1 to S1 to 4 and the second unit switche S2-1 are connected on the first stage and the second stage, respectively, in a line concentration shape, as shown in a Figure. Only the unit switches S1 are provided with tables T-1 to T-4 defining the plural output lines which should output multi-address data. Input ports #0 to #31 are inputted in multistage connection parts P-1 to P-16 by branching the input ports. Output ports are assigned two by two to the multistage connection part P and the outputs to output ports #0 to #31 can be performed by 16 multistage connection parts P-1 to P-16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data exchange device for exchanging various kinds of multimedia information such as voice, data and images at high speed. In particular, the broadband IS
The present invention relates to a cell switching device that switches cells, which are fixed-length packets in which these data are blocked, at high speed in an asynchronous transfer mode (ATM) communication system adopted in DN.

[0002]

[Prior art]

Conventional example 1. When a large-scale switch is constructed, a method of expanding the scale by making a unit switch into a multi-stage configuration has been known. "Consideration of ATM switching system architecture" (Technical report of IEICE SSE89-3)
8, 1989. In the literature of Suzuki, Suzuki, Ito, Ishido), a case where three stages are connected is described as an example of a multistage configuration. FIG. 36 shows a constitutional model of a communication path. The cell that entered the system from the incoming line is transferred to the system operating clock from the received clock on the line in the cell synchronization unit, and is further output at the cell synchronization timing specified on the communication path in the system. . Next, the cell is input to the header processing unit. Here, the cell header is checked first, and if there is no error in the header, VCI
Based on, the outgoing line information for designating which outgoing line of the switch should be output is added, and the value of the VCI in the header section is changed to a predetermined value corresponding to the outgoing line. After the header conversion, the cell is input to the ATM switch unit, switched to the output line designated by the output line information added by the header processing unit, and output. The cell traffic measuring unit measures a cell passage amount or the like before or immediately after a switch in order to grasp a state of a call path or obtain a call amount for each call. The positions where the respective functions are provided are not necessarily the positional relationships shown in FIG. 36 depending on the processing method, but they are all necessary functions.

Next, the format of the route information given to the switch by the header processing unit will be considered. Normally, it suffices to give the outgoing line (outgoing port) number of each unit switch by the number of stages of the switch along the route of the route determined as a result of the call processing. Considering the support for broadcast connection, it is possible to specify the output to multiple outgoing lines in the bitmap format (each bit
Corresponds to the switch output line, and whether or not the cell output is specified by the bit value) is required to be expressed. On the contrary,
It is conceivable to use an outgoing line number for a normal one-to-one connection and use a bit map format expression only for a broadcast connection. FIG. 37 shows a comparison between the present method and the capacity of the route information search table when all are represented by a bitmap. From the figure, it can be seen that the hardware amount of the table can be significantly reduced by using only the broadcast call in the bitmap format.
For a broadcast call, the header processing unit in the preceding stage of the switch once converts the VCI into a broadcast call identification number, and the switch unit searches the table from the broadcast call identification number to make a bit map. At the time of one-to-one connection, the outgoing line number is obtained by the header processing unit in the preceding stage of the switch and sent to the switch. Next, the VCI update process of the cell will be considered. Considering the broadcast connection, the VCI can be updated only after switching (= cell duplication). However, in order to perform VCI conversion at the latter stage of the switch, the incoming line number or the identification number for each call that can be used instead (the above-mentioned broadcast identifier corresponds to this) is the VC at the latter stage of the switch.
It is necessary to carry around to the I converter. Considering the use of an identifier in the case of broadcast, the VCI update process is performed when the route information in the preceding stage of the switch is obtained during normal one-to-one connection, and the broadcast call identification number is used during broadcast connection. The method of conversion by the header processing unit provided at the post stage of the switch is suitable because the information to be carried around can be reduced and the number of tables does not increase. FIG. 38 shows the configuration of the header processing unit based on the above examination results. In the case of a one-to-one connection call, the header processing unit arranged in the preceding stage of the switch checks the header of the input cell, and outputs the outgoing line information from the VCI and the VCI (new VCI) defined on the next link. After searching and rewriting VCI, the cell and outgoing line information is sent to the switch section.

In the case of a broadcast connection call, the header processing unit arranged in the preceding stage of the switch retrieves the broadcast call identification number from the VCI and inputs it to the switch together with the cell. The cell output from the switch is searched for a new VCI by the header processing unit arranged at the output unit of the switch by the broadcast call identification number previously given and is written in the header. As an actual configuration, the capacity of each table exceeds 100 Kbytes as shown in FIG. 37, and therefore it is not a good idea at present to embed it in an LSI. Further, since the access is performed on a cell-by-cell basis, an ordinary general-purpose memory device can be used. Therefore, it is appropriate that the header processing unit is realized by a table including a logic unit configured by an LSI for checking, converting, and controlling the memory of the header unit and a general-purpose memory connected thereto.

As described above, the unit switches are configured in multiple stages to form a large-scale switch, and cells are copied and distributed to a plurality of destinations. At the same time, as shown in FIG. 37, it is also considered that the amount of a destination bitmap table that manages a plurality of outgoing lines to be output increases according to the identification number (VCI value) of the call within the incoming line. In particular, when a multi-stage connection such as a three-stage connection is made for a large scale, as shown in FIG. 38, each switch is provided with a destination bit map table and performs routing for a broadcast cell. for that reason,
There is a problem that the size of the destination bitmap table becomes enormous, but according to the document, the number of broadcast calls is limited,
Proposals have been made to introduce broadcast identifiers, which suggest reducing the destination bitmap table. However, with respect to the second and third tiers, broadcast cells may arrive from all incoming lines, and therefore the destination information of the broadcast calls for all incoming lines must be provided. Further, the broadcast call number is a number added to broadcast calls including all incoming lines, and there is a problem that the number becomes extremely large in the worst case.

Conventional example 2. When a large-scale switch is configured, the unit switch has a two-stage configuration and the method for expanding the scale is “An ATM System and Network”.
rk Architecture in Field
Trial, "(GLOBECOM '93, Session 40, 40.5, 1993. Wolfgang
Fischer, Rolf Stiefel and
It has already been disclosed in the document Tom Worster). FIG. 39 shows a case where a large-scale switch of 64 × 64 is configured by using 12 pieces of 32 × 16 switches. In the figure, 64 × 64 is obtained by connecting 4 sets of funnel-shaped structures (A) that make up 64 × 16 in parallel.
Form a large switch. Larger switching networks are possible with other combinations of switching elements. For example, 128 with a three-stage configuration
A × 128 switching network can be configured.

However, the document does not mention to handle the broadcast. Further, if the same idea as in the conventional example 1 is introduced, it is necessary to distribute all the cells of the incoming lines in the switches of the second and subsequent stages, which causes a problem that the amount of the destination bitmap table increases.

Conventional example 3. An ATM switch capable of accommodating a plurality of low speed interfaces is disclosed in JP-A-4-1804.
There are 33 examples.

FIG. 40 is an overall configuration diagram showing a cell exchange apparatus. This cell switching device 8 receives 15
32 input ports 6 of 5.52 Mb / s and 32 output ports 7 of 155.52 Mb / s that output cells
The cells are exchanged between the two. Further, this cell switching device 8 has the input port 6 of 155.52 Mb / s set to 1
ATM which accommodates eight circuits 1 and eight outgoing lines 2 with a 622.08 Mb / s interface and eight cell multiplexing circuits 4 for cell multiplexing to the 622.08 Mb / s incoming line 1
Eight circuits are provided with a switch 3 and a cell separation circuit 5 for separating one output line 2 of 622.08 Mb / s into four output ports 7 of 155.52 Mb / s.

FIG. 41 shows an example of the ATM switch 3. In the figure, reference numeral 1 denotes n (n ≧ 2) incoming lines in which input ports to which cells each including a header portion including an output port number as destination information and a data portion are input are cell-multiplexed. 2 is an m that accommodates an output port to be output according to the destination specified by the cell in the header part.
There are (m ≧ 2) output lines. Reference numeral 10 denotes a header processing circuit which is provided corresponding to each of the incoming lines 1 and detects the destination output port 7 from the header portion of the cell input through the incoming line 1. Reference numeral 11 stores the cells at a designated address, and by designating the address, the stored cells can be read out regardless of the order of writing, and p (p ≧ 1) buffer memories can be read. Is. Reference numeral 12 is a storage control circuit which is provided corresponding to each of the buffer memories 11 and manages an empty address by using, for example, a FIFO type memory and gives a read address and a write address to the associated buffer memory 11. . Reference numeral 13 is a cell writing circuit which selectively connects the header processing circuit 10 to a predetermined buffer memory 11 and is realized by a space switch. 14 is each buffer memory 11
Is a cell read circuit for selectively connecting to a predetermined output line 2 and is realized by a space switch.

Reference numeral 15 is a buffer control circuit. The buffer control circuit 15 controls the switching of the cell write circuit 13 to select the buffer memory 11 in which cells are stored. In addition, the buffer memory 11 for the accumulated cells
The above address is managed for each output port of each cell, and the switching of the cell read circuit 14 is controlled based on the address managed for each destination. Then, the cells are output in a predetermined order to the outgoing line 2 that accommodates the output port 7 designated by the header portion thereof.

The buffer control circuit 15 has the following configuration. The write buffer selection circuit 16 has an input line 1
When the cell arrives at, the output line number of the cell detected by the header processing circuit 10 provided corresponding to the input line 1 is received, and the buffer memory 11 that stores the cell is selected. Then, in order to connect the buffer memory 11 to the corresponding header processing circuit 10, the switching of the cell writing circuit 13 is controlled. Address exchange circuit 17
Refers to the output port number detected by the write buffer selection circuit 16, divides the arriving cells by destination output port, and stores the write address in the buffer memory 11 in which the cell is written in the buffer memory 11 corresponding to the write address. It is obtained from the control circuit 12 and written in the address queue described later. 18 is an address queue, F
The output line 2 is composed of an IFO type memory.
Are provided corresponding to the output ports accommodated in each. In the address queue 18, the write address in the buffer memory 11 in which the cell destined for the output port is accumulated is written in the address queue 18 by the address exchange circuit 17 in the order of arrival. Be done. The read buffer selection circuit 19 determines a cell to be read from the buffer memory 11 by referring to the address queue 18, and the storage control associated with the corresponding buffer memory 11 using the address read from the address queue 18 as a read address. Send to circuit 12. Also, by controlling the switching of the cell read circuit 14,
The buffer memory 11 is connected to the corresponding output line 2.

FIG. 42 shows an example of the internal circuit of the cell multiplexing circuit, which is an example of cell multiplexing the four 155.52 Mb / s input ports 6 in FIG. 40 to one 622.08 Mb / s input line 1. In the figure, one FI corresponding to the input port 6
A cell speed adjustment buffer 21 composed of an FO type memory is used, and writing is performed at 155.52 Mb / s and reading is performed at 622.08 Mb / s sequentially. FIG.
4 is an example of the internal circuit of the cell separation circuit. In FIG. 40, one 622.08 Mb / s outgoing line 2 is connected to four 155.52.
This is an example in which cells are separated into Mb / s output ports 7. In the figure, a cell speed adjustment buffer 23 and an address filter 22 each of which is composed of one FIFO type memory are used in correspondence with the output port 7, and writing is 622.08 Mb.
/ S, and reading is performed at 155.52 Mb / s.
The cell speed adjustment buffers 21 and 23 are intended only for speed adjustment and are not expected to have the effect of statistically multiplexing cells. Therefore, the capacity of the cell speed adjustment buffers of at most 2 cells is sufficient. next,
The operation of the cell multiplexing circuit will be described. The cell length handled here is a fixed length and is randomly input. The cell input phase is adjusted before inputting to the input port 6, and cell input from all lines is supplied in the same phase. I shall. FIG. 43 is a timing chart in this circuit example, in which the input port 6 in FIG. 42 is A and the input line 1 is B, and each is shown in cell units. In the ATM communication method, a significant cell may come in a certain time slot and an idle cell (empty cell) having no information may come. In the figure, significant cells are indicated by "cell 1" or the like, and idle cells (empty cells) are specified as "idle cells". 622.0
One cell transfer time at 8 Mb / s is 155.52 M
It is 1/4 of that of b / s, and has a capacity to accommodate all cells input from the input port 6 in the input line 1. Here, one cell time at 155.52 Mb / s is used as a unit, and four cells at 622.08 Mb / s are fixedly assigned to the input port 6 at the time position.
For example, the cell input from the input port 6 of # 1 is
At the position of 1, the output is 622.08 Mb / s.

Next, the operation of the ATM switch will be described with reference to FIG. Here, it is assumed that the input phase of the cell on each input line 1 input to the switch is adjusted and is the same.
When a cell is input to the incoming line 1, the header processing circuit 10 provided corresponding to each incoming line 1 detects the output port and the outgoing line number accommodating the output port from the header portion of the input cell. The write buffer selection circuit 16 in the buffer control circuit 15 refers to the header processing circuit 10 and informs the cell writing circuit 13 of the header processing circuit 10 to which the cell has arrived.
And the selected buffer memory 11 for storing cells are instructed to be individually connected. The write address used at this time is obtained by referring to the storage control circuit 12. This write address is the address exchange circuit 17
Destination output port 7 of the cell sent to each incoming line 1
It is divided according to.

The address queue 18 is provided for each output port, and the write address of the cell and the buffer memory number are written at the end thereof. The read buffer selection circuit 19 takes out the addresses stored therein from these address queues 18 and sends them to the storage control circuit 12 corresponding to the corresponding buffer memory 11, and outputs them to the cell read circuit 14 with the buffer memory 11. Instruct to connect the wires 2 and 2 individually. Generally, the capacity of the output line 2 and the capacity of the output port 7 are different, but the address queue 18 is read in units of output ports. Try not to. The cell read circuit 14 connects the buffer memory 11 and the outgoing line 2 in this time slot. Each storage control circuit 12 sends the received address to the associated buffer memory 11 as a read address, and thereafter manages the address as a free address. The cell read from each buffer memory 11 is output to the outgoing line 2 that accommodates the destination output port 7 designated by the respective header section.

Here, FIG. 46 and FIG. 47 are examples showing in detail the reading of the address queue 18 for the outgoing line # 1. Outgoing line # 1 accommodates output ports # 1 to # 4 of 155.52 Mb / s, so 622.08 Mb
Has a speed of / s. FIG. 46 is an example of the address queue 18 corresponding to the output ports # 1 to # 4 in a certain time slot, and where "cell 11" or the like is indicated, the buffer memory storing that cell is shown. The number and address are written. FIG. 47 shows a read rule of the address queue 18. The same figure shows outgoing line 2
The timing is shown in FIG. 2 and is different from the conventional one in that cells addressed to output ports # 1 to # 4 are fixedly assigned in units of four cells. For example, in the figure, the time slots 1 to 4 are assigned to the output ports # 1 to # 4, respectively, and this is repeated. Therefore, the cell separation circuit 5 only needs to regularly adjust the speed, and cell discard due to a buffer overflow in the cell separation circuit 5 does not occur. For example, in FIG. 46, the cell 11 currently destined for the output port # 1, the cell 21 destined for # 2, and the cell 41 destined for # 4 are currently waiting for output. Therefore, they are regularly read in the time slots 1, 2, and 4. In the time slot 3, since the cell addressed to the output port # 3 has not arrived, the idle cell (indicated as "empty cell" in the figure) is transmitted.

Although the address queue 18 is provided corresponding to the output port 7, it is considered that there is one large queue for the outgoing line 2 in the conventional example. If this example is applied, Since another significant cell is output in time slot 3, no empty cell is output, and any one of output ports # 1, # 2, and # 4 is duplicated, and buffering is performed in cell separation circuit 5. There is a need to. That is, in the conventional example, a statistical fluctuation occurs in the arrival of cells with respect to one output port 7, and a large amount of buffer is required in the cell separation circuit 5.

Next, the operation of the cell separation circuit will be described. FIG. 45 is a timing diagram in this circuit example,
In FIG. 44, the output line 2 is C and the output port 7 is D, which are shown in cell units. In the figure, as in FIG. 43, significant cells are indicated by "cell 1" and idle cells (empty cells) are indicated by "cell 1".
Idle cell ”is specified. 622.08 Mb / s
Transfer time at 155.52 Mb / s, 4 of that
It is one-third. Outgoing line 2 transmitted from ATM switch 3
Is 622.08 Mb / s, but 155.52 Mb /
622.08 Mb /
Since the output port 7 is fixedly assigned to the 4 cells of s at the time position, the output port 7 and the time slot that are always output are guaranteed for the cell input to the cell separation circuit 5, and the buffer overflow here. Does not occur. The cell input to the cell separation circuit 5 is first broadcast to the address filter 22 provided corresponding to the output port 7, and only the address filter 22 corresponding to the corresponding output port 7 allows the cell to pass and the speed adjustment buffer. Two
Write to 3. The other address filter 22 discards the cell. The cell speed adjustment buffer 23 performs writing at 622.08 Mb / s and reading at 155.5.
The speed is adjusted by performing the operation at 2 Mb / s. Since the cell speed adjustment buffer 23 is intended only for speed adjustment and does not expect statistical multiplexing effect of cells, its capacity is at most 2.
A cell amount is enough.

However, in the above-mentioned case, there is a problem that a large-scale switch cannot be constructed because only one stage of the switch is considered. Also, the implementation of the broadcast function was not mentioned.

Conventional example 4. For the system that accommodates high-speed interface compared with the input and output lines of ATM switch, "Development of common buffer type ATM switch LSI with broadcast function" (IEICE, IEICE SSE)
92-169, 1993. ) Is disclosed.

As shown in FIG. 48, a 2.4 Gb / s line is accommodated by connecting DMUX to input lines # 0 to 3 of the unit switch and connecting MUX to output lines # 0 to 3 of the unit switch. This time,
In the unit switch, cells for outgoing lines # 0 to # 3 are queued in one address queue to manage the order of cells. Further, the DMUX outputs the cells to the incoming lines # 0 to 3 in order from the first received cell, and the MUX sends the cells to the line in the order of outgoing lines # 0 to 3, whereby the cell order can be maintained. In addition, input / output lines # 4 to 7 may be connected to this, and this includes 600 Mb / s 4 lines or 150 lines.
Either of the Mb / s 16 lines can be selected and accommodated.

However, there is a problem in that a large-scale switch cannot be constructed because only one switch is considered.

[0023]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is possible to make the unit switch multi-staged and to expand the scale, and at the same time efficiently handle broadcast data. The purpose is to obtain a data exchange device that can.

It is another object of the present invention to provide a data exchange device which has a multi-stage unit switch, can be expanded in scale, and can accommodate a plurality of low speed interfaces.

It is another object of the present invention to provide a data exchange apparatus which has a multi-stage unit switch, can be expanded in scale, and can accommodate a high speed interface.

[0026]

A data exchange apparatus according to a first invention comprises a plurality of input ports and a plurality of output ports, and a plurality of input lines are provided between the plurality of input ports and the plurality of output ports. In a data exchange device in which a plurality of unit switches for exchanging data between a plurality of output ports and a plurality of output lines are arranged in at least two stages and data is exchanged between a plurality of input ports and a plurality of output ports, If the unit switch is the first unit switch, the unit switches of the second and subsequent stages are the second unit switches, and a plurality of first unit switches are necessary for the broadcast data input from a certain input port, if necessary. The broadcast data is copied and exchanged, and the plurality of copied broadcast data are output to the output lines corresponding to the output ports of the broadcast destination. And input the copied broadcast data output from the output lines of the unit switches in the preceding stage and exchange the copied broadcast data based on a predetermined rule. It is characterized in that it has a multi-stage connecting portion characterized in that it is output to the output port of the broadcast destination.

A data exchange device according to a second aspect of the invention is provided with a plurality of the multistage connection parts, and the data input to the input port is branched and input into the plurality of the multistage connection parts, and the multistage connection parts are different from each other. It is characterized by assigning output ports.

In the data exchange device according to the third aspect of the present invention, the first unit switch has a table that defines a plurality of outgoing lines to which each broadcast data is to be output, and the broadcast data can be obtained by referring to the table. Is provided with a broadcast processing means for determining the outgoing line to be output and exchanging the broadcast data for copying.

In the data exchange device according to the fourth aspect of the present invention, the second unit switch outputs the copied broadcast data based on the input line number of the input line for inputting the copied broadcast data. It is characterized by determining.

A data exchange device according to a fifth aspect of the present invention is a cell exchange device for exchanging a cell having a virtual path identifier and a virtual channel identifier, and the table above shows the virtual path identifier and the virtual channel identifier. Define multiple outgoing lines that should output broadcast cells to the Tiffer,
The first unit switch determines the outgoing line to be broadcast from the table based on the virtual path identifier and virtual channel identifier of the broadcast cell.

In the data exchange apparatus according to the sixth aspect of the present invention, the table is provided for each first unit switch.
The feature is that they are provided independently of each other.

In the data exchange apparatus according to the seventh aspect of the invention, the table is commonly provided for the plurality of first unit switches.

A data exchange apparatus according to an eighth aspect of the present invention is a cell exchange apparatus for exchanging cells, and the cell exchange apparatus assigns a broadcast identifier for identifying a broadcast cell to each broadcast cell in the preceding stage of an input port. A broadcast identifier is assigned to the broadcast identifier, and the first unit switch should broadcast from the table based on the broadcast identifier. Characterized by determining the outgoing line.

In the data exchange apparatus according to the ninth aspect of the invention, the broadcast identifier assigning means is provided for each incoming line group consisting of a plurality of the input ports.

A data exchange apparatus according to the tenth invention is
An output port accommodating a plurality of low speed interfaces is provided, and the first unit switch performs copy and exchange of broadcast data corresponding to the plurality of low speed interfaces,
The second unit switch outputs the broadcast data corresponding to the plurality of low speed interfaces to an output port accommodating the plurality of low speed interfaces.

A data exchange apparatus according to the eleventh invention is
Further, a separation circuit connected to a subsequent stage of at least one of the output ports, connecting a plurality of low speed interfaces, separating the data output from the output ports and outputting the separated data to the low speed interface, and the separation circuit. The first unit switch includes timing generation means for generating an identification timing for operating the first unit switch and the second unit switch at a common timing, and the first unit switch is an output port to which the separation circuit is connected. For the output line corresponding to the above, a plurality of queues for storing output data for each low-speed interface and a plurality of output lines to which each broadcast data is to be output are defined. A table that defines the low-speed interface that should output broadcast data when the outgoing line is connected, and By referring to the table,
Determine the low speed interface that should output the broadcast data,
The second unit switch includes the broadcast processing means for storing the broadcast data in a queue corresponding to the corresponding low-speed interface, and a selector for controlling the order of outputting the data from the queue according to the identification timing. Corresponding to the output line corresponding to the output port to which the separation circuit is connected, a plurality of queues for storing the data to be output for each low-speed interface and the low-speed interface to which the data input from the input line should be output at the above identification timing. It is characterized in that it is provided with a distribution circuit for distributing to the queue and a selector for controlling the order of outputting data from the queue according to the identification timing.

A data exchange apparatus according to the twelfth invention is
At least one high-speed interface is provided with a plurality of output ports, the first unit switch performs copy and exchange of broadcast data corresponding to the high-speed interface, and the second unit switch has the high-speed interface. The broadcast data corresponding to the interface is output to a plurality of output ports accommodated in the high speed interface.

A data exchange apparatus according to the thirteenth invention is
A multiplexer circuit connected to the latter stage of the plurality of output ports to connect the high speed interface, and multiplexing the data output from the plurality of output ports and outputting the multiplexed data to the high speed interface; and the first unit switch. And the second unit switch has one queue for storing data for a plurality of outgoing lines corresponding to a plurality of output ports connected to the multiplex circuit, and the order stored in the queue It is characterized by outputting data to each outgoing line.

[0039]

The data exchange device according to the first aspect of the present invention comprises a plurality of first unit switches and a plurality of second unit switches. The data exchange device includes a multi-stage connection section in which a plurality of first unit switches are arranged in the first stage and a plurality of second unit switches are arranged in the second stage and thereafter. The input line of the first unit switch is connected to the input port, and if necessary, the broadcast data is copied. Then, each of the plurality of copied broadcast data is output to the outgoing line corresponding to the output port of the broadcast destination.
The second unit switch is arranged in the second and subsequent stages. The second unit switch arranged in the second stage inputs the copied broadcast data from the plurality of first unit switches in the preceding stage. Then, the outgoing line is determined based on a predetermined rule. If there is a third step, a fourth step, etc., the second unit switch inputs the copied broadcast data from the second unit switch in the previous step, and outputs the line based on a predetermined rule. To decide. The output line of the second unit switch at the final stage is connected to the output port and outputs the copied broadcast data to the output port of the broadcast destination. By using a plurality of first unit switches, the number of input ports that can be connected to the data exchange device can be increased.

The data exchange device according to the second aspect of the invention comprises a plurality of multi-stage connection sections in which a plurality of first unit switches and second unit switches are connected in multiple stages. The data input to the input port is branched and input to the plurality of multistage connection units. Then, different output ports are assigned to the multi-stage connection section. This can increase the number of output ports that can be connected to the data exchange device.

In the data exchange device according to the third aspect of the invention, the first unit switch is provided with a table defining a plurality of outgoing lines to which each broadcast data is to be output. The broadcast processing means of the first unit switch refers to the table to determine the outgoing line to which the broadcast data should be output, and exchanges the broadcast data for a copy.

The data exchanging device according to the fourth aspect of the present invention uses the input broadcast data, which has been copied, as input,
It has a second unit switch that determines the outgoing line to be output. Therefore, the second unit switch does not need to have a table for determining the outgoing line of the input data.

The data exchange device according to the fifth aspect of the present invention is a cell exchange device for exchanging a cell having a virtual path identifier and a virtual channel identifier. The table provided in the first unit switch defines a plurality of outgoing lines from which broadcast cells should be output to the virtual path identifier and the virtual channel identifier. Thus, the first unit switch can determine the outgoing line to be broadcast from the table based on the virtual path identifier and virtual channel identifier of the broadcast cell.

The data exchange device according to the sixth aspect of the present invention independently comprises a table for determining the destination outgoing line for each first unit switch. Therefore, since the table only needs to be the broadcast data input from the input ports connected to the respective first unit switches, the size of the table can be reduced.

In the data exchange device according to the seventh aspect of the present invention, one table can be shared by a plurality of first unit switches for use. Alternatively, all the first unit switches can use one table.

The data exchange apparatus in the eighth invention is a cell exchange apparatus for exchanging cells. The cell exchange has a broadcast identifier assigning means. The broadcast identifier allocating means is connected to the front stage of the input port and allocates a broadcast identifier for identifying a broadcast cell to each broadcast cell. The above table also defines the outgoing line from which the broadcast cell should be output for the broadcast identifier. The first unit switch determines the outgoing line to be broadcast from the table based on the broadcast identifier.

In the data exchanging device according to the ninth aspect of the invention, the input port is divided into several input line groups. Broadcast identifier assigning means is provided for each incoming line group. Therefore, the number of broadcast identifiers that need to be registered in the table may be the broadcast data input from the input ports belonging to the corresponding incoming line group. Therefore, the size of the table can be reduced.

A data exchange device according to the tenth invention is
The output port can accommodate multiple low speed interfaces. The first unit switch performs copy and exchange of broadcast data corresponding to the case where the output port has a plurality of low speed interfaces. The second unit switch outputs broadcast data corresponding to the plurality of low speed interfaces.

A data exchange device according to the eleventh invention is
A low speed interface can be accommodated in the latter stage of the output port. The low speed interface is connected to the output port of the data exchange device via the isolation circuit. The data exchange device also includes a timing generation means. The timing generating means generates an identification timing for operating the separation circuit, the first unit switch and the second unit switch at a common timing. The first unit switch has a plurality of queues for storing, for each low speed interface, data to be output to the output line corresponding to the output port connected to the separation circuit. The table provided in the first unit switch defines a plurality of outgoing lines from which broadcast data should be output. Further, when the outgoing line is an outgoing line connecting the low speed interface, a low speed interface for outputting broadcast data is defined. The broadcast processing means of the first unit switch refers to the table, determines the low speed interface to which the broadcast data should be output, and stores the broadcast data in the queue corresponding to the low speed interface. When outputting data from a plurality of queues corresponding to the low-speed interface, the selector controls which queue the data is output from according to the identification timing. The second unit switch has a plurality of queues for storing data to be output for each low speed interface when the output line corresponds to the output port to which the separation circuit is connected. It has a distribution circuit that distributes the data input from the incoming line to a queue corresponding to the low-speed interface at the identification timing. The selector of the first unit switch and the distribution circuit of the second unit switch are controlled by the same identification timing. As a result, the data stored in the queue corresponding to one low-speed interface of the first unit switch is stored in the queue corresponding to the same low-speed interface of the second unit switch. That is, by giving the same identification timing, between the first unit switch and the second unit switch,
Can be synchronized. Further, a selector is provided for controlling the order of outputting data from the queue corresponding to the low-speed interface according to the identification timing. Since the selector of the second unit switch and the separation circuit are controlled at the same identification timing, when the separation circuit separates the data for each low speed interface, the data is correctly output to the destination low speed interface. By providing the selectors on the first and second unit switches, compared to the output from the queue corresponding to the normal outgoing line,
The number of times data is output from a plurality of queues stored for each low-speed interface is small. Therefore, cell discard due to buffer overflow in the separation circuit can be eliminated.

A data exchange device according to the twelfth invention is,
The output port contains at least one high speed interface. One high speed interface is connected to a plurality of output ports. The first unit switch performs copy and exchange of broadcast data corresponding to the high speed interface. Second
The unit switch can output broadcast data corresponding to the high speed interface to a plurality of output ports accommodated in the high speed interface.

A data exchange apparatus according to the thirteenth invention is
A multiplex circuit is connected after the output ports, and a high-speed interface is connected after this multiplex circuit. The multiplexing circuit multiplexes data output from a plurality of output ports. The first unit switch and the second unit switch have one queue for storing data for a plurality of output lines corresponding to a plurality of output ports connected to the multiplex circuit. Data is output to each output line in the order stored in the queue.

[0052]

【Example】

Example 1. In this embodiment, an example of a method for expanding a scale by forming a unit switch in a multi-stage configuration to configure a large-scale ATM switch will be described. The connection form described in this embodiment is based on the connection method described in the conventional example 2, but is a concentrated linear connection method in which the functions of the switches in the first stage and subsequent stages are different. For example, when two-stage connection is made, cells are copied and exchanged by the first-stage unit switch, and the second-stage unit switch determines the destination from the incoming line number information input by the cell.

In FIG. 1, the number of incoming lines is 8 and the number of outgoing lines is 2 (hereinafter 8
An example will be shown in which unit switches of (× 2) are connected in two stages to form a large-scale switch having 32 input ports and 32 output ports (hereinafter referred to as 32 × 32). In FIG. 1, S1-1 to S1-4 are 8 × 2 first unit switches. T-1 to T-4 are destination bit map tables defining a plurality of outgoing lines for outputting broadcast cells. S2
-1 is an 8 × 2 second unit switch. In addition, in the following embodiments, regarding the incoming lines of the first unit switch S1 and the second unit switch S2, the incoming line numbers i (i = 0, 1,
2, ...) is called an incoming line i, and an outgoing line of an outgoing line number outgoing line i is called an outgoing line i (i = 0, 1, 2, ...). First
The input lines of the unit switch S1-1 of No. 2 are connected to the input ports # 0 to # 7, respectively. Similarly, the first unit switch S
1-2, S1-3, and S1-4 are # 8 to # 15 and # 16 to.
# 23 and # 24 to # 31 are respectively connected. Further, the outgoing lines 0 and 1 of the first unit switch S1-1 are connected to the incoming lines 0 and 1 of the second unit switch S2-1, respectively, from above. Similarly, the other first unit switches S1-2, S1-
Outgoing lines 0 and 1 of S3 and S1-4 are connected to incoming lines 2 and 3, 4, 5 and 6 and 7 of the second unit switch S2-1, respectively. The two outgoing lines 0 and 1 of the second unit switch S2-1 are connected to the output ports # 0 and # 1. Further, the first unit switches S1-1 to S1-4 respectively include destination bitmap tables T-1 to T-4. The first unit switch S1-1 determines the destination bitmap table T- from the header information of the broadcast cells input to the input ports # 0 to # 7.
1 to determine a plurality of destinations. If there are two or more destinations, the broadcast cell is copied and the cell is output to the output line indicated in the destination bitmap table T-1. The second unit switch S2-1 determines the destination using the incoming line number. Therefore, the destination bitmap table is unnecessary.

P-1 to P-16 are multistage connecting portions. The multi-stage connection parts P-1 to P-16 include the first unit switch S1.
4 and one second unit switch S2, which is composed of a group of unit switches connected in multiple stages in a concentrated line. Multi-stage connection P
Signals from the input ports # 0 to # 31 are branched and input to -1 to P-16. That is, the multistage connecting portion P-1
And the multistage connection parts P-2 ... P-16 are the input ports # 0.
The same cell is input from # 31. Multi-stage connection P-
The output ports # 0 and # 1 are assigned to 1, and the output ports # 2 and # 3 are assigned to the multistage connection unit P-2.
In this way, the multistage connection unit P allocates 32 input ports and 2 output ports (32 × 2). And 16
By assigning two different output ports to each of the multistage connection parts P, it is possible to provide a total of 32 output ports. With the above configuration, it is possible to configure a large 32 × 32 switch by using a plurality of 8 × 2 unit switches.

FIG. 2 is a block diagram of the first unit switch S1. In the figure, the constituent elements having the same numbers as those of the conventional example 3 have the same functions, and therefore their explanations are omitted. Reference numeral 131 is a header processing circuit. The header processing circuit 131 holds the cell that arrived at the incoming line and reads the header information of the cell. The write buffer selection circuit 111 includes a header processing circuit 131.
The header information of the cell read by is received and the destination, that is, the outgoing line number is determined by referring to the destination bitmap table T. If there is no destination, the cell is discarded and no further processing is performed. When there are one or more destinations, the write buffer selection circuit 111 uses the buffer memory 11 for storing cells.
Is selected and the header processing circuit 131 and the buffer memory 11 are connected by switching control of the cell writing circuit 13.

A1-0 and A1-1 are address queues. The address queue A1 is provided corresponding to the outgoing line and is composed of a FIFO type memory. Address queues A1-0 and A1-1 correspond to outgoing lines 0 and 1, respectively. The write address (address) of the buffer memory 11 in which the cell output to the output line 0 is stored is
The addresses are written in the order of arrival by the address exchange circuit 120 described later. Here, when there are a plurality of outgoing lines of the broadcast destination, the address of the corresponding cell is written in the plural address queue corresponding to the outgoing line.

The address exchange circuit 120 writes the address of the buffer memory 11 in which the cells to be output to the corresponding output line are stored in the address queue A1 corresponding to the output line number.
The address of the buffer memory 11 is
Is obtained by the storage control circuit 12 corresponding to. The output line number is obtained from the write buffer selection circuit 111. The broadcast processing means 105 includes a write buffer selection circuit 111, an address exchange circuit 120, an address queue A1, a read buffer selection circuit 19, and a destination bitmap table T.

Next, the operation of the first unit switch S1 will be described with reference to FIGS. FIG. 3 is a diagram showing an operation example in the first unit switch S1-1. Input lines 0 to 7 of the first unit switch S1-1 are input ports # 0, respectively.
~ Assign # 7. The output lines 0 and 1 are finally output to the output ports # 0 and # 1, respectively, via the second unit switch S2-1. The write buffer selection circuit 111 is
From the header information of the broadcast cell to the destination bitmap table T
The destination to be output is determined by -1. The destination bit map tables T-1 to T-4 are in a bit map format for instructing a plurality of destination outgoing lines with respect to the value of the header information of the broadcast cell (each bit corresponds to the outgoing line of the switch, and the value of the bit is If "0", cell output is not performed, and if the bit value is "1", cell output is specified).

Further, the multistage connection section P-0 to which the first unit switch S1-1 belongs is
Since 0 and # 1 are allocated, the destination bitmap table T-1 has only to have information about whether or not to finally output to the output ports # 0 and # 1 for the broadcast destination of the broadcast cell. Good. Therefore, the size of the destination bitmap table T-1 does not need to have data of all the output ports # 0 to # 31, so that the storage capacity for the destination bitmap table T-1 can be reduced. is there.
Further, since the header information that is the target of the destination bitmap table T-1 is only the header information of the broadcast cells input to the input ports # 0 to # 7, the input ports # 0 to # 3.
It is not necessary to have header information that may be entered in 1. Therefore, the size of the destination bitmap table may be smaller than when all input ports are considered. Moreover, since the size of the destination bitmap table T-1 is small, there is an advantage that the search time is short. Also,
Since the size of the destination bitmap table T can be made small, it becomes possible to store it in the RAM and store it in the first unit switch.

The operation in the first unit switch S1-1 when the broadcast cells having the header information a and b are input from the input ports # 0 and # 5 will be described. The header processing circuit 131 connected to the input port # 0, that is, the incoming line 0 checks the header information of the input broadcast cell, obtains the header information a, and notifies the write buffer selection circuit 111. The write buffer selection circuit 111 refers to the destination bitmap table T-1 and determines that the output line 1 is the destination because the bit of the output line 1 is “1”. Address exchange circuit 12
0 indicates the output line number from the write buffer selection circuit 111 and the buffer memory 11 in which the corresponding cell is written.
Is obtained from the storage control circuit 12. The address exchange circuit 120 uses the address queue A1 corresponding to the outgoing line 1.
Write the corresponding address in -1.

Next, the header processing circuit 131 checks the header information of the broadcast cell input from the input port # 5, and b
Get. The write buffer selection circuit 111 refers to the destination bitmap table T-1 from the header information b and determines that the destinations are outgoing lines 0 and 1. Address exchange circuit 1
20 is an address queue A1-corresponding to outgoing lines 0 and 1.
Write addresses to 0 and A1-1. One cell of the corresponding cell is stored in the buffer memory 11, and the address is written in the two address queues corresponding to the outgoing line. As a result, the usage amount of the buffer memory 11 used can be reduced and the destination outgoing line can be managed. The read buffer selection circuit 19 includes address queues A1-0 and A1-
Addresses are sequentially read from 1 by the FIFO. In the case of FIG. 3, the address of the cell whose header information is b (hereinafter referred to as cell b) is read from the address queue A1-0 and sent to the storage control circuit 12 associated with the corresponding buffer memory 11. Then, the switching of the cell read circuit 14 is controlled to read the cell b from the corresponding buffer memory 11 to the output line 0. Next, the same processing is performed for the cell a in the address queue A1-1, and the result is output to the output line 1. The read buffer selection circuit 19 again determines the address queue A1.
-0 is read, but since there is no cell to read, an idle cell is output to the output line 0. Next, the read buffer selection circuit 19 reads the address queue A1-1 again and outputs the cell b to the output line 1. At this time, the address of the buffer memory 11 storing the cell b is released. The release timing of the used address is realized by a method using a broadcast cell counter (reference: Japanese Patent Laid-Open No. Hei 0).
No. 4-175034).

FIG. 4 is a diagram showing an operation example in the first unit switch S1-3. First unit switch S1-
Input ports # 16 to # 23 are connected to eight incoming lines of the cable 3. Outgoing line is 0, 1 is the second unit switch S
It corresponds to the output ports # 0 and # 1 via 2-1. Since the destination bitmap table T-3 corresponds to the same output ports # 0 and # 1 as the destination bitmap table T-1, it may be a table having the same value. However, since the corresponding input port is different, the destination bitmap table T
-1 and T-3 may be tables for different header information. Further, for example, as shown in FIGS. 3 and 4, the value of the outgoing line for the same header information d may be changed. Since the destination bitmap table T is divided and held for each first unit switch S1, not only the size of the destination bitmap table T can be reduced, but also different values can be given. In addition, since the table is divided and partially modified in the destination bitmap table T,
It can be done easily.

In FIG. 4, the first unit switch S1-
It is assumed that a broadcast cell is input to input port 3 from input ports # 17, # 20, and # 22. The first unit switch S1-3 checks the header information of the input broadcast cell, and the header information is c
In case of, the destination cell is found out from the destination bitmap table T-3, and the input cell is discarded. Also,
Header information c in the destination bitmap table T-3
Since the destination regarding 0 is 0, the data regarding the header information c may be omitted. In that case, the input cell may be discarded assuming that the destination bitmap table T-3 does not have information regarding the header information c. However, in this embodiment, the information regarding the header information c is registered in consideration of the later change. The broadcast cell having the header information b determines that the outgoing lines to be output from the destination bitmap table T-3 are 0 and 1. Then, the cell b is stored in the buffer memory 11, and its address is output line 0,
Write to the address queue A1-0, A1-1 corresponding to 1. The same processing is performed for a cell whose header information is d.

FIG. 5 is a diagram showing an example of the operation of the first unit switch S1-63. First unit switch S1
-63 has the same input ports # 16 to # as S1-3.
Twenty-three cells are input. In addition, the first unit switch S1
Reference numeral -63 is a switch belonging to the multistage connection unit P-16. Therefore, the output line 0 of the first unit switch S1-63,
1 corresponds to the output ports # 30 and # 31 via the second unit switch S2-1. In the destination bitmap table T-63, the broadcast cell finally outputs the output ports # 30 and #.
Whether to output to 31 is specified in the bitmap format. The first unit switch determines the destination of the input broadcast cells b, c, d by referring to the destination bitmap table T-63. The broadcast cells c and d output to the outgoing line 0. Broadcast cell b outputs to output line 1.

FIG. 6 is a block diagram of the second unit switch S2. Only components different from those in FIG. 2 will be described. The header processing circuit 132 holds the cell that has arrived from the unit switch in the previous stage, checks the header information, and determines whether or not the cell is an idle cell. In the case of an idle cell, no further processing is performed. If it is not an idle cell, the incoming line number is notified to the write buffer selection circuit 112. The write buffer selection circuit 112 determines the outgoing line number from the notified incoming line number. Address queue A2 is similar to address queue A1.

FIG. 7 is a diagram for explaining the operation of the second unit switch S2. The second unit switch uses the incoming line number to determine the destination. Therefore, the destination bitmap table T is unnecessary. In the example shown in FIG. 7, the destination of the cell arriving at the second unit switch S2-1 is the remainder obtained by dividing the incoming line number by the outgoing line number of the second unit switch. In this case, there are eight incoming lines of the second unit switch S2-1, and the incoming line numbers are 0 to 7. Lines 0 and 1 are first
Is connected to the unit switch S1-1. Entry lines 2 and 3
Is connected to the first unit switch S1-2, the input lines 4 and 5 are connected to the first unit switch S1-3, and the input lines 6 and 7 are connected to the first unit switch S1-4. However, if the connection method of the outgoing line of the first unit switch and the incoming line of the second unit switch is changed, the outgoing line of the second unit switch can be determined by another method. For example, the first unit switch S1-
1 to S1-4 output line 0 to the second unit switch input line 0 to
Connect to 3. First unit switches S1-1 to S1-4
Output line 1 is connected to the input lines 4 to 7 of the second unit switch. In this case, how to decide the outgoing line by the number of incoming line is the second
The cells arriving at the input lines 0 to 3 of the unit switch may be output to the output line 0, and the cells arriving at the input lines 4 to 7 may be output to the output line 1. The output lines 0 and 1 of the second unit switch S2-1 are connected to the output ports # 0 and # 1. The address queue A2-0 stores the address of the cell waiting for output to the output line 0, that is, output line # 0. The address queue A2-1 stores the addresses of cells waiting to be output to the output line 1.

For example, the header processing circuit 132 determines whether the cell arriving at the incoming line 2 is an idle cell. If it is not an idle cell, the input line number 2 is notified to the write buffer selection circuit 112. Write buffer selection circuit 1
12 calculates the remainder 0 by dividing the cell input line number 2 by the number of output lines 2 and determines that the destination output line is 0. The write buffer selection circuit 112 switches the header write circuit 132 and the buffer memory 1 by switching the cell write circuit 13.
1 is connected and the corresponding cell is stored in the buffer memory 11. The address exchange circuit 120 is notified of the destination output line number from the write buffer selection circuit 112, and is notified of the address of the buffer memory 11 in which the cell is stored from the storage control circuit 12. The address exchange circuit 120 writes the address to the address queue A2-0 corresponding to the output line 0. On the other hand, the read buffer selection circuit 19 reads from the head address of the address queue A2-0 and notifies the storage control circuit 12 of it. Then, the switching of the cell read circuit 14 is controlled, and the buffer memory 1
1 is connected to the output line 0, and the cell of the corresponding address is output to the output line 0, that is, the output port # 0. The cells arriving at the incoming lines 0, 4, and 6 are output to the outgoing line 0 through the same processing. The cells arriving at incoming lines 1, 3, 5, and 7 are output to outgoing line 1.

As described above, the second unit switch S2 is characterized in that the fixed routing processing is performed according to the incoming line number, and the destination bitmap table T is unnecessary. For this reason, the total amount of the destination bitmap table T can be reduced in the entire switch in which the unit switches are configured in multiple stages. Another feature is that cell discard is eliminated by assigning addresses of a plurality of cells to be output to the address queue A2 corresponding to the same output port. In this embodiment, the destination of the arriving cell is the remainder obtained by dividing the incoming line number by the number of outgoing lines, but the destination may be determined by another method as described above. Although the second unit switch S2-1 in the multi-stage connection portion P-1 has been described above as an example, the second unit switch in the other-stage connection portion also has the same function. For other multi-stage connections,
The difference is that the assigned output ports are different.

In the three-stage connection of Conventional Example 1, the destination bitmap table is arranged in each unit switch of each stage. However, in this embodiment, the destination bitmap table is placed only in the first unit switch in the first stage. The second unit switch is characterized in that the destination of the arriving cell is subjected to fixed routing processing by its incoming line number. Therefore, the destination bitmap table is not required for the second unit switch. Therefore, the total amount of the destination bit map table can be reduced in the entire multi-stage switch. Moreover, since each unit switch has a destination bitmap table, it is possible to specify different destinations for the same header information in each table. Further, since the destination bitmap table can be replaced for each unit switch, the destination management of the broadcast cell can be performed more flexibly. In this way, the first with a small number of incoming and outgoing lines
It is possible to connect a large number of input ports by combining a number of unit switches of. In addition, a large number of output ports can be associated with each other by using a plurality of multi-stage connection units each composed of a plurality of unit switches and assigning different output ports to each.

The priority control can be used in each unit switch in the same manner as in the case of a single unit switch without a multistage configuration.

Example 2. This embodiment shows an example in which m × n unit switches are connected in two stages to form an M × N large-scale switch.

FIG. 8 shows a case in which m × n unit switches are used and 2
It is a block diagram of M * N switch by stage connection. In the figure, the number of input ports is M. The first unit switch S1 has m input lines and n output lines. Therefore, the number of input ports M is m and the first unit switch S is m.
1-1 to S1-M / m. The second unit switch S2 has m input lines and n output lines. The multistage connecting portion P has M input ports and n output ports. The number of output ports is N. Multi-stage connection parts P-1 to P-N / n
Connect N output ports by sharing each N ports. First
A destination bitmap table T is prepared for each unit switch S1. Since the second unit switch S2 obtains the destination of the cell that has arrived from the incoming line number, the destination bitmap table T is unnecessary. The functions of the first unit switch S1 and the second unit switch S2 are the same as those in the above embodiment except that the numbers of incoming lines and outgoing lines are different. Also,
The destination bitmap table is the same as in the above embodiment.

Here, the number of the first unit switches S1 is M
/ M, but if M cannot be divided by m, round up to the decimal point. M / m first unit switches S
Since n output lines of 1 are connected to m input lines of the second unit switch S2, a relationship of m ² = nM is established between M, m, and n. The number of multi-stage connection parts P is N / n. Here, when N cannot be divided by n, the number of decimal points is rounded up.

FIG. 9 shows the first unit switch S in FIG.
It is a figure which shows the operation example of 1-1. FIG. 9 is almost the same as the first unit switch S1-1 in FIG. 3 of the above embodiment. The difference is that the number of incoming lines has changed from 8 to m, and the number of outgoing lines has changed from 2 to n. Destination bitmap table T according to the input cell header information x, y
-1 is referred to and the output line to be output is determined.

FIG. 10 is a diagram showing an operation example in the second unit switch. The second unit switch S2-1 is
It has m incoming lines and n outgoing lines. Of the m incoming lines, n incoming lines 0 to (n-1) are connected to the outgoing lines of the first unit switch S1-1. The n output lines of the second unit switch S2-1 are connected to the output ports # 0 to # (n-1), respectively. Similar to the above-mentioned embodiment, the destination of the cell arriving at the second unit switch S2 is the remainder obtained by dividing the incoming line number by the outgoing line number n. Also,
Address queues A2-0 to A2-corresponding to each outgoing line
(N-1) is provided. The operation of the M × N switch using the m × n unit switch is the same as that of the above-mentioned embodiment, and therefore its explanation is omitted.

Example 3. In this embodiment, an example will be described in which the first and second unit switches are connected in three stages to form a multi-stage connection portion P. FIG. 11 shows three m × n unit switches.
It is a block diagram of a KxL switch when using multiple stages. In the figure, there are K input ports. There are L output ports. The feature of the three-stage configuration is that the first unit switch S1 is used for the switch of the first stage and the second unit switch S2 is used for all of the second and subsequent stages. Therefore, the first stage of the first stage
Destination bit map table T only for the unit switch S1 of
Should be provided. The second unit switch S2 used in the second and third stages determines the outgoing line from the incoming line number.

In the figure, the portion Q surrounding the combination of the first-stage and second-stage unit switches has the same structure as the two-stage connection multi-stage connecting portion P shown in FIG. In this way, in the case of the concentric connection of the three-stage configuration, a plurality of switch groups combined like Q of the first stage and the second stage are collected.
A plurality of output lines n of the second unit switch of the second stage are gathered,
It is connected to m incoming lines of the second unit switch S2 in the third stage. As described above, the multistage connecting portion P in the case of the three-stage configuration is configured. The number of multi-stage connection parts P is L / n. However, L
The number after / n is rounded up. Since different output ports are assigned to the respective multistage connection parts P, it is possible to correspond to L output ports.
The difference from the three-stage connection described in Conventional Example 1 is that the number of unit switches in the second stage is smaller than that in the first stage, and the number of unit switches in the third stage is smaller than that in the second stage. In this, only the first unit switch S1 used in the first stage has the broadcast cell destination determination function, and the cell is copied if necessary. The second unit switch used in the second and subsequent stages is that the cell destination can be determined from the incoming line number. Therefore, the destination bitmap table T may be provided only in the first unit switch S1 used in the first stage. Further, although the three-stage configuration is shown in FIG. 11, the number of stages can be increased.

Next, the number of input ports and output ports in the case of the three-stage configuration and the number of the two-stage configuration will be compared. The first and second unit switches have m = 32 and n = 8, four first unit switches S1 are used, and the number of input / output ports M = N = 128.
It is based on the case. When this two-stage configuration is expanded to a three-stage configuration, the number of input / output ports is K = L = 512. Generally, in the i-stage configuration, the number of input / output ports = 3
It becomes 2 × 4 ^(i-1) . As described above, by further combining the basic configuration of the first unit switch S1 and the second unit switch S2 by the concentric connection, it is easy to increase the input ports and the output ports. That is, the existing configuration can be easily expanded without impairing it.

As described above, in this embodiment, the case where the first and second unit switches are connected in three stages and the case of the multistage configuration is mainly described. By using the first unit switch S1 in the first stage and the second unit switch S2 in the second and subsequent stages, it is possible to handle a large number of input ports and output ports. In addition, the number of input ports and output ports can be easily expanded without impairing the current configuration.

Example 4. This example describes one example of introducing a broadcast call number to identify the destination of a broadcast cell.

FIG. 12 is a diagram showing the construction of an M × N switch based on a concentric connection when defining a broadcast call number for each incoming line group. In the figure, the broadcast identifier assigning means D is placed in the preceding stage where the input port is branched to the multi-stage connecting section P. When the input cell is a broadcast cell, the broadcast identifier assigning means D assigns a broadcast call number based on the header information. The other constituent elements are the same as those described in the above-mentioned embodiment shown in FIG. Further, in Conventional Example 1, it has been shown that the broadcast number is introduced in the entire device to reduce the destination bitmap table amount. If this idea is directly applied to the centralized connection, the efficiency of the destination bitmap table T is low. Therefore, as shown in FIG. 12, a plurality of incoming lines accommodated by the first unit switch S1 are set as an incoming line group, and the broadcast number is defined by using this as a unit. Since the first unit switch S1 targets a specific input port, it is more efficient to use the destination bitmap table T when defining the broadcast call number for each incoming line group than when defining the broadcast call number for the entire device. Is good.

The broadcast call number assigned by the broadcast identifier assigning means D is added to the cell as an extra header as shown in FIG. Alternatively, it may be given by a separate line as shown in FIG.

FIG. 15 is a diagram showing an operation example in the first unit switch S1-1. In the figure, the cells input to the input ports # 0 and # (m-2) are broadcast cells, and extra headers are added to the cells. The header processing circuit 131 checks the extra header of the cell input to the input port # 0 and obtains the broadcast call number Y. The write buffer selection circuit 111 refers to the destination bitmap table T-1 by the broadcast call number Y and outputs the output lines 1 and (n
It is determined that -1) is the destination. Input port # (m-
The broadcast cell input from 2) similarly knows the destination based on the broadcast call number Z attached to the extra header. Also, the extra header is excluded when outputting from the first unit switch S1. Alternatively, the extra header may be used to add other information.

As described above, in this embodiment, one embodiment in which the broadcast call number is introduced has been described. When inputting the broadcast number, the plurality of input ports accommodated by the first unit switch S1 are set as an incoming line group, and the broadcast number is defined by using this as a unit. However, the method of allocating the input line groups may be such that the input ports corresponding to the plurality of unit switches are made into one input line group. In this case, the broadcast identifier assigning means D
Has corresponding input ports corresponding to the plurality of unit switches. As described above, by dividing the plurality of input ports into the incoming line groups and introducing the broadcast call numbers to the incoming line groups, the use efficiency of the destination bitmap table is further improved.

Example 5. In this embodiment, as header information, a virtual path identifier / virtual channel identifier (VPI /
An example of referring to the VCI) value will be described.

When the VPI / VCI value in the header is directly referred to, the broadcast identifier assigning means D of the above embodiment is not required, and the hardware scale of the entire apparatus can be reduced.
An example of the destination bitmap table T at this time is shown in FIG. In the case of the conventional example 1, the VPI / VCI value in the header cannot be directly referenced. Because VPI /
Since the VCI value is defined for each incoming line, the same VPI / VCI value may be used for different incoming lines. Therefore, in the first conventional example, the second-stage switch and the third-stage switch cannot determine from which incoming line the cell arrived when only the VPI / VCI is used. Therefore, when determining the destination bitmap table T, the incoming line information is also added. Because it must be. However, in the data exchange device shown in the above embodiment, only the first unit switch S1 refers to the destination bitmap table T. Further, the first unit switch S1 is connected to the input port. Therefore, the output line can be determined by referring to the destination bitmap table T from the VPI / VCI value and the input port number in the first unit switch S1.

Example 6. In this embodiment, the capacity of the destination bitmap table T is set in the three-stage connection of the conventional example 1,
The case of the concentrated connection described in the above embodiment will be compared. Therefore, calculate the capacity for each case,
Next, the two are compared.

Preconditions for comparison are shown in FIGS.
I give it to 8. FIG. 17 shows common prerequisites. FIG.
8 is a parameter.

1. The destination bitmap table amount in the three-stage connection of Conventional Example 1 is calculated. Here, it is assumed that t ² ≧ M is a condition for enabling the three-stage connection. (1) Destination Bitmap Table Capacity in First Stage (Destination Bitmap Table Capacity in First Stage) = ct (row) x t (column) x (M / t) = ctM (bits) (2) Second Stage Destination bitmap table capacity (second stage destination bitmap table capacity) = cM (row) × t (column) × (M / t) = cM ² (bits) (3) third stage destination bitmap table Capacity (3rd-stage destination bitmap table capacity) = cM (row) x t (column) x (M / t) = cM ² (bits) (4) Total of destination bit map table capacity of switch network) = c (tM + 2M ² ) (bits)

2. Amount of destination bitmap table in centralized connection In the case of centralized connection, the number of input ports of the entire switch M
And the number m of input lines, the number n of output lines, and the number k of stages of the unit switch have the following relationship. M ≦ m × (m / n) ^(k−1) As described above, the destination bitmap table capacity in the first stage is the total capacity. (Total of destination bitmap table capacities of all switch networks) = cm (row) x n (column) x (M / m) x (M / n) = cM ² (bits)

3. Comparison In order to simplify the calculation, consider a case where the total number M of input ports is divisible by the numbers t and m of incoming lines of the unit switch. In addition, a case where a pyramid can be assembled just when a concentric connection is made, that is, a case where the number of stages is k and M = m × (m / n) ^(k−1) is established will be examined. FIG. 19 is a diagram comparing the calculated values of the destination bitmap tables. Here, when M = m × (m / n) ^(k−1) , the ratio R between the two in the entire destination bitmap table is R = (concentrated linear connection / conventional three-stage connection) = (cm ² (M / n) ^(2k-2) ) / (c (tm (m / n)
^(k-1) + 2m ² (m / n) ^(2k-2 )) = 1 / ((t /
m) (n / m) ^(k-1) +2). Here, the relationship between t, m, and n becomes a problem, but in the case of a collective switch, m> n. Also, in the case of a three-stage connection, it becomes a square switch, but in general, when making an ATM switch, it is possible to limit the number of output lines due to the I / O pin neck depending on the number of input lines + the number of output lines and the difficulty of forming a queue. . Therefore, this time, m ≧ t ≧ n, and quantitative evaluation is performed. Now, assuming that k ≧ 2, m> n, and m ≧ t ≧ n, the range of R is 0 <n / m <1, and when k = 2, FIG.
FIG. 21 shows when k = 3. However, t, n, m,
It becomes 1/2>R> 1/3 regardless of the value of c. That is, the capacity of the destination bitmap table in the concentric connection is reduced by 1/3 to 1/2 as compared with the conventional three-stage connection.

As described above, in this embodiment, the capacity of the destination bitmap table of the broadcast function in the concentric multistage structure is examined in comparison with the conventional three-stage connection. Consider the case where the same large-scale switch is configured and the same number of broadcast calls is realized per input port. Regardless of the switch scale or the size of the unit switch, the aggregated multi-stage configuration brings about a reduction effect that the total destination bitmap table amount becomes 1/3 to 1/2 as compared with the conventional three-stage connection.

Example 7. In the above embodiment, the case where the number of incoming lines of the first unit switch and the second unit switch is the same has been described. However, even when the numbers of incoming lines of the first unit switch and the second unit switch are different, it is possible to configure a large-scale switch by the concentric connection described in the above embodiment. For example, if the 32 × 8 first unit switch is 3
When used in the first stage, 24 × 8 second unit switches are used in the second stage. When seven 32 × 8 first unit switches are used in the first stage, 56 × 8 in the second stage.
The second unit switch of is used. In both cases, the number of outgoing lines of the first unit switch is equal to the number of outgoing lines of the second unit switch, so that the destination of the cell in the second unit switch is determined by the remainder obtained by dividing the incoming line number by the number of outgoing lines. Alternatively, it may be obtained by another method based on the incoming line number.

Further, in the case of a concentric connection of two or more stages, a second unit switch having a different number of incoming lines may be used in the second and subsequent stages.

Example 8. This embodiment describes one embodiment of a system that accommodates a plurality of low speed interfaces in the latter stage of the output port.

FIG. 22 is a configuration diagram of a 16 × 32 switch by a two-stage connection compatible with a low speed interface. In the present embodiment, an example in which a common low speed interface identification timing is used in order to operate at a common timing is shown. AT
The operating speed of the M switch is 622 Mb / s and the low speed interface is 156 Mb / s. The input ports other than the low speed interface have a speed of 622 Mb / s.
Even if the low-speed interface is connected to the input side, it can be handled as an input port with a speed of 622 Mb / s by the multiplexing circuit, so it is not necessary to consider whether or not the low-speed interface exists on the input side. The number of input ports is 16 from # 0 to # 15. Number of output ports # 0
There are 32 lines up to # 31. Behind the output port # 0, the low speed interface # 0-0 is transmitted via the cell separation circuit 100.
4 to # 0-3 are connected. Multistage connection part is P-1
There are 16 to P-16. In each of the multi-stage connection parts P, two 8 × 2 first unit switches and one 4 × 2 second unit switch are used to perform a two-stage concentric connection. The destination bitmap table is included in the first unit switch SL1. The timing generation means 101 supplies a common low speed interface identification timing to the first unit switch SL1, the second unit switch SL2 and the cell separation circuit 100. Output port # 0 of the first unit switch SL1 and the second unit switch SL2
Outgoing line 0 corresponding to 4 has four address queues corresponding to each of the four low-speed interfaces. FIG. 22 shows the case where the low speed interface is connected to the output port # 0, but the same applies regardless of which output port other than the output port # 0 the low speed interface is connected to.

FIG. 23 is a block diagram of the first unit switch SL1 (for low speed interface). The difference between the first unit switch SL1 compatible with the low speed interface and the first unit switch S1 described in FIG. 2 is the following two points. Address queues A1-00 to A1-03 corresponding to the low-speed interfaces # 0-0 to # 0-3, respectively.
Is provided. In addition, the read buffer selection circuit 1
A selector 160 is provided between 51 and the address queues A1-00 to A1-03. The read buffer selection circuit 151 determines a cell to read from the buffer memory 11 by referring to the address queue A1 and sends the corresponding address as a read address to the storage control circuit 12 associated with the buffer memory 11. Then, the switching of the cell read circuit 14 is controlled and the buffer memory 11 is connected to the output line which is about to be output. The above is
Same as the read buffer selection circuit 19 described above,
The read buffer selection circuit 151 uses the address queues A1-00 to A1- that support the low-speed interface.
03 is not directly referred to, but an address is obtained via the selector 160. The selector 160 has four address queues A1 corresponding to the low speed interface.
One address queue is selected from -00 to A1-03, and the read address is sent to the read buffer selection circuit 151.

FIG. 24 shows a timing chart of each outgoing line. (A) is the low-speed interface identification timing. 22B shows the output timing of the cell at the output line 0 of the first unit switch SL1-1 in FIG. In the output line 0, when the low speed interface identification timing is "High", cells addressed to the low speed interface # 0-0 are output. In this way, the selector 160 always reads an address from the address queue A1-00 corresponding to the low speed interface # 0-0 when the low speed interface identification timing is "High".

FIG. 25 is a diagram showing an operation example of the first unit switch (for low speed interface) SL1-1. In the first unit switch SL1-1, the incoming lines 0 to 7 are connected to the input ports # 0 to 7. The outgoing lines 0 and 1 are connected to the incoming lines 0 and 1 of the second unit switch SL2-1. The outgoing line 0 is connected to the low-speed interface via the second unit switch SL2-1. The selector 160 is supplied with the low speed interface identification timing. The destination bitmap table T-1 is a destination corresponding to the header information.
It has a low speed interface # 0-0 to # 0-3 and an outgoing line 1. In this way, by having the information corresponding to the low-speed interfaces # 0-0 to # 0-3 in the destination bitmap table T-1, the address queues A1-00 to A1-0
It is possible to determine where in 3 the address should be stored.

Next, the case where the broadcast cell a is input to the input port # 1 and the broadcast cell b is input to the input port # 5 will be described as an example. However, the description of the same operation as the conventional example is omitted. The write buffer selection circuit 111 refers to the destination bitmap table T-1 based on the header information and determines the destination. The destination of broadcast cell a is the low-speed interface #
It is determined that the line is 0-0, # 0-1, and the outgoing line 1. The address exchange circuit 120 transfers the addresses of the buffer memory 11 in which the cell a is stored to the address queues A1-00 and A1-
01 and A1-1. Next, for the broadcast cell b arriving at the input port # 5, the destination bitmap T-1 is similarly set.
From the broadcast destination, low-speed interfaces # 0-0, # 0-2, # 0-3, and outgoing line 1 are obtained, and the address is set to the address queue A.
Write 1-00, A1-02, A1-03, A1-1.

The operation when outputting to the output line will be described. (1) The read buffer selection circuit 151 includes the selector 1
Transfer control to 60. At this time, the low speed interface identification timing is set to "High". Since the low-speed interface identification timing is "High", the selector 160 reads the address of the buffer memory 11 in which the cell a is stored from the address queue A1-00 and passes it to the read buffer selection circuit 151. Selector 160
After reading the address from the address queue A1-00, the counter is incremented by 1 to set the position of the address queue to be read next. The read buffer selection circuit 151 sends the received address to the storage control circuit 12, controls the switching of the cell read circuit 14, connects the corresponding buffer memory 11 to the output line 0, and outputs the cell a. (2) The read buffer selection circuit 151 sends the address of the cell a from the address queue A1-1 to the read storage control circuit 12. Further, the switching of the cell read circuit 14 is controlled to connect the corresponding buffer memory to the output line 1. (3) The read buffer selection circuit 151 includes the selector 1
Transfer control to 60. The selector 160 knows that the address queue to be read next from the value of the counter is the address queue A1-01, and reads the address of the cell a. In the same manner as above, low speed interface # 0-
The cell a addressed to 1 is output to the output line 0. (4) The read buffer selection circuit 151 knows the address of the cell b from the address queue A1-1, and similarly outputs the cell b to the output line 1. (5) The same operation is repeated, and then the cell b addressed to the low speed interface # 0-2 is output to the output line 0. (6) Since no address is stored in the address queue A1-1, the idle cell is output to the output line 1.

In this way, cells addressed to the low speed interfaces # 0-0 to # 0-3 are output to the output line 0. Four address queues A1-00 to A1 by the selector 160
Since one of -03 is selected, cells destined for the same low-speed interface are ¼ of the number of cells output to the output line 1.
Becomes Therefore, cell discard due to buffer overflow in the cell separation circuit can be eliminated.

FIG. 26 is a block diagram of the second unit switch SL2 (compatible with the low speed interface). There are the following three differences between the second unit switch SL2 compatible with the low speed interface and the second unit switch S2 described in the above embodiment. Address queue A2-00-A2-0
3 are provided corresponding to the low speed interfaces # 0-0 to # 0-3. The selector 160 is provided between the address queues A2-00 to A2-03 and the read buffer selection circuit 151. Also, the distribution circuit 17
0 is the address exchange circuit 120 and the address queue A2
It is provided between −00 and A2-03.

In the distribution circuit 170 and the selector 160,
The same low speed interface identification timing as that supplied to the selector 160 of the first unit switch SL1 is supplied. The distribution circuit 170 refers to the low-speed interface identification timing and refers to the address queue A2-00.
Allocate cells to A-03. The selector 160 sends out cells in the same manner as the first unit switch SL1 at the low speed interface identification timing. FIG. 24C shows the transmission timing of cells on the output line 0 of the second unit switch SL2-1. In (b) and (c), when the low-speed interface identification timing is "High",
The cells addressed to the low speed interface # 0-0 are output. That is, the output line 0 (b) of the first stage and the output line 0 of the second stage
(C) operates at the same timing.

An operation example of the second unit switch (corresponding to the low speed interface) SL2-1 will be described with reference to FIG. The header processing circuit 132 examines the header information and determines whether the arrived cell is an idle cell. If it is not an idle cell, the write buffer selection circuit 112 is notified of the incoming line number. The write buffer selection circuit 112 determines the cell output line number based on the input line number.
As in the above embodiment, the number of the outgoing line is obtained from the remainder obtained by dividing the incoming line number of the cell arrived by the number of outgoing lines of the second unit switch. However, it may be obtained by other methods. The second unit switch SL2-1 has four incoming lines. Therefore, incoming lines 0 and 2 are output to outgoing line 0, and cells arriving at incoming lines 1 and 3 are output to outgoing line 1. In entry line 0, cells a, a, b, b,
b arrives. The cells a and b arrive at the incoming line 1. Entry line 2
The cells e, f, g, g, g arrive at. The cells f, g, h, i, and j arrive at the incoming line 3. The addresses of the cells a and e arriving on the incoming line 0 and the incoming line 2 are passed to the distribution circuit 170 via the address exchange circuit 120. At this time, the low speed interface identification timing is set to "High". Since the low-speed interface identification timing is "High", the allocating circuit 170 determines that the address queue A2-
Write the addresses of cells a and e in 00. Then, the counter is incremented by 1, and the position of the address queue to be written next is set.

In addition, cell a arriving at incoming line 1 and incoming line 3,
The address of the cell f is written in the address queue A2-1 by the address exchange circuit 120. Next, the cells a and f arriving at the incoming line 0 and the incoming line 2 have the address exchange circuit 12
The address is passed to the distribution circuit 170 via 0.
The distribution circuit 170 writes the addresses of the cells a and f into the address queue A2-01 by checking the counter. In this way, addresses are written in the address queue A2. Since the number of incoming lines is 4, the distribution circuit 170 writes two cell addresses at a time in one address queue A2. If the number of incoming lines is 8, the distribution circuit 170 writes the addresses of four cells at a time to one address queue A2. Since the distribution circuit 170 moves at a speed that is (the number of incoming lines / the number of outgoing lines) times the time slot, the distribution circuit 170 does not need a buffer.

The address exchange circuit 120 can write the address to the address queue A2-1 at the same time as notifying the distribution circuit 170 of the address. Alternatively, they may be performed alternately. Second unit switch SL2
The operation of the selector 160 at -1 is the same as that described for the first unit switch SL1-1.

The address queues A2-00 to A2-03 corresponding to the low speed interface are assigned to the distribution circuit 170.
By referring to the low speed interface identification timing, the address is written. Therefore, the first unit switch SL
The address of the cell written in the address queue A1-00 of No. 1 is written in the address queue A2-00 corresponding to the same low-speed interface # 0-0 also in the second unit switch SL2-1. In this way, by supplying the low-speed interface identification timing to all the unit switches and referencing it by the selector 160 and the distribution circuit 170, the cells stored in the address queue having the first unit switch become the second It is stored in the address queue corresponding to the same low speed interface of the unit switch. Further, the selector 160 in the second unit switch SL2 selects the address queue in order according to the low speed interface identification timing. As a result, the low speed interfaces # 0-0 to # 0-3 corresponding to the cell destinations
You can output cells to. By providing the selectors in the first and second unit switches, the number of times the data output from the plurality of queues stored for each low-speed interface is larger than the output from the queue corresponding to the normal outgoing line. It's getting less. Therefore, cell discard due to buffer overflow in the separation circuit can be eliminated. In addition, also in the cell separation circuit 100, FIG.
As shown in (g), cells are transmitted to the low speed interfaces # 0-0 to # 0-3 at the low speed interface identification timing.

In this way, the first unit switch and the second unit switch are provided with the address queue corresponding to the low speed interface, and the same low speed interface identification timing is given to the selector, the distribution circuit and the cell separation circuit. As a result, even if the first and second unit switches are configured in multiple stages, cells can be sent to a desired low speed interface. The same applies to the case of two or more stages.

As described above, in this embodiment, the cell exchange apparatus capable of connecting the low speed interface to the input port or the output port has been described. This cell exchange device comprises a plurality of first and second unit switches. The first unit switch performs cell copying and destination allocation. First, second
Unit switch operates in synchronization with the low-speed interface identification timing. Since the second unit switch determines the destination outgoing line, that is, the destination low-speed interface with respect to the input cell based on the input line number and the low-speed interface identification timing, the second unit switch does not need the destination bitmap table of the broadcast cell. is there. By connecting such first and second unit switches in two or more stages in a concentrated manner, a cell exchange device capable of large-scale exchange can be obtained. Further, when a plurality of cells input from a plurality of input ports are exchanged by a cell switching device and the cells are output to an output port, cell discard due to buffer overflow in the cell separation circuit can be eliminated. Therefore, when outputting cells from the ATM switch to the cell separation circuit, it is possible to prevent the capacity of each low speed interface from being exceeded. In addition, the buffer memory of the first and second unit switches is used by being shared by the low-speed interfaces by absorbing the time variation of cell arrival in the buffer memories of the first and second unit switches. , The buffer usage efficiency is improved, and the low discard rate can be realized with a small total buffer amount in the entire system.

Example 9. FIG. 28 shows an M using first and second unit switches (m × n) compatible with a low speed interface.
It is a block diagram of a xN switch. It is possible to construct a cell switching device of any size by using a plurality of first and second unit switches corresponding to the low speed interface similar to the above embodiment. The number of low speed interfaces is arbitrary. Further, the number of output ports connected to the low speed interface is not limited to the output port i and may be any number.

Example 10. This embodiment describes one embodiment of a system that accommodates a high speed interface.

FIG. 29 is a block diagram of a high speed interface. The figure shows only the multi-stage connection portion P-1.
One high-speed interface is connected via the cell multiplexing circuit 180 to the subsequent stage of the output ports # 0 to # 4. Also,
For large scale, the first and second unit switches are connected in two stages. First unit switches SH1-1, SH1-
Both 2 and the second unit switch SH2-1 have 16 incoming lines and 8 outgoing lines. The feature of the first and second unit switches is that for a plurality of outgoing lines corresponding to the high speed interface,
One address queue. Considering the case where a high-speed interface is connected to the input port side via a cell separation circuit, it is necessary to save the cell arrival order. Therefore, when cells arrive at the first and second unit switches at the same time, the cells are processed in the order from the incoming line 0 to the incoming line 15.

FIG. 30 is a block diagram of the first unit switch (high-speed interface compatible) SH1. The features of the first unit switch (high-speed interface compatible) SH1 are:
This is a point having one address queue A1-H for a plurality of outgoing lines. The plurality of outgoing lines are outgoing lines corresponding to the output ports connected to the high speed interface via the cell multiplexing circuit 180. A distribution circuit 190 is provided between the address queues A1-H and the read buffer selection circuit 152. The distribution circuit 190 sequentially reads the addresses stored in the address queues A1-H one by one from the beginning of each of the plurality of outgoing lines. The address read by the distribution circuit 190 is the read buffer selection circuit 1
Passed to 52.

FIG. 31 is a block diagram of the second unit switch (high-speed interface compatible) SH2. An address queue A2-H corresponding to a plurality of outgoing lines is provided, and a distribution circuit 190 is provided. The functions of the address queue A2-H and the distribution circuit 190 are the same as in FIG.

The operation of the first unit switch in the first stage will be described with reference to FIG. In the figure, "a" to "h" represent cells and show the flow from the input to the queue to the output. In the first unit switch SH1, one address queue A1-H is provided to the four outgoing lines 0 to 3 corresponding to the high speed interface. In the first unit switch SH1-1, cells are arranged in the order of "a", "b", "c", and "d" from the beginning in the address queue A1-H accommodating the high speed interface. . A high-speed interface may be connected to the four input ports via the cell separation circuit. Therefore, in order to save the order relation of the cells on the output destination high-speed interface, the separation circuit 190 causes the address queues A1-H to store the addresses "a", "b", "c", and "d" four at a time. read out. Read "a", "b", "
The addresses “c” and “d” are passed to the read buffer selection circuit 152, and the read buffer selection circuit 152 outputs the cell “a” stored in the buffer memory 11 to the output line 0.
Then, "b" is output to output line 1, "c" is output to output line 2, and "d" is output to output line 3. 4 are sent out simultaneously on 4 outgoing lines
Regarding the cell, the cell on the outgoing line 0 is set to be the cell to be transmitted first in terms of time in advance, and the outgoing lines 1, 2 and 3 will be described in this order. Cell "e" of the first unit switch SH1-2
The same applies to "chi".

Using FIG. 33, the second unit switch SH2
The operation of will be described. Second unit switch SH2
Has one address queue A2-H for four outgoing lines 0-3 corresponding to the high speed interface. The second unit switch SH2-1 has 16 incoming lines,
Determine the outgoing line from the incoming line number. The write buffer selection circuit 112 uses the remainder obtained by dividing the incoming line number of the arriving cell by the number of outgoing lines as the destination outgoing line number as in the above embodiment. However, other methods may be used. If the remainder obtained by dividing the incoming line number by the number of outgoing lines is the destination outgoing line, outgoing lines 0 to 3 correspond to the address queue A2-H, and therefore incoming lines 0, 1, 2, 3, 8, 9,
The cells arriving at 10 and 11 will be written. The address exchange circuit 120 includes a write buffer selection circuit 112.
From the output line 0 to 3 and writes it in the address queue A2-H. When the destination is 4, the address queue A2-4 is written. If the destination is 7, write to the address queue A2-7.

Here, it is necessary to prevent the order of cells from being reversed between the incoming lines 0, 1, 2, and 3 and between the incoming lines 8, 9, 10, and 11. Therefore, the address exchange circuit 120
Writes the addresses in the address queue A2-H in ascending order of incoming line numbers, that is, in ascending order of destination. The order of cells written to the address queue is cell "a", "
"B", "c", "d", "ho", "f", "to", "
The order is "chi." However, for example, "i", "ho", "
Even if it becomes "ro", "he", "ha", "to", "d", or "chi", it will be between lines 0, 1, 2, 3 and line 8, 9, 10,
This is possible because cell order inversion between 11 does not occur. Address queue A2-H to cell "a", "
The addresses “b”, “c”, and “d” are read at once by the distribution circuit 190, and the read buffer selection circuit 152
Passed to. The read buffer selection circuit 152 reads cells from the buffer memory 11 based on the passed address.
"A" to output line 0, cell "b" to output line 1 ... cell "
D) is output to output line 3. Cell "ho", "he", "
The same processing is performed for "TO" and "HI". Then, the cell multiplexing circuit 180 in the subsequent stage transmits the cells to the high speed interface in the order of "I", "RO" ... "HI". The same applies when the first and second unit switches are connected in two or more stages.

As described above, in this embodiment, the cell exchange apparatus capable of connecting the high speed interface to the input port or the output port has been described. This cell switching device comprises a plurality of first and second unit switches. The first unit switch performs cell copying and destination allocation. The second unit switch determines the destination outgoing line of the arrived cell based on the incoming line number. Predetermined order relations are stored in multiple incoming lines that support high-speed interfaces,
Write incoming cells to one queue. By connecting the first and second unit switches in two or more stages in a concentrated manner, a cell exchange device capable of large-scale exchange can be obtained. Also, when a plurality of cells input from a plurality of incoming lines are exchanged by the first and second unit switches and the cells are output to an outgoing line, a fixed priority is assigned to the plurality of incoming lines and outgoing lines. Process and save the order of cells that arrived at the same time. Also, by managing these multiple outgoing lines in a single queue, it became possible to accommodate a high-speed interface.

Example 11. FIG. 34 is a configuration diagram of a 128 × 32 switch in the case where the input line 32 and the output line 8 are used for the first unit switch S1 and the input line 16 and the output line 4 are used for the second unit switch S2. In the above-described embodiment, 32 × 8 is used for the second unit switch S2 in order to realize 128 × 8 for the multistage connection portion P. However, as shown in the figure, the second
The same function can be realized by using two 16 × 4 unit switches S2. In this case, the outgoing lines 0 to 3 of all the first unit switches S1-1 to S1-4 are connected to the second unit switch S2-1. All first unit switches S1
-1 to S1-4 output lines 4 to 7, the second unit switch S
Connect to 2-2. Thus, the first unit switch S
The number of incoming lines and the number of outgoing lines of the first and second unit switches S2 may be different. The same applies to the first and second unit switches for low speed interfaces and high speed interfaces.

Example 12. A case where the destination bitmap table is shared will be described with reference to FIG. The first unit switches S1-1 and S1-2 share the destination bitmap table T-1 for use. The first unit switches S1-3 and S1-4 are the destination bitmap table T-2.
To share. In this way, the destination bitmap table can be shared and used among the plurality of first unit switches. Alternatively, one destination bitmap table may be shared by all the first unit switches. The same applies to the first and second unit switches for low speed interfaces and high speed interfaces.

Example 13 In the above embodiments, the ATM switch into which cells are input has been described. However, if a broadcast cell is used as broadcast data, a similar switch can be provided for a data exchange device used for general data communication.

[0123]

According to the first aspect of the present invention, the number of input ports connectable to the data exchange device can be increased by arranging a plurality of unit switches having a small number of incoming and outgoing lines in multiple stages.

According to the second invention, the number of output ports connectable to the data exchange device can be increased.

According to the third invention, the first unit switch can know the output line to which the broadcast data should be output from the table. Also, the output destination of each broadcast data can be easily changed by exchanging the table.

According to the fourth invention, the second unit switch does not need a table for knowing the destination of the input data. Therefore, it is possible to reduce the amount of tables used as the data exchange device.

According to the fifth aspect of the present invention, the cells can be exchanged by the virtual path identifiers of the cells and the virtual channel identifiers.

According to the sixth aspect, the size of the table for determining the destination can be reduced, and the destination can be searched efficiently. Further, since the size of the table is small, the table can be stored in the RAM and can be built in the first unit switch. Moreover, since the tables are separately provided, it is easy to change the tables.

According to the seventh invention, since a plurality of unit switches can share one table, they can be collectively managed.

According to the eighth aspect, the outgoing line can be determined by the broadcast identifier. Further, since the broadcast identifier is used, the size of the table can be reduced.

According to the ninth aspect of the invention, since the broadcast identifier only needs to be defined for some input ports, the broadcast identifier can be easily assigned.

According to the tenth invention, the invention can be applied to the case where the low speed interface is accommodated.

According to the eleventh invention, data addressed to each low-speed interface can be reliably output to the low-speed interface of the destination, and cell discard due to buffer overflow in the separation circuit can be eliminated. In addition, the time variation of cell arrival can be absorbed by the first and second unit switches.

According to the twelfth aspect, the invention can be applied to the case where a high speed interface is accommodated.

According to the thirteenth invention, the order relation of data can be stored and output to the high speed interface on the output port side.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a 32 × 32 switch with two-stage connection.

FIG. 2 is a block diagram of a first unit switch.

FIG. 3 is a diagram showing an operation example in a first unit switch S1-1.

FIG. 4 is a diagram showing an operation example in a first unit switch S1-3.

FIG. 5 is a diagram showing an operation example of a first unit switch S1-63.

FIG. 6 is a block diagram of a second unit switch.

FIG. 7 is a diagram showing an operation example of a second unit switch.

FIG. 8 is a configuration diagram of an M × N switch with two-stage connection.

FIG. 9 is a first unit switch S1- of the M × N switch.
2 is a diagram showing an operation example in FIG.

FIG. 10 is a second unit switch S2 of the M × N switch.
2 is a diagram showing an operation example in -1. FIG.

FIG. 11 is a configuration diagram of a K × L switch with a concentric connection when three stages of m × n unit switches are used.

FIG. 12 is a configuration diagram of an M × N switch by a concentric connection when the broadcast number is defined for each incoming line group.

FIG. 13 is a diagram showing an example in which a broadcast number is added to an extra header.

FIG. 14 is a diagram showing an example in which a broadcast number is given to a switch by another line.

FIG. 15 is a diagram showing an operation example in the first unit switch when the broadcast number is used.

FIG. 16 is a diagram showing an example of a destination bitmap table in the case of directly referring to VPI and VCI values for each input port.

FIG. 17 is a diagram showing common items for comparison.

FIG. 18 is a diagram showing each parameter.

FIG. 19 is a diagram comparing the amounts of destination bitmap tables.

FIG. 20: Capacity ratio R of destination bitmap table
Showing the range (k = 2).

FIG. 21: Capacity ratio R of destination bitmap table
Showing the range (K = 3) of FIG.

FIG. 22 is a configuration diagram of a concentrated line connection for a low speed interface.

FIG. 23 is a block diagram of a first unit switch (compatible with a low speed interface).

FIG. 24 is a diagram showing a timing chart of each outgoing line.

FIG. 25 is a diagram showing an operation example of a first unit switch SL1-1.

FIG. 26 is a block diagram of a second unit switch (compatible with a low speed interface).

FIG. 27 is a diagram showing an operation example of a second unit switch SL2-1.

FIG. 28 is a configuration diagram of an M × N switch compatible with a low speed interface.

FIG. 29 is a block diagram of a concentrated line connection for a high speed interface.

FIG. 30 is a block diagram of a first unit switch (compatible with a high speed interface).

FIG. 31 is a block diagram of a second unit switch (compatible with a high speed interface).

FIG. 32 is a diagram showing an operation example of a first unit switch (compatible with a high-speed interface).

FIG. 33 is a diagram showing an operation example of a second unit switch (compatible with a high speed interface).

FIG. 34 is a configuration diagram of a centralized connection including a first unit switch and a second unit switch having different numbers of incoming lines and outgoing lines.

FIG. 35 is a configuration diagram of a centralized connection when sharing a destination bitmap table.

FIG. 36 is a diagram showing a speech channel configuration model in Conventional Example 1.

FIG. 37 is a route information table capacity comparison diagram in Conventional Example 1.

FIG. 38 is a configuration diagram of a header processing unit in Conventional Example 1.

FIG. 39 is a diagram showing an increase in scale due to a pyramid configuration in Conventional Example 2.

FIG. 40 is a block diagram showing an entire cell exchange apparatus in Conventional Example 3.

FIG. 41 is a block diagram of an ATM switch in Conventional Example 3.

FIG. 42 is a diagram showing an internal circuit example of a cell multiplexing circuit in Conventional Example 3;

FIG. 43 is a timing chart of each part in Conventional Example 3.

FIG. 44 is a diagram showing an example of an internal circuit of a cell separation circuit in Conventional Example 3.

FIG. 45 is a timing chart of each part in Conventional Example 3.

FIG. 46 is a diagram showing an example of an address queue in the ATM switch in Conventional Example 3.

FIG. 47 is a timing chart of outgoing lines in Conventional Example 3.

FIG. 48 is a diagram showing a line accommodation system in Conventional Example 4.

[Explanation of symbols]

1 input line, 2 output line, 3 ATM switch, 4 cell multiplexing circuit, 5 cell separation circuit, 6 input port, 7 output port, 8 cell switching device, 10 header processing circuit, 1
DESCRIPTION OF SYMBOLS 1 buffer memory, 12 storage control circuit, 13 cell write circuit, 14 cell read circuit, 15 buffer control circuit, 16 write buffer selection circuit, 17
Address exchange circuit, 18 address queue, 19 read buffer selection circuit, 21 and 23 cell speed adjustment buffer, 22 address filter, 100 cell separation circuit, 101 timing generation means, 105 broadcast processing means, 111 and 112 write buffer selection circuit , 12
0 address exchange circuit, 131, 132 header processing circuit, 151, 152 read buffer selection circuit, 16
0 selector, 170 distribution circuit, 180 cell multiplexing circuit, 190 distribution circuit, S1-1, S1-2, S1
-3, S1-4, S1-63, S1-M / m, S1 first unit switch, T-1, T-2, T-3, T-4,
T-M / m, T destination bitmap table, S2-
1, S2 Second unit switch, P-1, P-2, P-
16, P-N / n, P-L / n multi-stage connection part, A1-
0, A1-1, A1-2, A2-0, A2-1, A2-
2, A2- (n-1), A1-00, A1-01, A1
-02, A1-03, A2-00, A2-01, A2-
02, A2-03, A1-H, A2-H address queue, D-1, D-2, DM / m broadcast identifier assigning means, SL1-1, SL1-2, SL1-M / m 1
Unit switch (compatible with low-speed interface), SL2-
1 2nd unit switch (low speed interface compatible),
SH1-1, SH1-2 First unit switch (high-speed interface compatible), SH2-1 Second unit switch (high-speed interface compatible).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhito Sasaki 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corp. Communication Systems Research Institute (72) Hirotoshi Yamada 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corporation (72) Inventor Kazuno Oshima 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Co., Ltd.

Claims (13)

[Claims] 1. A plurality of units, each having a plurality of input ports and a plurality of output ports, for exchanging data between a plurality of input lines and a plurality of output lines between the plurality of input ports and the plurality of output ports. Arrange the switches in at least two stages to exchange data between multiple input ports and multiple output ports,
In a data exchange device that, when broadcast data is input, copies the broadcast data and outputs it to a plurality of predetermined output ports, the first unit switch is the first unit switch, and the second unit switch is the second unit switch. The unit switches after the second stage are the second unit switches,
If necessary, multiple first unit switches respond to the broadcast data input from a certain input port by copying and exchanging the broadcast data, and handling the copied multiple broadcast data to the output port of the broadcast destination. The second unit switch has a plurality of unit switches in the preceding stage, and the copied broadcast data outputted from the outgoing lines of the plurality of unit switches in the preceding stage are inputted and inputted. A data exchange device having a multistage connecting section, characterized in that copied broadcast data is exchanged based on a predetermined rule and finally outputted to an output port of a broadcast destination. 2. A plurality of the multi-stage connection units are provided, data input to an input port is branched and input to the plurality of the multi-stage connection units, and different output ports are assigned to the multi-stage connection units. The data exchange device according to claim 1. 3. The first unit switch determines a table defining a plurality of outgoing lines to which each broadcast data is to be output and an outgoing line to which the broadcast data is to be output by referring to the table. 3. The data exchange device according to claim 1, further comprising a broadcast processing means for copying and exchanging the broadcast data. 4. The second unit switch determines an outgoing line for outputting the copied broadcast data based on an incoming line number of an incoming line for inputting the copied broadcast data. The data exchange device according to item 1, 2, or 3. 5. The data exchange device is a cell exchange device for exchanging cells having a virtual path identifier and a virtual channel identifier in an asynchronous transfer mode communication system (ATM communication system), and the table is virtual. A plurality of outgoing lines from which a broadcast cell should be output are defined for both or one of the path identifier and the virtual channel identifier, and the first unit switch is a virtual path identifier for the broadcast cell. 5. The data exchange device according to claim 3, wherein the outgoing line to be broadcast is determined from the table based on both or one of the virtual channel identifiers. 6. The data exchange device according to claim 3, wherein the table is provided independently for each first unit switch. 7. The data exchange apparatus according to claim 3, wherein the table is provided commonly to the plurality of first unit switches. 8. The data exchange device is a cell exchange device for exchanging cells, and the cell exchange device assigns a broadcast identifier for identifying a broadcast cell to each broadcast cell before the input port. Means for defining the outgoing line from which the broadcast cell should be output for the broadcast identifier,
5. The data exchange device according to claim 3, wherein the first unit switch determines an outgoing line to be broadcast from the table based on a broadcast identifier. 9. The data exchange apparatus according to claim 8, wherein said broadcast identifier assigning means is provided for each of the incoming line groups consisting of a plurality of said input ports. 10. The data exchange device comprises an output port for accommodating a plurality of low speed interfaces, wherein the first unit switch performs copy and exchange of broadcast data corresponding to the plurality of low speed interfaces, The data exchange device according to claim 1, wherein the second unit switch outputs the broadcast data corresponding to the plurality of low speed interfaces to an output port accommodating the plurality of low speed interfaces. 11. The data exchange apparatus is further connected to at least one of the output ports after the output port, connects a plurality of low speed interfaces, and separates data output from the output ports to separate the low speed interfaces. And a timing generating means for generating an identification timing for operating the separation circuit, the first unit switch, and the second unit switch at a common timing, the first unit switch Defines a plurality of queues for storing output data for each low-speed interface and a plurality of output lines to which each broadcast data should be output, for the output line corresponding to the output port to which the separation circuit is connected. In addition, if the outgoing line is the outgoing line that connects the low-speed interface, the low A table defining interfaces, a broadcast processing means for determining a low-speed interface to which broadcast data should be output by referring to the table, and storing the broadcast data in a queue corresponding to the low-speed interface, And a selector for controlling the order of outputting the data from the queue according to the identification timing, wherein the second unit switch outputs the data to be output to the output line corresponding to the output port to which the separation circuit is connected for each low-speed interface. A plurality of queues stored in the queue, a distribution circuit that distributes the data input from the incoming line to a queue corresponding to the low-speed interface that should be output at the identification timing, and the order in which the data is output from the queues is controlled by the identification timing. 11. The selector according to claim 10, further comprising: Placing data exchange apparatus. 12. The data exchange device comprises a plurality of output ports accommodated in at least one high-speed interface, and the first unit switch performs copy and exchange of broadcast data corresponding to the high-speed interface. 2. The data exchange device according to claim 1, wherein the second unit switch outputs the broadcast data corresponding to the high speed interface to a plurality of output ports accommodated in the high speed interface. 13. The data exchange device is further connected to a subsequent stage of the plurality of output ports, connects the high speed interface, and multiplexes data output from the plurality of output ports and outputs the multiplexed data to the high speed interface. And the first unit switch and the second unit switch are one queue for storing data to a plurality of output lines corresponding to a plurality of output ports connected to the multiple circuit. 13. The data exchange apparatus according to claim 12, further comprising: and outputting data to each outgoing line in the order stored in the queue.