JP3079068B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode: Used for communication.
The present invention is suitable for use in an ATM switching device. In particular,
The present invention relates to a technology for configuring a large-scale ATM switch by connecting unit switches in multiple stages.

[0002]

2. Description of the Related Art In ATM, fixed-length cells are switched at high speed by hardware using a simplified program without using software. Therefore, the ATM switch mounted on the ATM exchange is required to have high-speed controllability and high-speed switching performance. In particular, the number of accommodation lines has increased,
When the required switch size becomes large, it cannot be accommodated by adding unit switches, and a multistage switch configuration for connecting the unit switches in multiple stages is required.

This conventional example will be described with reference to FIG. FIG. 9 is a diagram showing an ATM switch in which unit switches are cascaded in three stages. Conventionally, as shown in FIG. 9, a cross switch architecture in which unit switches are connected in cascade in three stages is known as an effective method for increasing the switch size in a multistage switch configuration.

In this cross switch architecture,
Basically, input traffic is switched on a connection basis, so that cells forming the same connection always pass through the same route in the switch. For this reason, if the connection route in the switch is not managed, a link block due to the connection level occurs in the second-stage switch, the traffic flowing into the link falls into a high load state, and the cell loss rate is remarkably deteriorated.

Conventionally, as a method of avoiding such a link block state, (1) a condition in which a connection having an arbitrary speed is accommodated in a switch in a worst pattern is considered (Sakurai et al., “Multi-stage”). Investigation of non-blocking conditions for connected ATM communication path "Shin-Shungaku Spring Spring University B-31"
8) Even if the accommodating connection is biased in the worst state in the switch, the speed of the inside of the cross switch is increased so that the link capacity is insufficient and a link block does not occur, or the second stage switch constituting the cross switch is used. A method of increasing non-blocking by increasing the effective link capacity by increasing the number of routes to be routed. (2) Managing all connections accommodated in the switch and, when a link block occurs, the number of connections accommodated There is a method of avoiding a link block by changing the accommodating of connections in consideration of a used band, and (3) a method of distributing an in-switch traffic by distributing an input connection to a second stage at a cell level and preventing a link block. .

[0006]

However, such a conventional method has a problem in its feasibility in an ATM having a plurality of service classes and multiplexing connections having an arbitrary data transmission rate. It cannot be a complete solution to non-blocking.

For example, in order to accommodate a connection having an arbitrary speed by the method according to (1), it is necessary to increase the internal link capacity of the switch to three times, which is a great difficulty for forming a link between switches. Accordingly, there is a disadvantage that a high-speed switch has an uneconomical architecture.

In the method according to (2), in a high-speed switch in which the average hold time of the connection is shortened and the number of accommodated connections is enormous, the bandwidth used for each connection is managed and the connection level overlaps. In order to prevent the link block by changing the combination of the accommodating connections in consideration of the above, a huge amount of calculation is required, and it cannot be a realistic approach.

In the method of (3), in order to prevent the cell order from being reversed, a time stamp is added to each cell on the switch input side, and the operation of rearranging the cells on the switch output side based on the time stamp information is performed. is necessary.

In the case of such a configuration, a buffer is usually provided in the switch in order to obtain good traffic characteristics.
Since 0 or more cells are provided, the order may be reversed for the maximum buffer capacity.

[0011] Assuming that the sorting object is N, usually s = K
Since a log2N step is required, in a high-speed switch having a plurality of high-speed input / output ports, it is difficult to arrange such a large-scale sorting circuit and a large-scale buffer for holding cells for each output port. This is not a realistic approach.

The present invention has been made in such a background, and an AT capable of accommodating a connection having an arbitrary data transmission rate regardless of a service class.
It is intended to provide an M switch. SUMMARY OF THE INVENTION It is an object of the present invention to provide an ATM switch that switches accommodation connections in a non-blocking manner and improves network efficiency.

[0013]

The most important feature of the present invention is to perform dynamic cell-level routing capable of realizing cell order guarantee without time stamps and to make the ATM switch non-blocking. It differs from the prior art in that static connection-based routing is not performed.

For this reason, the unit switch in the first stage is designed so that the output lines do not overlap for each input line within one cell time.
By sorting input cells on a cell-by-cell basis,
It is possible to equalize the load of the traffic input to the second-stage unit switch and the target output path without depending on the input load and without depending on the bias of the input traffic.

In the unit switch of the second stage, 3
For each buffer connected to the same unit switch at the stage, the arriving cell information is detected between the buffers, the detected information is exchanged between the buffers, and an empty cell is inserted based on the detected information. Thus, the queue length in each buffer is controlled in conjunction with the queue length of the buffer in which the maximum simultaneous arrival of the cells of the unit switch of the second stage has occurred, and each cell which aims at the same unit switch of the third stage 2
The delay time in the unit switch at the stage is made the same.

For this reason, cells that have passed through different first-stage unit switches and second-stage unit switches aiming at the same third-stage unit switch are input to the third-stage unit switch with the same intra-switch delay time. Therefore, the cell order can be reversed. For this reason, a time stamp is provided for each switch cell, the order of the cells is sorted on the switch output side, and the conventional technique that requires rearrangement of the cells is different from the conventional technique in which the time stamp is unnecessary and a sorting circuit on the output side. However, the point that is unnecessary is greatly different.

Further, in the ATM switch of the present invention, an empty cell is inserted in the unit switch at the second stage, so that the buffer input load apparently increases. Therefore, it is desirable to improve the traffic characteristics by increasing the buffer output by a factor of K. It is desirable that the empty cells are separated from the actual input cells and discarded on the input side of the third-stage unit switch.

That is, the present invention relates to an ATM switch comprising a unit switch for distributing cells arriving at N input lines to one of N output lines according to the destination. The switches are connected in cascade in three stages. In each of the first and second stages and the second and third stages, each of the N output lines of the unit switch is the same as the input line of the next N unit switches. It is an ATM switch connected to the crab.

Here, a feature of the present invention is that the unit switch in the first stage changes the destination allocation of N output lines every cell time and returns to the initial allocation in N cell times. Where means for circulating water are provided.

Each of the second-stage unit switches is provided with a buffer for each output line, and each of the second-stage N switches connected to the same third-stage unit switch has its N buffer. It is desirable to have means for inserting empty cells so that the queue lengths of the buffers become equal to each other.

The processing speed on the output side of the unit switch in the second stage and the input side of the unit switch in the third stage is 1
It is desirable to set K times the processing speed of the unit switch at the stage.

The unit switch at the third stage comprises N buffers provided for each input line, and means for removing empty cells inserted by the inserting means from a cell row to be written into the buffers. It is desirable to provide.

[0023]

Embodiments of the present invention will be described with reference to FIG. FIG. 1 is an overall configuration diagram of an ATM switch according to an embodiment of the present invention.

The present invention relates to an ATM switch comprising unit switches U _{11 to} U _3N for distributing cells arriving at N input lines to one of N output lines according to their destinations. The unit switches U _{11 to} U _3N are 3
It is connected to the cascade-, the first and second stages and the second and third stages, the unit switches U ₁₁ respectively ~U _1N, U ₂₁ ~U
_N output lines of _2N are connected to N unit switches U ₂₁ to U ₂₁ of the next stage.
U _2N, U ₃₁ ~U _3N connected A to one of the input lines
It is a TM switch.

The features of the present invention are as follows.
Stage unit switch U ₁₁ ~U _1N of, there is to be circulated back to the first assignment with changes the destination assignment of N output line for each cell time N cell time.

The second unit switch U _{21 to} U _2N is provided with a buffer for each output line, and the second stage unit switch U _{31 to} U _3N is connected to the same unit switch U _{31 to} U _3N . The cell order control unit 10 inserts empty cells so that the queue lengths of the N buffers are equal to each other for each of the N buffers.

The processing speed of the output side of the second-stage unit switches U _{21 to} U _2N and the processing speed of the input side of the third-stage unit switches U _{31 to} U _3N are the processing speed of the first-stage unit switches U _{11 to} U _1N . K
It is set to double.

The unit switches U _{31 to} U _{3N at the} third stage are composed of N buffers provided for each input line, and empty cells inserted by the cell order control unit 10 from a cell row written in the buffers. And an empty cell removing unit 20 for removing the

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is as described above. Figure 2 is a unit switch U ₁₁ ~U block diagram of a _1N in the first stage. Figure 3 is a diagram for explaining the unit switch U ₁₁ ~U _1N operation of the first stage. FIG. 4 is a block diagram of the unit switches U _{21 to} U _{2N in} the second stage. FIG. 5 shows the unit switch U in the second stage.
It is a diagram for explaining the operation of the ₂₁ ~U _2N. 6 is a diagram showing the relationship between the size and the line speed increasing rate of the unit switch U ₂₁ ~U _2N in the second stage. The horizontal axis indicates the unit switch size, and the vertical axis indicates the line speed increase rate. FIG. 7 is a diagram showing the relationship between the input load and the line speed increase rate. The horizontal axis indicates the input load, and the vertical axis indicates the line speed increase rate. Figure 8 is a block diagram of the unit switch U ₃₁ ~U _3N of the third stage.

The ATM switch of the present invention is based on a cross switch architecture in which N × N unit switches U _{11 to} U _3N are connected in three stages. As shown in FIGS. 2 and 3, the unit switch at the first stage U ₁₁ ~U _1N unit of second stage input traffic at the cell level switch U ₂₁ ~U _2N
And a bufferless switch that performs allotting.

As shown in FIGS. 4 and 5, the unit switches U _{21 to} U _2N in the second stage guarantee the cell order by inserting empty cells in the buffer, and read from the buffer by k times. Output at high speed.

As shown in FIG. 8, the unit switches U _{31 to} U _3N in the third stage are the empty cells inserted in the unit switches U _{21 to} U _2N in the second stage in the empty cell removing unit 20 in the switch input stage. The original communication cell is separated, and the empty cell is discarded. In addition, 2
Undo faster line speed in stage unit switch U ₂₁ ~U _2N.

Next, the unit switches U _{11 to} U in each stage
A specific configuration example of _3N and an operation example thereof will be described. Shows the A slotter ring switch configuration example that is disposed in the unit switch U ₁₁ ~U _1N in the first stage in FIG. The unit switch U ₁₁ ~U _1N
Is composed of a bufferless cross point switch and a tag conversion circuit 15. The tag conversion circuit 15 inserts a tag corresponding to the output route number every time a cell arrives.

FIG. 3 conceptually shows the status of the tag conversion. Times T1 to T4 correspond to one cell time. FIG. 3 shows an example in which the number of input / output lines is four. A predetermined input line is connected to one of the N output lines in a cyclic manner every cell time. The tag conversion circuit 15 outputs 00, 0 in the order of cell arrival.
Tags 1, 10, and 11 are assigned to input cells. Thereafter, the input cells are sent to the subsequent bufferless switch, read out by the address filter included in the cross point X for each tag, and distributed to different output routes. At this time, (01, 10, 11, 00), (1
0, 11, 00, 01), (11, 00, 01, 10)
, The cells input to the corresponding first-stage unit switches U _{11 to} U _1N are uniformly distributed in load and output route destination, and the second-stage unit switches U ₂₁
ＵU _2N .

FIG. 4 shows an example of the configuration of the second-stage unit switches U _{21 to} U _2N . The unit switch U ₂₁ ~U _2N is a base of an output buffer type switch, the unit switches U ₂₁ ~
It is assumed that the speed of the inside of U _2N is increased to N times speed, and a maximum of N cells arrive at the output buffer unit 16.

At this time, as shown in FIG. 5, the second-stage unit switches U _2p , U _2q and U _2r connected to the same third-stage unit switch U _3i (i = 1 to N). (P, q,
A buffer control unit 51 connected to each other by a control line 50 is arranged between buffers at r = 1 to N). The buffer control unit 51 monitors the number of cells arriving at its own unit switch U _2p , U _2q , U _2r simultaneously,
The number of simultaneous cells is notified to the buffer controllers 51 of the unit switches U _2p , U _2q , and U _2r other than itself using the control line 50.

Each buffer control unit 51 compares the notified information with the number of cells arriving at its own buffer.
If the number of arriving cells is small, an empty cell I is generated until it becomes the same as the maximum number of arriving cells other than itself, and inserted into the buffer.

FIG. 5 shows the second stage unit switch U at time T1.
Three cells (illustrated as t1) arrive at the _2p buffer at the same time, and in response thereto, the buffer controller 5 of the unit switch U _2q receives it.
1 shows an example in which three empty cells I are inserted, and the buffer control unit 51 of the unit switch U _2r inserts two empty cells I. By performing such an operation, the delay time in the switch to the unit switch U _2p , U _2q , U _{2r in} the second stage between the cells aiming at the same unit switch U _3i in the same stage becomes the same. Order reversal can be guaranteed.

However, since an extra load is generated due to such an empty cell, the buffer output is increased by K times. 6 and 7 estimate the speed-up coefficient.
As shown in FIG. 6, if the unit switch size is increased, the speed-up factor can be suppressed. As shown in FIG. 7, when the input load is reduced, sufficient traffic characteristics can be obtained without increasing the speed.

Next, FIG. 8 shows a configuration example of the unit switches U _{31 to} U _{3N in} the third stage. Third stage unit switches U _{31 to} U _3N
Is composed of an output buffer type switch 17 and an empty cell removing unit 20. Empty cell removal unit 20 separates the communication cell with the air-cell I which is inserted in the unit switch U ₂₁ ~U _2N in the second stage, the unit switches U ₃₁ in the third stage by discarding the empty cell I ~U lower the input load of _3N improving the traffic characteristics of the unit switch U ₃₁ ~U _3N of the third stage.

The first-stage unit switch U ₁₁ described above.
~ U _1N can also be configured using a common buffer type switch. In the case of the configuration using the common buffer type switch, the input traffic is equally distributed to the respective output ports at the cell level for both the load and the destination by providing an allotting function to the cell reading portion of the conventional common buffer type switch. be able to. Furthermore, it is possible for the second-stage unit switches U ₂₁ of ~U _2N and units of the third stage switch U ₃₁ ~U _3N also constructed using the shared buffer type switch.

[0042]

As described above, according to the present invention,
An ATM switch that can accommodate a connection having an arbitrary data transmission rate regardless of the service class can be realized. Further, it is possible to realize an ATM switch that switches the accommodated connections in a non-blocking manner and improves network efficiency.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an ATM switch according to an embodiment of the present invention.

FIG. 2 is a block diagram of a first-stage unit switch.

FIG. 3 is a diagram for explaining the operation of a first-stage unit switch;

FIG. 4 is a block diagram of a second-stage unit switch.

FIG. 5 is a diagram for explaining the operation of a second-stage unit switch;

FIG. 6 is a diagram illustrating a relationship between the size of a unit switch in a second stage and a line speed increase rate.

FIG. 7 is a diagram illustrating a relationship between an input load and a line speed increase rate.

FIG. 8 is a block diagram of a third-stage unit switch.

FIG. 9 is a diagram showing an ATM switch in which unit switches are cascaded in three stages.

[Explanation of symbols]

10 cell sequence controller 15 tag conversion circuit 16 the output buffer unit 17 output buffer type switch 20 empty cell removal unit 50 control lines 51 buffer controller I empty cell t1, t2 cell _{U 11 ~U 3N, U 3i,} U 2p, U _2q , U _2r unit switch X cross point

Continuation of front page (72) Inventor Takashi Kurimoto Nippon Telegraph and Telephone Corporation 3-9-1-2 Nishishinjuku, Shinjuku-ku, Tokyo (56) References JP-A-6-6370 (JP, A) JP-A-5 -268251 (JP, A) JP-A-8-23334 (JP, A) IEICE technical report SSE89-173 IEICE technical report SSE97-31 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12 / 28 H04L 12/56

Claims (3)

(57) [Claims] 1. A cell arriving at N input lines is addressed to the cell.
One of N output lines according to the previousofOutput line
Unit switch that distributes the
The first, second and second stages are connected in cascade
In the third stage, the N output lines of each unit switch are
Connected to one of the input lines of the N unit switches
In the ATM switch, the first-stage unit switch is:Traffic in ATM switch
Distribute the load of the hickEquipped with means, The second-stage unit switch is provided for each output line.
And the same unit switch as the third-stage unit switch is provided.
For each of the N buffers in the second stage connected to the
So that the queue lengths of the N buffers of
With means for inserting empty cells ATM characterized by the following:
switch. 2. The output side of said second stage unit switch and
And the processing speed on the input side of the third unit switch is
The ATM switch according to claim 1, wherein the processing speed is set to K times the processing speed of the first unit switch. 3. The unit switch of the third stage is an input line.
N buffers provided for each
Inserted from the cell row written to the
ATM switch according to claim 1, further comprising a means for removing empty cell that is.