AU630728B2 - Switching network for an atm system - Google Patents

Description

11 1~1-_11--1- 3 0 7 2 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED "SWITCHING NETWORK FOR AN ATM SYSTEM" The following statement is a full description of this invention, including the best method of performing it known to us:-

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i e This invention relates to a switching network for an ATM system comprising switches having inputs for receiving cells, outputs for transmitting cells, means for transferring a cell received at any input to any output, and memories for buffering cells, wherein during the passage of each cell through the switching network, the outputs of the traversed switches in a first portion of the switching network are selected independently of the destination of the cell, while the outputs of the traversed switches in a second portion of the switching network are selected in accordance with the destination of the cell.

Such a switching network is known from J.S. Turner, "Design of a Broadcast Packet Network", published in "Proceedings of INTFOCOM '86"1, April 1986, pages 667 to 675.

0000The term "ATM system" (ATM =Asynchronous Transfer Mode) as used herein S means any information transmission system in which the information is split U into par'Ls of equal or unequal length and transmitted, together with a 0 0 oU connection-specific header, as a sequence of packets or cells.

A switching network of the aforementioned type is a switching network with multiple paths. It is constructed exclusively from, 2 x 2 switching elements. Generally, however, switching elements are needed which can arbitrar- 2' ily connect as large a number of inputs to as large a number of outputs as 0 possible. In this marnner, only few stages have to succeed one another, so U that delays, delay jitter, and cell losses are kept to a minimum. However, such switching elements should be comrbined in integrated circuits, in which at U least the numaber of leads cannot be enlarged without difficulty. In ATM sys- 0 tenB, because of the high transmission rate, which is expected to be about 150 Mb/s or even 600 Mb/s, parallel data transfer will frequently be necessary.

It is also known to replace larger switching elemrents by switchingnetwork modules which are constructed from several switching elements and act outwardly like one large switching element. Such a switching-network module should be non-blocking.

According to the invention, there is provided a switching network for an ATM system, comprising switching-network modules each having a plurality of inlets for receiving cells, a plurality of outlets for transmitting cells, and means for transferring a cell received at any of the inlets to any of the outlets, wherein during the passage of each cell through the switching network, the outlets of the traversed switching-network modules in a first portion of the switching network are selected independently of the destination of the cell, while the outlets of the traversed switching-network modules in a second portion of the switching network are selected in accordance with the destination of the cell, wherein each switchingnetwork module comprises a two-stage arrangemnent of switching elements, each switching element having a plurality of inlets, a plurality of outlets, means for transferring a cell received at any of the inlets to any of the outlets, and memories for temporarily storing cells, each inlet of a switching element of a first stage being connected to one of the inlets of the switching-network module, each outlet of a switching element of a second stage being connected to one of the outlets of the switching network module, each switching element of the first stage being connected to each switching element of the second stage.

The invention takes advantage of the peculiarities of the switching network and the mode of operation used. In the switching network and the mode of opero 20 ation used here, wherein the traffic is evenly distributed over the whole switching o network down to the smallest unit, namely a cell, only local, short-time blocking can occur, which can be handled by buffers. This load distribution can be further .0 refined by dividing the cells within the exchange into two or more smaller cells each having a cell header of its own. The additional cell headers increase the total 25 load, however.

As a result of very uniform load distribution, multiple-path capability can be i dispensed with not only within each of the two portions of the switching network, but also within individual switching-network modules. It suffices if, within a switching-network module, one path is possible from every input to every output.

If the capacities of the individual paths are equal, it suffices if the sum of the capacities of all paths is sufficient for carrying the total traffic.

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For a given size of the individual switching-network modules, the number of successive stages must be chosen so that, as required, one path is possible from every input to every output. It turns out that the minimum number of successive stages is also optimal inasmuch as every additional stage not only requires additional circuitry but also results in additional delays, additional delay jitter, and additional cell losses. Additional paths, which are possible for a given size of the switching element without an increase in the number of stages, have no adverse effect. They may even be necessary to make available the total capacity.

A disadvantage of the above mentioned mode of operation is that, unlike in a virtual circuit, the cells belonging to the same connection cannot take the same path and thus may p-ss each other. A simple way of preventing this S has been known for a long tj o000 If cells belonging tog r follow each other closely, the next cells are 0 o delayed at the input of the exchange until the respective preceding cell can 0o no longer be passed. An input conversion unit suitable for this, even though intended for another purpose, is disclosed in the specification of Australian Patent Application No. 45325/89.

The invention will become more apparent from the following description of °200 an embodiment thereof when taken in conjunction with the accompanying 0000 drawings, in which: 0.o Figure 1 shows the structure of a switching network in accordance with the invention; o Figure 2 is another representation of the switching network of Figure 1 which serves to illustrate the mode of operation; Figure 3 shows a switching-network module in accordance with the invention; Figure 4 shows further details of the switching-network module of Figure 3; Figure 5 shows the structure of a switching element, and Figures 6 to 14 show the way cells are written into and read from the buffer.

The switching network of Figure 1 has T terminal units TSU1 TSUT and P switching planes SW1 SWP. In the embodiment shown, T has a maximum value of 128, and P a maximum value of 16. Each terminal unit contains up to 8 line units LT1 LT8 and 4 switching-network modules SM01 SM04. Each switching plane contains two stages of switching-network modules; the first stage contains up to 32 switching-network modules SM101 SM132, and the second stage up to 16 switching-network modules SM201 SM216.

All switching-network modules SM are of identical construction. Each of them has 128 inputs and 128 outputs which act outwardly as a 128x128 matrix.

The switching network is designed as a reverse switching arrangement, ie., the switching-network modules SMO and SM1 of the two front stages, which also act as the fifth and fourth stages, respectively, are used as two 64x64 matrices.

Each of the line units LT contains a line terminating equipment ET and a multiplexer/demultiplexer Muldex, which distributes the incoming traffic to the switching-network modules SM01 SM04 of the respective terminal unit TSU and combines the outgoing traffic in the opposite direction. All paths are designed for 150 Mb/s; between the switching-network modules, every four such paths are combined into one 600-Mb/s path by multiplexing.

Figure 2 shows the sane switching network in a straightforward arrangement. Here, the terminal units TSU and the switching-network modules SMO contained therein appear as an input portion TSUi and an input portion SMOi, respectively, and as an output portion TSUo and an output portion SMOo, respectively. Similarly, the switching-network modules SM1 appear as an input 4' portion SMIi and an output portion SMIo.

For the rest, Figure 2 illustrates the conventional structure of a switching network with an odd number of stages, which may also be regarded as a three-stage arrangement, with the middle stage, in turn, consisting of three stages.

4 i. i L- I Heavy arrows indicate all paths which are possible from an input A to an output B.

In the first half up to the switching-network modules SM2, any output can be taken at any branching point (Muldex, SMOi, SMli). Only in the second half mrust the cells be switched selectively to the desired output B. It is readily apparent that the entire switching network is very uniformly loaded at any time if all cells arriving at any input of any terminal unit are freely dis tributed in the first half of the switching network.

Whether the distribution in the first half is effected cyclically, randomly, or in response to an acknowledgement signal which indicates the load on the succeeding stage is of secondary importance.

Figure 3 shows the coarse structure of a switching-network module SM.

The module has 32 input lines El, E32 with one demultiplexer Dl, D32 each, 32 output lines Al, A32 with one multiplexer Ml, M32 each, and a matrix M. Each denultiplexer Dx separates a 600-Mb/s optical data stream into four 150-Mb/s electric data stream. The multiplexers Mx recombine these four electric data streams into one optical data stream.

400 0Figure 4 shows the internal. structure of the matrix M. The matrix has eight switching elensnts which are arranged in two stages SUll SU14 and SU21 Each switching element has 32 150-Mb/s inputs and 32 150-Mb/s outputs.

The inputs of the first stage are connected via the denultiplexers to the input lines El, E32 of the switching-network module. The outputs of the CO second stage are connected via the multiplexers to the output lines Al, A32 of the switching-network module. From each switching element of the first stage, a group of eight lines runs to each switching element of the second 3 stage.

TIhe extreme case to be taken into account in conventional switching arrangements, namely that all inputs of a switching element of the first stage are fully loaded and that the entire traffic must be routed to a single switching element of the last stage longer than for only a very short time,

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cannot occur here, because no data streams can taken the same path for a prolonged period of time. An interrmdiate stage between the input and output stages can therefore be dispensed with.

A switching element as is needed to imrplement the switching network ac cording to the invention and the switching-network module according to the invention will now be described with the aid of Figure The switching element shown in Figure 5 has p input units IP1, IPp with one input line each, Il, Ip, a multiplexer Mx, a buffer PS with C individually addressable L-bit memory blocks, a demultiplexer Dx, q output units OPi, OPq, a memory management unit SV, and a routing block W.

Preferably, p q 32, ie. the switching element has 32 input lines and 32 output lines. For C and L, numerical values of C 256 and L 50 are currently under discussion. The size of the memory blocks cannot be chosen Q freely. Since, because of the high processing speed, parallel processing will 2 be necessary at least internally, the size of the memory blocks will have to be adapted to the word width created by serial-to-parallel conversion. In the 00present example, word Tidth and size of a memory block are identical. Memory blocks which can hold four, eight, 16 or more words at a time are also possible. What is appropriate depends on the cell length.

0 The input unit IPl shows the internal structure of the input units in 0 C some more detail. The input line Il runs to a synchroniser SYNC, whose output is connected to a serial-to-parallel converter SPW, and the output of the latoo ter is connected via a unit ZAE for detecting starts and ends of cells to the input end of the multiplexer Mx. The unit ZAE is also connected to one input o of the routing block W and to one input of the memory management unit SV.

00 The output unit OKl shows details of the output units. The output end of the demultiplexer Dx is connected via a unit ZE for detecting ends of cells to a parallel-to-serial converter PSW, whose output is coupled to the output line 01. The output unit further includes an output FIFO OFF and an output register CR. The output FIFO OFF has its input connected to one output of the routing bl(ck W, and its output is coupled to the output register OR, which, in turn, is linked bidirectionally with the memory management unit SV.

In Figure 5, the multiplexer Mx and a network of single lines provide the connection between the input units IPI, IPp and the central units, namely the buffer PS, the memory management unit SV, and the routing block W. The data stream is converted to an L-bit parallel format. Neither control and clock lines nor the power supply are shown. The same applies as for switching elements for synchronous systems. Such a switch element, which includes a bus system for interconnecting the units, is described in an article by J.M. Cotton et al, "SYSTEM 12, Digital-Koppelnetz", Elektrisches Nachrichtenwesen, Vol. 56, Number 2/3, 1981, pages 148-160. It should be pointed out that a bus system with a plurality of transmitters and one receiver is equivalent to a multiplexer. The same applies analagously to the output side.

The normal switching process will now be described with the aid of a i greatly simplified example which is illustrated in Figures 6 to 14. In this simple example, the buffer PS has C 14 memory blocks, which are at first all empty. The memory management unit SV is shown by a table-like V representatin of its memories. The heart of the memory management unit SV is a list memory LL, which has one location for each of the C memory blocks of 020 the buffer PS. This location has the same address as the associated memory block and can receive the address of another memory block. At first (Figure 4 6) the list memory LL is empty. The memory management unit SV further includes a memory EFF for storing the addresses of unused memory blocks, which works on the FIFO (first-in-first--out) principle and first contains the addresses of all memory blocks of the buffer PS in a random sequence. The output FIFOs, of which OFFI, CFFi, and OFFl6 are shown, are at first empty, too.

Actualy an "empty" location contains some kind of data, as usual. This may be a value which marks it as empty, but it may also be a value from the previous use which is no longer valid. In the latter case, steps must be taken to ensure that this value will not be requested any more. The memory management 8 unit SV of the present embodiment further includes C locations of a count memory CC, which can be addressed by the list memory LL. The count memory CC indicates to how many output units the contents of the associated memory block of the buffer PS still have to be outputted. The contents of all locations of the count memory CC are initially 0.

On each of the input lines Ii and Ik, one cell now arrives. No further cells arrive in this example. The synchronisers of the two input units IP1 and IPk, together with the respective serial-to-parallel converters, convert each of the cells into five blocks of equal length. The first block SOC1, SOCk begins with a start-of-cell label SOC. The last block EOcl, EOCk coni tains an end-of-cell label EOC. The label EOC lies at an arbitrary point i within the last block, namely where the cell arriving from outside actually Sends. The synchroniser adds blanks to fill che blocks. The remainder of the Sfirst blocks, the second to fourth blocks, lD1, 2D1, 3D1 and 1Dk, 2Dk, 3Dk, respectively, and the portions of the fifth blocks up to the EOC label contain the data of the cells.

'i The input units are cyclically interrogated by the multiplexer Mx. The S units ZAE in the input units IP1 and IPk recognise by the SOC labels that in- Sformation is present which has to be passed on. From the memory EFF, the address 7 is transferred as the address of an unused memory block into an input 44 register IR1, and the first block SOC1 is stored in the buffer PS in memory block 7. At the same time, the SOC label goes to the routing block W and to I the memory management unit SV.

For each switching network stage to be traversed, the SOC label contains, too, in the order in which the stages are to be traversed, information on the output to be selected in this stage. After each evaluation, that part of the path information within the SOC label which is valid for the next stage is brought to the correct position by shifting. The path information may be "Select any output", or "Select any output within a predetermined group of outputs", or "Select a particular predetermined output". Via the path infori mation in the SOC label, the terminal units determine the mode of operation of the switching network.

In the example shown, the output line i is specified. In the output FIFO OFFi, address 7 is noted as the start address of a cell to be outputted by the output unit OPi. In the count memory, a 1"1 is noted in location 7. This is the condition shown in Figure 7.

The next block to be transferred into the buffer PS is the block SOCk from the input IPk. The memory EFF indicates that this block is to be stored in the buffer in memory block 8. The routing block W determines from the SOC label that this cell is to be outputted to both the output line 01 and the output line 0i. This multiple-output capability is a special feature of the switching element describE.d here. It has nothing to do with the structures of the switching network and the switching-network module in accordance with the invention. Address 8 is therefore stored both in the output FIFO OFFl and in the output FIFO OFFi, in the latter in the second location behind the 7. The block SOCk itself is stored in the buffer PS in memory block 8, and in the count memory CC, 11211 is entered into location 8. The 11811 is stored in the input register IRk. This is the condition shown in Figure 8.

Next, the block iDl is stored in the buffer PS in the next unused memory block 2; in the count memory CC, a 1"1 is entered into location 2, and in the list memory, a "12" is entered into location 7. Address 7 was temporarily stored in Ifli as the address under which the preceding block of this cell was o stored. In the same manner, the other blocks from the input units IPi and Ipk are stored.

At the end of the input, shown in Figure 9, the blocks of the cell re- '~ceived from Il are stored in the memory blocks 7, 2, 3, 4 and 6 in this order, and the blocks of the cell received from 1-k are stored in the memory blocks 8, 1, 5, 9, and 13 in this order. The mmory EFF indicates only four unused memory blocks in the buffer PS. The list memory IL contains the above mentioned address sequences, with a special character, here "Ell, entered instead of a link address for the respective last block.

'The output of the cells, which is to follow the complete input, will now be described with the aid of Figures 10 to 14. Output is initiated from the output units; to this end, the output units are cyclically activated.

The output FIFO OFFi indicates that a cell whose first block is stored in the buffer in memory block 8 is to be outputted via the output line 01. Address 8 is transferred to the output register OJRl and applied t1-o buffer PS, list memory LL, and count memory CC; the first block is outputted from PS, the link address 1"1 is transferred from EL to CR1, and the count memory is decremented from 112" to 1"1, cf. Figure Figure 11 shows the next output, which is initiated from OPi. The start address 7 is transferred from OFFi to ORi and applied to PS, LL, and CC; the first block is outputted from PS, the link address 2 is transferred to uRi, and CC is decremented from 1"1 to This "10" indicates that the contents of block 7 in PS are no longer needed; this block is now free, and its address is returned to the memory F for storing the addresses of unused memory el blocks.

V Figure 12 shows the condition which results when one cell has been outputted to 01 and 0i each. The end of a cell is detected both by the units ZEl and ZEi for detecting ends of cells and with the aid of the contents of the K output registers CR1 and ORi. Units not shown cause dummny blocks to be transmitted. OFFi indicates, however, that a further cell has to be transmitted from the output unit OPi, and that the first block of this cell is stored in PS in memory block 8. The output of the cell begins with the condition in Figure 13 and ends with the condition in Figure 14.

All blocks have thus been outputted, buffer PS anet list memory EL are free, all locations of the count memory CC contain a the memory EFF again contains the addresses of all memory blocks of PS, even though in a different order, and dunmy blocks are being transmitted over all output lines.

I ii; lit -liiiii.~l:ii In reality, inputs and outputs need not necessarily be separated in time as described but may occur simultaneously. The buffer PS is designed as a dual-port RAM, so that inputs and outputs can access it independently of each other. This means in particular that the first blocks of a cell can be read out before the last blocks have been written in. This minimises the delay of the cells and the holding time of the buffer PS.

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Claims (4)

1. A switching network for an ATM system, comprising switching-network modules each having a plurality of inlets for receiving cells, a plurality of outlets for transmitting cells, and means for transferring a cell received at any of the inlets to any of the outlets, wherein during the passage of each cell through the switching network, the outlets of the traversed switching-network modules in a first portion of the switching network are selected independently of the destination of the cell, while the outlets of the traversed switching-network modules in a second portion of the switching network are selected in accordance with the destination of the cell, wherein each switching-network module comprises a two-stage arrangement of switching elements, each switching element having a plurality of inlets, a plurality of outlets, means for transferring a cell received at any of the inlets to any of the outlets, and memories for temporarily storing cells, each inlet of a switching ele- ment of a first stage being connected to one of the inlets of the switching-network module, each outlet of a switching element of a second stage being connected to one of the outlets of the switching-network module, each switching element of the first stage being connected to each switching element of the second stage.

2. A switching network for an ATM system as claimed in claim 1, wherein groups of two o" more outlets of a switching element of the first stage of a 20 switching-network module are connected to groups of two or more inlets of a switching element of the second stage of the switching-network module.

3. A switching-network module for the switching network claimed in claim 1, comprising a plurality of inlets for receiving cells, a plurality of outlets for trans- mitting cells, and means for transferring a cell received at any of the inlets to any 25 of the outlets, wherein said switching-network module comprises two-stage ar- rangement of switching elements, each switching element having a plurality of in- lets, a plurality of outlets, means for transferring a cell received at any of the inlets to any of the outlets, and memories for temporarily storing cells, each inlet of a switching element of the first stage being connected to one of the inlets of the switching-network module, each outlet of a switching element of the second stage being connected to one of the outlets of the switching-network module, and each switching element of the first stage being connected to each switching element of the second stage.

4. or of en 4404 0I4 0 6 0 t i £440 0 00 44 0C iu s o i i I i: r i UC BIa* Y eWHt.w sffuite33t!Wntca 1- P _or.t_ A- 14 4. A switching-network module as claimed in claim 3, wherein groups of two or more outlets of a switching element of the first stage are connected to groups of two or more inlets of a switching elemen'. of the second stage. A switching-network module, substantially as herein described with refer- ence to Figs. 3 to 4 of the accompanying drawings. DATED THIS SEVENTH DAY OF SEPTEMBER 1992 ALCATEL N.V. 4444 4 4 a roo 4 4, 4 aa i ,oo+ Io r I II i i t '6>1 I