JP3500511B2 - An input queuing system for connecting to the inputs of a space division switching matrix. - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space-division switch matrix.
g matrix) and an input queuing system whose main purpose is to connect to the input of a g matrix.

[0002]

2. Description of the Related Art Conventionally, an asynchronous time division switching network (async) is used.
hornous time-division swi
Tching networks) are divided into several classification methods, of which two types of fields are the main ones. The first is a queue linked to the output.
s) monitored non-block (non-block)
ing) space-division exchange matrix. "CO
"PRIN" type switches are typical in this field. The second field, on the other hand, uses an input queue monitored by a non-blocking, space-division switching matrix, such as a "BATCHER BANYAN" type switching matrix.

A first field of communication networks
The design has the intractable advantage of being able to accept relatively high internal loading while minimizing idle time and dither.

However, super multiplex (sup)
to a structure called an ermulplex
s) must be transferred in full, and uninhibited switching (uninhibited switching) is used when using relatively high throughputs.
The ability of g) is limited. For example, when the latest technology is used, the processing cost is expected to be about 20 Gbit / sec. This type of technology may be sufficient for many applications.

[0005]

However, if the processing amount is higher than this, it is necessary to make the matrix multistage, and in general, the number of queues through which cells must pass is doubled. Although blocking occurs when communication is established, this parameter does not cause many problems when considering the size of the multiplexing process and the number of multiplexing virtual circuits.

A disadvantage of the second class of conventional communication networks was that the cells could not be distributed during the exchange unless a large number of circuits were added to store and copy the cells. Moreover, the allowable loading is essentially limited to 0.59. Further, compared to the communication network of the first classification, a large delay and a discrete delay are generated in the transverse direction, and it is necessary to increase the number of interconnections as the number of stages increases depending on the design specifications.

Various solutions have been proposed to overcome these constraints, but in many cases they are very expensive. One of the recent proposals is by using content addressable memory (CAM). Here, in the queue output at the moment when the first input cell depends on the resolution of conflicts due to various access requests to the same output originating from other inputs, "BATCHE
It proposes to transform the input queue associated with the "RBANYAN" type switching matrix, and this method is more promising than others. Time slot (time sl)
ot), the request to access the output is directed to the request processing circuit, where for each input queue during the aforementioned time slot, the interval of the request output in terms of all other requests is considered. It provides the first available timeslot to open.

This proposal was proposed by Akata Masao et al.
C Scheduling Content-Addressable Mem for Control of ATM Space Division Switch (A Scheduling Content-Addressable Mem)
ory for ATM Space DivisionSwitch Control) ”, I
EEE Solid-State Circuit
International Conference on Its) (1991), page 244.

Considering the performance of this device, the CAM
Despite the improvement of the memory, the two-access static storage device (dual-
The analysis time required to access the access static memory is tripled. The disadvantage of this method is that it requires dedicated circuitry that operates in a relatively complex manner, which limits the overall exchange throughput.

Although the present invention can perform near the output level of a first field network that uses a non-blocking, space-division switching matrix monitored by output-linked queues, these networks It is an object of the present invention to provide a second field input queuing system that uses a non-blocking, space division switching matrix monitored input queue that can be operated faster. Equivalent technology is being used to try to increase the total exchange throughput by a factor of four.

[0011]

For the above-mentioned purpose, data transmission and / or data transmission
Alternatively, a cell of the type used in an ATM system is received at the input and each output is connected to a corresponding input of the switching matrix, each input circuit further having a one-to-one relationship with the output of the switching matrix. Assigned to a signal by including a sequence of inputs, each of which is designed to carry a sequence of available signals that are assigned to a time slot after the current time slot. For the transmission of cells in timeslots,
Each available signal represents the available state at the matrix output corresponding to the input carrying it, and each input circuit has a memory pocket.
et) has the ability to store one cell present at the input at the address associated with the time slot assigned to the available signal which represents the state available for delivery of the cell to the matrix output addressed. The enable signal represents an unavailable condition after a store operation, the memory is read at the address corresponding to the current time slot and the cell stored at that address is transmitted to the exchange matrix. The inputs of the switching matrix are connected to an input queuing system designed in accordance with the present invention, including:

Further in accordance with the present invention, in each of the input circuits, the available signal carried by the input during the time slots is divided into micro-intervals which are further divided into each time slot. Each is presented to the inputs and each is assigned to a time slot after the current time slot.

Further in accordance with the present invention, these minute intervals are determined by the signal emitted from the time base, which causes the input matrix corresponding to the switch matrix output addressed by the current cell. The storage address of the cell existing at the input of the input circuit is obtained from the value of the minute interval time signal when the available signal represents the available state.

Further in accordance with the invention, each input circuit includes a memory for storing cells present at the input,
The memory is read-addressed by the local time signal sent by the timebase and write-addressed by the minute interval time signal sent by the timebase.

Further, the present invention includes means for preventing further storage of previously stored cells.

Further in accordance with the present invention, each input circuit is provided with m outputs corresponding to the m inputs to which it sends the updated available signal, and the m outputs of the input circuits are Connect to the m inputs of the next input circuit in the series.

Furthermore, the updated available signal transmitted to the m inputs of the input circuit is the m inputs of the next input circuit of the series of input circuits with a delay amount of duration equal to the delay amount of one minute interval. And the time base of the input circuit is offset from one input circuit to the next by one micro interval.

Further in accordance with the present invention, each input circuit verifies the available signals present at the m inputs of the input circuit and the updated available signals to the m outputs of the input circuit. Included is an allocation circuit for applying and sending control signals which, when activated, control the storage of cells present at the input of the input circuit.

Further in accordance with the invention, the assignment circuit includes an input for receiving an output indicator signal representative of the switching matrix output to which the cell currently present at the input of the input circuit is to be addressed.

Further in accordance with the invention, the assignment circuit includes a number of AND gates having at least two inputs, the first input receiving the output indicating signal and the second input receiving the available signal. To receive. Gate output is O
It is connected to the input of the R-gate, the output of which constitutes the output of the allocation circuit. The output of each gate in column j is also connected to one input of an OR gate, the second of which
Of the OR gates respectively receive the available signals and the outputs of the OR gates are respectively connected to the outputs of the allocation circuits which transmit the updated available signals.

[0021]

The foregoing and other features of the present invention can be more clearly understood by reading the following description of an application of the present invention with reference to the accompanying drawings.

The switching communication network shown in FIG.
Individual input circuits CE _{1 to} CE _n and time management (time
Interval management unit U
GIT and system time base (system ti)
me base) input queue management including a time base called BT _s.
management system. The circuit also includes an exchange matrix MatCom.

Each input circuit CE _i is of the form used in data transmission and / or ATM systems,
In particular, it has an input E _i for receiving a cell consisting of a header part in which information about the system, such as the number of virtual circuits to which the cell belongs, is stored and a part in which the message to be transmitted is included. Such a cell is described in European Patent EP-A.
No. 108028.

Each input circuit CE _i has an exchange matrix M
It also has an output S _i connected to one of the n inputs of atCom.

The matrix is non-blocking, and more particularly a non-blocking, space-division switching matrix such as the "BATCHER BANYAN" type, or more generally some non-blocking except by collisions of accesses to simultaneous single outputs. It is a block-type space division exchange matrix. The exchange matrix MatCom does not necessarily include n outputs, and a matrix including m outputs is also considered as will be described later.

Each input circuit CE _i also has _m inputs Ea _{1 to} Eam in a one-to-one relationship with the m outputs of the exchange matrix MatCom, and the m inputs corresponding to the m inputs. also it has outputs _Sa 1 _{~Sa m.} The output Sa _j of each input circuit CE _i is connected to the next input Ea _j of the input circuit _{CE i + 1} of the series of the input circuit _CE 1 _{~CE n.}

The time processing unit UGIT is, on the one hand, the first
Input circuit CE₁M input Ea of ₁~ Ea_mTo each
M output Sit to connect₁~ Sit_mOn the other hand,
Last input circuit CE_nM outputs Sa of₁~ Sa_mTo each
M input Eit which each connects₁~ Eit_mincluding.

The system time base Bt _s sends on the one hand a clock signal Sh whose duration is one-kth of the duration of the time slot T and on the other hand is equal to p times the duration of the time slot, for example a time A sync signal CSY having a duration of eight times the slot T or the like is transmitted. Clock signal Sh and synchronization signal CSY is transmitted to the first input circuit CE _1, propagating from one input circuit CE _i to the next circuit _{CE i + 1.} These are the last input circuits C
It is sent to timed processing unit UGIT from E _n.

The function of the timed processing unit UGIT will be described below.

Referring to FIG. 2 which shows a schematic diagram, the input circuit CE
Continue the explanation of _i .

The illustrated input circuit CE includes a register Reg
It includes AdMtr, conversion memory Mtrad, cell memory MC, delay circuit RET, time base BT, allocation circuit CAF, and toggle switch Basc.

The translation memory Mtrad is a random access memory (RAM), the storage pockets of which are assigned to virtual circuits which can be processed by the system. At system initialization, the translated labels are stored in each of these pockets corresponding to the virtual circuits assigned to the pockets, and may include the addition of self-addressing labels. Each of these pockets corresponding to a virtual circuit
If the number m is equal to the number of outputs of the exchange matrix MatCom, “output instruction (outgoing direction)
n) "bits Bd _{1 to} Bd _m are also stored, and when these bits are set, they are used to specify the matrix output to which the cell containing the number of virtual circuits corresponding to said pocket is to address.

The bit Bd ₁ ~Bd _m, which constitutes the output instruction signal, its structure is different from the binary encoding of other methods for example the m output instruction of the application of the present invention. The latter solution can reduce the amount of conversion memory required to convert the information relating to the output instruction, but requires the use of a decoder circuit, for example incorporated in the allocation circuit CAF.

Virtual circuit V to which the cell present at input E belongs
The wiring representing the CI number is registered in the register RegAd
Connect to the input of Mtr, the output of which is the conversion memory Mt
Connect to the read address input of rad. In read mode, it transmits the translated label E _i , which is transmitted to the corresponding input of the allocation circuit CAF, bits Bd ₁ -B.
It is sent to the input of the memory MC in addition to the d _m.

The wiring representing the number of the virtual circuit is connected to the input of the memory MC via the delay circuit RET. The delay circuit RET is included to compensate for the amount of time delay introduced by the memory Mtrad.

The memory MC has a large number of pockets,
Each is adapted to store all the bits of a particular cell.

The time base BT is controlled by the clock signal Sh received from the system time base Bts and is synchronized by the signal CSY transmitted by the punching input circuit CE. The function of this circuit is to transmit the local time signal Hloc and the minute interval local time signal Mtl. Although one unit of time of the local time signal Hloc corresponds to the time slots T ₀ to T _n , the minute interval time signal is subdivided into time slots T _i , such as the value Hloc + 1 for the first and Hloc + 2 for the second. It is divided into k times the interval that takes a value.

FIG. 3 shows three time slots T ₀ , T ₁ ,
T ₂ which are each a small time interval t ₀ to t ₇
Subdivided into This time is identified by the first input circuit CE ₁
For one input circuit to the next input circuit is offset by the duration of one minute interval, as shown by the thick staircase in FIG.

[0039] Here, k is noted that correspond to the number of pulses of the clock signal Sh to the system time base Bt _s is generated during one time slot T. As can be seen from the description below, the number of k corresponds to the depth of the virtual input queue.

The time base BT of the input circuit CE _i is such that its local time signal Hloc is the input circuit CE _i-1 immediately before.
The time base BT is designed to be placed after one minute interval. Therefore, the time base B of the input circuit CE _i
T is the synchronization signal CS transmitted by the immediately preceding input circuit CE _{i- 1.}
Y is used for the next circuit CE _{i + 1} from the previous signal by 1
A new synchronization signal CSY, which is placed after a minute interval, is transmitted.

Generally, the minute base time signal Mt transmitted by the time base BT during the section t _i of the time slot T _j.
The value of l is the time cell T
It is the value of _{i + j + 1} . That is, during time slot _{T 0,} timed (time interval) signal takes a value such as a time _{t 0} value _{T 1,} the time _{t 1} that the value _{T 2.} Similarly, during the time T ₁ , the value T ₂ is set at the time t ₀ , and the value T ₃ is set at the time t ₂ .

Each pocket of the memory MC is read-addressed by the local time signal Hloc received from the time base BT and write-addressed by the output signal sent by the register REG. The input of the register REG receives the minute interval time signal Mtl transmitted by the time base BT. The register REG has its control input connected to the output S of the allocation circuit CAF.

The allocation circuit CAF has a register Rin ₁
~ Rin _m (each controlled by output instruction bits Bd _{1 to} Bd _m ), sent by the immediately preceding input circuit,
Alternatively, if the input circuit in question is the first of a series of circuits, the available signal s transmitted from the timed processing unit UGIT
d ₁ to SD _m are forms to receive m input i
n _{1 to} in _m . In addition, the circuit has m outputs O
ut ₁ to OUT _m also has, to the input _Ea 1 _{~Ea m} of the m following circuit of a series of input circuits, or, in the case of the input circuit is the last input circuit problems, timed processing unit UGI
To the corresponding input of T, updated availability signal sdr ₁ ~
Send sdr _m . The circuit is a conversion memory Mtrad
Having m inputs _Ebd 1 _{~Ebd m,} each of which receives the m output instruction bits _Bd 1 _{~Bd m} from. The output S of the assignment circuit CAF also has another input, which
There is an assignment signal sent by the toggle switch Basc.

The toggle switch Basc has an input Es connected to the output S of the allocation circuit CAF and an allocation circuit C.
It is connected to the input E of the AF and has an output for transmitting the assignment signal saf. The input Eh of the circuit receives the signal Sh so that it is reset at the start of each time slot T in synchronization with the signal Sh. When the time slot is assigned to the cell existing at the input E of the input circuit CE at time t, the signal saf output from the toggle switch Basc becomes 1, and this level is held until the end of the time slot.

The operation of the input circuit CE according to the present invention will be described below.

When the cell arrives at the input E, it is stored with the header (translated by the memory Mtrad) in the pocket of the memory MC whose address was determined as follows.

At the same time that the converted header Et is supplied, the memory Mtrad outputs the output instruction bits Bd _{1 to} Bd.
_{Since m} is sent and one of them becomes 1, the matrix output for outputting the arriving cell is represented.

During the time slot in question, the inputs Ea ₁ ...
Ea _m is, timed _t of each of the current time slot 0 ~t
It is verified by the assignment circuit CAF during _k .

The cell currently being processed is the exchange matrix Mat.
Assuming we are addressing the jth output of Com, the output indicator bit Bd _j of column j will be one.

During the time period t _i , the j-th input Eaj is 1
, Then time slot T _{a + i + 1} is occupied by the j th output, where a is the sequence of time slots currently being processed.

However, if the j-th input Eaj is 0 at time t _i , the time slot T _{a + i + 1} becomes
Free at the jth output of the exchange matrix MatCom. The assignment circuit CAF in time _{t i} Therefore,
A signal for controlling the register REG is sent from the output S.
The register also sends to the write input of the memory MC the timed signal Mtl received from the time base, which is equal to Ta _{+ i + 1} , as already shown. Therefore, the cell is stored at the address of the memory Mc which is equal to Ta _{+ i + 1} . The assignment circuit CAF also outputs the output O of the column j.
A signal sdr _j , which is 1 here, is transmitted from ut _j , and represents the occupation of the time slot T _{a + i + 1} .

When the allocation circuit CAF controls the register REG, the input Es of the toggle switch Basc is 1. Therefore, the output signal saf also changes to 1 and remains unchanged until the end of the current time slot. Assignment circuit CA
F will therefore no longer assign time slots to the current cell.

During the time slot T _{a in} question, the memory MC receives from the time base BT a read address signal Hloc of a value equal to T _a . The cell stored at this address in the memory MC is sent to the corresponding input of the exchange matrix MatCom which can handle it.

The available signal sd is transmitted from one input circuit to the next input circuit with a delay amount equal in length to one minute interval.
It is also transmitted from the last input circuit to the time management unit UGIT. The delay amount of one minute interval is realized by the registers Rin _{1 to} Rin _m of each input circuit. This delay amount indicates that the local time transmitted by the time base BT of the input circuit is offset by the length of one minute interval as described above.

[0055] In Figure 3, using the arrow A, the exchange between the input circuit _CE 1 _{~CE 6} word constructed by the binding of the available signal _sd 1 to SD _m between the first minute gap _{t 0,}
Use the arrow B, and illustrates the exchange between the input circuit _CE 1 _{~CE 6} configuration the word by coupling of the available signal _sd 1 to SD _m between the second minute gap _{t 1.}

In the first minute interval t ₀ of the time slot T, the time management unit UGIT inputs its Eit _{1 to} Ei during the last minute interval of the immediately preceding time slot.
the availability signal _sd 1 to SD _m that existed t _m, are designed to deliver to the output _Sit 1 _{~Sit m} corresponding thereto. The function of the UGIT unit is represented by arrow C in FIG.

In FIG. 3, it can be seen that the number of minute intervals is one more than the number of input circuits. This allows a very small interval 1
It is possible to generate one offset so that the word present during the first time period of the next time slot always represents a free condition.

FIG. 4 shows a logic circuit diagram of the assignment circuit CAF. This circuit has 3 inputs of m AND gates A
ND _{1 to} AND _m are included. First of gate AND _j of column j
Is an input E that receives the output indicator bit Bd _j of column j
bd _j , the second input is the available bits s of column j
It receives _dj and connects the third inverter input to the input E from which it normally connects to the output of the toggle switch Basc. The outputs of the gates AND _{1 to} AND _m are OR
It is connected to the input of the gate OR _g , whose output constitutes the output S of the allocation circuit CAF.

[0059] The output of the gate the AND _j of row j is also connected to a first input of an OR gate OR _j, receives the available signal sd _j in column j in the second input of the OR gate. The outputs of the OR gates OR _{1 to} OR _m are outputs OUT _{1 to} O, respectively.
Connect to UT _m .

It is now assumed that the input cell has not yet been assigned a time slot and the input E is zero.

The cell currently being processed is the exchange matrix Mat.
Suppose we address the jth output of Com. The output indicator bit Bdj of column j at the input Ebd _j will therefore be 1 and the other bits will be zero.

If the j-th available signal sd _j is 1, then
The AND gate ANDj in column j sends a 1, while the other gates send a 0.

This causes the OR gate OR _g to send 1 which has the effect of controlling the register REG and also changes the signal saf to 1 until the end of the time slot, at the output of the toggle switch Basc, ie at the input E. Have the effect of As a result, during this section, AND _{1 to} AND
The output of all gates up to _m is zero.

Therefore, the toggle switch Basc ensures that a single cell is not assigned to several different time slots and, consequently, is not stored at several different addresses in the memory MC. I know that

Contrary to the above, the j-th available signal sd
_{When j} is zero, the gate OR _g sends a zero because the AND gate AND _j of column j sends a zero and all other gates AND _{1 to} AND _m also send a zero. Therefore, the cell is not stored at the address corresponding to the minute interval in which the above processing is performed.

It will be appreciated that for the purpose of limiting the number of pockets required in the memory MC, the indirect address memory can be used to save the storage address in the memory MC of the input cell. The address of this can be determined by the available address determination device. For example, a memory MC, an indirectly available address memory and a device for determining such an available address are described in detail in French patent FR-A-2617302 and are within the scope of the invention. , And is equivalent to the memory MC described herein in every aspect of its operation.

The allocation circuit can be composed of several basic circuits including registers Rin _{1 to} Rin _m as shown in FIG. The drawing shows such an allocation circuit including K elementary allocation circuits CAF _{1 to} CAF _k and interconnections to the input circuit CE.

[0068] The input _E 1 to E _k assignment circuit _CAF 1 _{~CAF k} all are connected in parallel, to receive an assignment signal saf from toggle switch Basc input circuit CE problems. The OR gate OR _g has K inputs each connected to the output S of the basic allocation circuit, and an output connected to the control input of the register REG of the input circuit in question.

Available signals sd _{1 to s} where M = K × m
d _M is distributed to each of the basic allocation circuits CAF _{1 to} CAF _k , which transmits K × m updated available signals sdr _{1 to} sdr _M.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a switched communication network with an input queuing system according to the present invention.

FIG. 2 is a schematic diagram of an input circuit that constitutes one element of an input queuing system according to the present invention.

FIG. 3 is an operation diagram of an input circuit according to the present invention.

FIG. 4 is a schematic diagram of an allocation circuit incorporated in the input circuit of the system according to the invention.

FIG. 5 is a schematic diagram of a variant of an allocation circuit capable of extending the capacity of the system according to the invention.

[Explanation of symbols]

AND _{1 to} AND _m AND gate Basc means (toggle switch) Bd _{1 to} Bd _m output instruction signal BT time base CAF allocation circuit CE _{1 to} CE
_n input circuit E _{1 to} E _n input Ea _{1 to} Ea
_m Input Hloc Local time signal MatCom
Exchange matrix MC Memory Mtl Minute interval time signal OR _g OR gate OUT _{1 to} O
UT _m output S _{1 to} S _n output Sa _{1 to} Sa
_m output _sd 1 _{~sd m} available signal t ₀ ~t _k
Minute interval

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michel Selbel F-22300 Lannion, Route de Tregastel, Le Rouen Selver (no address) (56) Reference JP-A-5-199574 (JP, A) Kaihei 4-65941 (JP, A) JP 3-187547 (JP, A) JP 3-65841 (JP, A) JP 2-179141 (JP, A) JP 2-87745 ( (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28 H04Q 3/00

Claims (10)

(57) [Claims] 1. An exchange matrix (M) having m outputs.
atCom) input queue to connect to n inputs
A column system comprising a series of n input circuits (CE₁~
CE_n), Each input (E₁~ E_n) Is day
Of the format used for data transmission and / or ATM systems
It is provided to receive cells and its output (S₁
~ S_n) Corresponds to the exchange matrix (MatCom)
Each input circuit (CE₁~ C
E_n) Is a one-to-one relationship with the output of the exchange matrix.
M inputs (Ea₁~ Ea_m) Is further included, and
Each of the input (Ea₁~ Ea_m) Is each time slot
During each session, each tie following the current timeslot
Sequence of available signals (sd
₁~ Sd_m), Each available signal (sd_j)
Cell in the time slot assigned to the signal
The input (Ea) that carries the signal for transmission._j)
Represents the availability status in the matrix output corresponding to
Each input circuit (CE_i) Is for memory (MC)
Within the storage space, the matrix (M
atComm) available to send the cell to the output
Available signal (sd)₁~ Sd_m)
This is assigned to the address associated with the assigned time slot.
Input (E_i) To store the cells existing in
Therefore, the available signal (sd) is not used after the storing operation.
It represents a possible state and the memory (MC) is
This address is read at the address corresponding to the time slot.
The cells stored in the dress are the exchange matrix (M
atCom)).
And the system. 2. Each input circuit (CE _{1 to} CE _n ) inputs (Ea _{1 to} Ea) during one time slot.
_m) Available signal supplied from _(sd 1 _{to SD} m)
Means that each time slot is subdivided so that each is present at said input during a minute interval (t _{0 to} t _k ) assigned to each time slot after the current time slot. The system of claim 1 characterized. 3. The minute interval (t _{0 to} t _k ) is determined by a signal (Mtl) transmitted from a time base (BT), and a cell existing at the input (E _i ) of the input circuit (CE _i ). Storage address of the micro-interval time signal when the availability signal (sd _j ) at the input (Ea _j ) corresponding to the output of the exchange matrix addressed by the current cell represents the availability state. 3. The system according to claim 2, wherein the system is configured to be obtained from the value of (Mtl). Wherein each input circuit _(CE 1 _{~CE n)} includes a memory (MC) for storing the cells present at its input _(E 1 _{~E n),} the memory (MC) during read It is addressed by a local time signal (Hloc) supplied from the time base (BT), and the minute interval time signal (Mtl) supplied from the time base (BT) is addressed to the memory (MC) at the time of writing. The system of claim 3, wherein the system comprises: 5. System according to claim 1, 2, 3, or 4, characterized in that it comprises means (Basc) for preventing further storage of already stored cells. . 6. Each of the input circuits (CE _{1 to} CE _n ) comprises:
m inputs _(Ea 1 _{~Ea m)} has a corresponding updated availability signals _(sdr 1 _{~sdr m) m-number} of outputs is supplied _(Sa 1 -SA _m), the input circuit ( CE _i )
M inputs _(Ea 1 to E of the m output _(Sa 1 _{~Sa m)} The following input circuit in a series of an input circuit _{(CE i + 1)}
a _m ). 6. The system according to claim 1, claim 2, claim 3, claim 4, or claim 5, characterized in that it is connected to a _m ). 7. The m outputs (Sa) of the input circuit (CE _i ).
₁ -SA _m) the updated availability signals are fed to _(sdr 1 _{~sdr m)} is, m inputs of the next input circuit of a series of the input circuit _{(CE i + 1) (Ea} 1 ~E
a _m ), the time base (BT) of the input circuit (CE _i ) is transmitted from one input circuit to the series of input circuits with a delay amount equal to one minute interval. 7. The system according to claim 6, wherein the system is offset to the next input circuit by the length of the one minute interval. 8. Each of the input circuits (CE _i ) is referred to as an allocation circuit (CAF) and the available signals (sd) present at the _m inputs (Ea _{1 to} Eam) of the input circuit (CE).
₁ and for to SD _m) verifying, and for supplying to the m outputs of the input circuit the updated availability signals _{(sdr 1 ~sdr m) (Sa} 1 ~Sa m), the input during operation circuits ( claim, characterized in that it comprises a circuit for supplying the cell present at the input (E _i) of the CE _i), the control signal instructing the memory to the memory (MC) in the output (S) 6 Or the system according to claim 7. 9. The assignment circuit (CAF) is arranged in the switching matrix (MatC) to which a cell currently existing at an input (E _i ) of the input circuit (CE _i ) is about to address.
7. The system according to claim 6, characterized in that it comprises inputs (Ebd _{1 to} Ebd _m ) to which an output indicating signal representative of the output of om) is provided. 10. The assignment circuit (CAF) comprises m AND gates (AND ₁ -A) having at least two inputs.
ND _m ) and includes the AND gates (AND _{1 to} AND
_m ) first input is provided for receiving output indicating signals (Bd ₁ -Bd _m ), and second input is provided for receiving the availability signal (sd ₁ -sd _m ). Yes,
The outputs of the gates (AND _{1 to} AND _m ) are O respectively.
Connected to the input of an R gate (OR _g ), whose output constitutes the output (S) of said allocation circuit (CAF),
The output of each AND gate (AND _j ) in column j is further connected to the first input of an OR gate (OR _g ), respectively,
That the output of the R gate _(OR 1 _{~OR m)} is that is form so as to connect to the output of the assignment circuit supplies available signal _(sdr 1 _{~sdr m)} were respectively updated _(OUT 1 _{~OUT m)} Claim 1, Claim 2, wherein
Claim 3, Claim 4, Claim 5, Claim 6, Claim 7,
The system according to claim 8 or claim 9.