JPS63102527A - Packet exchange - Google Patents

Abstract

PURPOSE:To decrease useless stop of packet transfer by storing an output path number to a register and a packet to a saving FIFO memory provided at a reception section so as to allow a succeeding packet to pass a preceding packet ahead when an outgoing path of a transfer destination to be exchanged is congested and an output waiting FIFO memory corresponding thereto is occupied. CONSTITUTION:Whether or not output waiting FIFO memories 31-3N are occupied is always informed from a packet switch 2 to a control section 13. When an optional output waiting FIFO memory is occupied, the control section 13 writes the number of an outgoing path connecting the said occupied output waiting FIFO memory to an idle outgoing path number register. Then the packet to be transferred to the output path is transferred from a packet reception FIFO memory to the saving FIFO memory corresponding to the register writing the outgoing path number. Every time the occupied output waiting FIFO memory is idle, the packet is transferred to the packet switch 2. During this time, the packet to be given to the other outgoing output path is not saved but transferred.

Description

[Detailed Description of the Invention] [Summary] This application provides a method for determining, when the outgoing route of a packet waiting to be processed inside an exchange is congested, the uncongested outgoing route following the packet is set as the switching destination. This invention discloses a packet switching device that saves packets in a packet save buffer until 'taff is released, and overtakes packets in a queue, so that packets can be exchanged without having to wait.

[Industrial Field of Application] The present invention relates to a packet switch, and more particularly to a device for reducing congestion within the packet switch.

The amount of traffic accommodated by packet switches continues to increase. In particular, the speed of communication between computers is becoming faster than 1 megabit per second.

It is difficult to implement a large-scale packet switch that accommodates such high-speed communications using the current system that relies mainly on software processing. One of the major reasons for this is that in such software-based packet switches, the memory for storing packets is provided in the CPU0 main memory, and management of packet queues, etc. is performed by O8 (operating system) memory management. In packet processing, this memory management places a heavy burden on the CPU, making it difficult to improve packet processing performance.

Therefore, in the processing of the packet switch, the portion related to the packet storage memory is transferred to the FIFO memory (First
A high-speed exchange packet method is becoming popular, which aims to increase the speed by simplifying the processing using a buffer memory (-In-First-Out buffer memory) and converting the processing into hardware.

[Prior Art] FIG. 7 shows the configuration of a packet switching device that employs such a conventional high-speed packet switching method.
1 to IOH, the packet switch 2 extracts the packet, determines the output route from the destination header of the packet, and transfers it to the output waiting FIFO memories 31 to 3N. At this time, if any of the output waiting FIFO memories 31 to 3N is full, the packet is not transferred to that output waiting FIFO memory, and the corresponding packet receiving FI
Store it in FO memory.

When the amount of packet traffic increases, this situation will occur and the packet reception FIFO memory will become full.Then, the packet switch or A command is issued to a terminal (not shown) to stop forwarding the packet.

[While the invention is intended to solve the problem] In this way, in a packet switch, the packet receiving FIF
If the destination of the first packet in the O memory has a wide branch and the output waiting FIF○ memory becomes full, the packets that follow the first packet will be sent to another destination, even if the destination is different: L :Even if it's a direct route, you end up waiting needlessly.

For this reason, the packet reception FIFO memory tends to become full, which also causes an increase in packet delay.

To solve this problem, we need a method that allows subsequent packets to overtake when the first packet is stopped in the PACT reception FIFO memory. Receive FIF○ v1 ability to arbitrarily read each packet in memory is required, and F
This was not possible with IFO memory.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a packet switching device that can discriminate the contents of each packet in a packet reception FIFO memory and process subsequent packets whose exchange destination is an output route that does not have a width difference overtaking a preceding packet. is in

[Means for solving the problem] In FIG. Packet output waiting FIFO corresponding to the
It is a diagram showing the principle of a packet switch according to the present invention provided with memories 31 to 3N, and in the present invention, the packet receiving section 1 is
Packet receiving FIFO memory 10 connected to each input route
, the save FIFO memories 111 to 11M, the output route number registers 121 to 12M provided corresponding to each save FIFO memory 111 to 11N, and the output route number registers 121 to 12M provided corresponding to each save FIFO memory 111 to 11N. When ~3N is full, the number of the output waiting FIFO memory 31~3N is written into the output route number register 121~12M, and the packet reception F uses the output route whose width is compared as the exchange destination.
Only the packets in the IFO memory 10 are saved in the FIFO memories 111 to 11Nl for saving, and the output is kept at r'IF.

FIF memory 1 for saving when memory 31 to 3N is free
FIFO memory 3 waiting to output packets from 11 to 11M
1 to 3N. However, M≦N.

[Operation] In FIG. 1, the control unit 13 includes a packet switch 2.
It is always notified whether each output FIFO memory 31 to 3N is full or not.

Further, the header information of the first packet in the packet reception FIFO memory 10 is always notified to the control unit 13, and the control unit 13 uses this information to determine the output route of the packet transfer destination.

When any FIFO memory with output becomes full, the control unit 13 writes the number of the output route to which the full output waiting FIFO memory is connected to the empty output route number register, and then writes the output route number to which the full output waiting FIFO memory is connected. The packet to be transferred to is transferred from the packet reception FIFO memory to the save FIFO memory corresponding to the register in which the output route number is written. The packets stored in this save FIFO memory are transferred to the packet switch 2 every time a space becomes available in the full output waiting FIFO memory.

During this time, packets that should go to other outgoing routes are transferred without being bypassed by 311.

Also, the congestion on the exit path is resolved and the evacuation FIFO
When the memory becomes empty, it is preferable to erase the contents of the corresponding output route number register. From now on, packets that should go to the corresponding output route are transferred directly from the packet reception FIFO memory to the packet switch 2. Ru.

[Embodiment] FIG. 2 shows an overall view of an embodiment of a packet switch according to the present invention, in which packets received from the incoming path enter the packet receiving section 11 to IN. The packet receiving units 11 to IN analyze the destination header of the packet, determine the output route, and transfer the packet to the packet switch 2. When the output waiting FIF○ memory 3□ to 3N of the output route is full, vTer is performed to the save FIFO memory or the packet reception FIF○ memory in the packet receiving unit 11 to IN. The packet receiving units 11 to IN can know whether each output waiting FIFO memory is full or not using the output route status notification bus 4.

FIG. 3 shows the packet format, and the packet received from the incoming route has the format shown in FIG. 3 (IL). Each packet receiving unit determines the outgoing route number of the forwarding destination from the destination header as described later, adds this outgoing route number to the beginning of the packet as shown in FIG. 3(b), and sends it to the packet switch 2. Forward. The packet switch 2 transfers the packet to a predetermined output waiting FIFO memory according to the output route number at the beginning of the packet. At this time, as shown in FIG. 3(c), the leading exit route number is removed.

FIG. 4 shows an example of a specific configuration of the packet receiving section, in which packets received from the incoming path are sent to the packet receiving F.
The data is input to the IFO memory 1o.

The first packet in the packet reception FIFO memory 10 is
Only the destination header (FIG. 3) is first extracted, and the output route number determination logic 21 unilaterally determines the output queue of the transfer destination. This outgoing route number determination logic 21 is a known logic that can be easily configured using a mapping memory. The determined outgoing route number is notified to the transfer control unit 22.

On the other hand, in this embodiment, a 1gl save FIFO memory 11 is used. Also, from the save FIFO memory 11, a signal indicating whether it is full or not (full flag) and a signal indicating whether the save FIFO memory 11 is completely empty or not are sent. It is always sent to the transfer control unit 22.

Further, in the outgoing route number register 12, the outgoing route number issued by the outgoing route number determination logic 21 is written and erased by the transfer control unit 22. This output route number register 12
The transfer control unit 22 is also notified of the outgoing route number written in the outgoing route number register 12.

Further, the transfer control unit 22 always knows whether each output waiting FIFO memory 3 is full or not via the output route status notification bus 4. In addition, the logic 21 and the transfer control unit 22
, a combiner 23 (which adds an outgoing route number to the received packet as shown in FIG. 3(b)), an input regulation logic 24 (to be described later), and switches SWI and SW2 to control the control unit 13t! of FIG. - constitutes.

The transfer control unit 22 receives the above-mentioned signals and controls the switches SWI and SW2 to transfer the packet reception FIFO memory 10 → packet switch 2 packet reception FIFO memory 10 → evacuation FIFO memory 11 Packets are transferred through each route: memory 11 → packet switch 2.

Hereinafter, the operation of the transfer control unit 22 of the packet receiving unit 1 will be explained as follows.
This will be explained with reference to the flowchart shown in the figure.

First, the transfer control unit 22 receives an "empty flag" signal and checks whether the output route number register 12 is empty (step Sl in FIG. 5), and if it is empty, the packet reception FIFO memory 10 is If it is "empty", do nothing and return to step S1, but if it is not "empty", the output route number determination logic 21 of the first packet of the packet reception FIFO memory 10 is checked.
It is checked based on the information from the bus 4 whether the output waiting FIFO memory 3 of the output route determined in is full (S3), and if it is not full, switches SW1 and SW2
The packet with the output route number added as shown in FIG. 3(b) is transferred to the packet switch 2 (S4 in the same figure).
), if it is full, the output route number register 12 is filled with
Write the already determined outgoing route number (S5), and then switch SW to transfer the first packet in the packet reception FIF○ memory 10 to the save FIFO memory 11.
I (S6) and wait until the uneven width on the exit road side is resolved.

Since the output route number that caused the conflict is now written in the output route number register 12, it is determined in step 81 that the output waiting FIFO memory 3 of the output route indicated by the register 12 is still full. If it is still full, check whether the packet reception FIFO memory 10 is "empty" (S8), and if it is, it will not be empty, and if it is not empty, it will continue to the above first packet. The latter packet, that is, this is the current first packet, and in the same way as in step S3 above, check whether the output waiting FIFO memory 3 of the output route determined by the logic 21 is full or 100 (S9). If the packet is full, it waits without doing anything, and if it is not full, switches SWI and SW2 are switched and the packet is sent to switch 2 (IO 5).

On the other hand, when the output waiting FIFO memory 3 of the destination output route is no longer full in step S7, the packet stored in the save FIFO memory 11 is taken out and sent to the bucket switch 2 by controlling the switch SW2 ( Same 5
11) I am doing this.

As mentioned above, if the output path width comparison state continues, the save FIFO memory will also become full, so stop the transfer from the packet reception FIFO memory to the save FIFO memory, and If the output queue is full after comparing the widths of the output routes, if there is no empty output route number register, the packet should go to another output route in the receive FIFO memory. Packets are stopped, but if this situation continues, the packet reception FIFO memory will eventually become full, and the input regulation logic 24 (Figure 4) will stop the packet switching equipment or terminal (not shown) at the end of the input path. ), such a situation is the worst case, but usually only a few outgoing routes are congested for a short time, so in most cases it can be absorbed by the evacuation buffer. Packets to outgoing routes that are not congested will be forwarded without being blocked. The order of packets remains the same for all calls.

FIG. 6 shows an example of the packet switch 2, and the packets inputted to the packet switch 2 from each of the packet receiving sections 11 to IN are sent to FIFO memories 30t to 3ON for - and interfaces. Accumulated. The packet receiving section address counter 31 generates an address for scanning each interface FIFO memory 301 to 3ON and sends it to the address bus 32, and if a packet is in the interface FIFO memory 301 to 3ON, it is sucked out from the transfer bus 33. The packet is sent to the packet transfer circuit 34, and the output route number (FIG. 3(b)) information at the head of this packet is sent to the output route address register 35.
As a result, one of the output waiting FIFO memories 31 to 3N is selected by the output route address bus 36, and the packet is transferred from the transfer bus 33 to this output waiting FIFO memory. At this time, the output route number information at the head of the packet is removed by the output route number removal circuit 37.

In the above embodiment, the evacuation FIF of the packet receiving section
Although the number of O memories is one, it can be increased to n (n-1 to the number of output routes).

[Effects of the Invention] According to the packet switch of the present invention, when the output route of the transfer destination to be exchanged is congested, the corresponding output waiting FIFO is
Evacuation FI provided in the receiver when the memory becomes full
Packets are stored in the FO memory and the outgoing route number is stored in a register, allowing subsequent packets to overtake the preceding packets, reducing unnecessary stops in packet transfer, reducing packet exchange delay and throughput (data flow rate). ) can be improved and the packet order does not change for each call.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of a packet switch according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG.
a) to (C) show the packet format used in the present invention, 4th IJ is a block diagram showing one embodiment of the packet receiving section, and FIG. 5 shows the operation sequence of the transfer control section of the packet receiving section. FIG. 6 is a diagram showing a configuration example of a packet switch, and FIG. 7 is a block diagram showing a conventional high-speed packet switch. In FIG. 1, 1 is a packet receiving unit, 2 is a packet switch, 31 to 3N are output waiting FIFO memories, 10 is a packet reception FIFO memory, 111 to 11M are save FIFO memories, 121 to 12+
Reference numeral 4 indicates an output route number register, and reference numeral 13 indicates a control unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A packet receiving unit (1) is provided between each input route and a packet switch (2), and between the packet switch (2) and each output route, a packet is received corresponding to each input route. A packet switch equipped with output waiting FIFO memories (3_1 to 3_N), in which the packet receiving section (1) has packet receiving FIFO memories (1 to 3_N) connected to each input path.
0), save FIFO memories (11_1 to 11_M), and output route number registers (12_1 to 12_M) provided corresponding to each save FIFO memory (11_1 to 11_M).
Then, the output path becomes congested and the corresponding output waiting FIFO memory (3
When _1 to 3_N) is full, the corresponding output waiting FIF
O memory (3_1 to 3_N) numbers are written to the output route number registers (12_1 to 12_M), and the packet reception FIFO is set to the congested output route as the exchange destination.
Only the packets in the memory (10) are stored in the save FIFO.
The packet is saved in the memory (11_1 to 11_M), and when the output waiting FIFO memory (3_1 to 3_N) becomes empty, the packet is transferred from the saving FIFO memory (11_1 to 11_N) to the output waiting FIFO memory (3_1 to 3_N). A packet switch comprising: a control unit (13). (2) The control unit (13) erases the contents of the corresponding outgoing route number register when the save FIFO memory (11_1 to 11_N) becomes empty. packet switch.