JPH0779252A - Packet output control system - Google Patents

Abstract

PURPOSE:To decrease the abolition ratio of a packet in a buffer memory provided at the intersection of an input and output highway in a packet output control system in a packet switchboard. CONSTITUTION:The packet switchboard in which the packet inputted to plural input highways 1 is stored in a buffer memory 3 provided at the intersection with an output highway 2, and outputted to the output highway 2, is equipped with a storage amount monitoring means 5 which transmits information when the buffer memory whose storage packet amount is beyond a thereshold value is generated. A reading control part 10 which operates control for outputting the packet stored in each buffer memory 3 through an outputting part 4 to the output highway is also equipped with a successive reading control means 11 which selects the buffer memory in a constant sequence, and executes the output of the packet, and a maximum storage buffer priority reading control means 12 which executes the priority output of the packet stored in the buffer memory 3 whose packet storage amount exceeds the thereshold value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet output control system in a packet switch, and more particularly to a packet output control system in a crosspoint buffer type packet switch in which a buffer memory is provided at an intersection of an input highway and an output highway.

In a packet switch for exchanging packets from a plurality of input highways to a plurality of output highways, packets input from a plurality of input highways and directed to the same route are connected to the same output highway corresponding to the route. In this case, a buffer memory (hereinafter referred to as a buffer memory) is provided to prevent packets from a plurality of input highways from colliding with each other. The format of the buffer memory is divided into several types depending on the arrangement position of the buffer memory, but there is a difference in the total memory amount and the necessity of converting the packet transfer rate depending on the format. Further, there are various methods for controlling the reading of the buffer memory, but in particular, the packet discard rate when packets are concentrated from a specific input highway to the same output highway, and the time required from the arrival of packets to the output The time (hereinafter referred to as the output delay time) and its variation greatly differ depending on the read control method.

Therefore, there is a demand for a packet output control method that does not require conversion of the packet transfer rate, has a low packet discard rate, and has a small output delay time and its fluctuation.

[0004]

2. Description of the Related Art FIG. 12 is a diagram for explaining the structure of an ATM switch.
13 is an explanatory diagram of an output buffer format, FIG. 14 is an explanatory diagram of a crosspoint buffer format, FIGS. 15 to 17 are prior art configuration diagrams, and FIGS. 18 to 20 are conventional buffer memory accumulation state explanatory diagrams. Is.

FIG. 12 shows an ATM which is a kind of packet switch.
3 is a diagram showing a switch configuration of the exchange. Broadband ISDN is being put to practical use as a next-generation communication network that integrates various types of communication services such as voice, data, and moving images. ATM (Asynchronous Transfe
r Mode: Asynchronous transfer mode) is the core technology of this technology.It does not depend on the generation status of continuous information such as moving images or burst information such as data, or the communication speed of various information, and all information is fixed length. This is a technique for high-speed transfer in units of packets (53 bytes) called cells, which are divided into (48-byte length) blocks and added with a 5-byte header.

In the ATM switch, information is transmitted in packets (hereinafter referred to as
Since the cells are exchanged on a packet-by-cell basis)
As shown in 12, the transfer destinations of the packets input from the plurality (N) of input highways 1 are selected by the address filter (AF) 32, and only the packets destined for the same route are assigned to the one route. Output to output highway 2 (indicated by output highway #i). At this time, in order to avoid collision of packets connected from the N input highways 1 to the same output highway 2, the input packets are temporarily stored in the buffer memory 3 and then sequentially output to the output highway. . The write control unit 30 of FIG. 12 controls writing of packets input to each input highway 1 into the buffer memory 3, and the read control unit 30 controls the buffer memory 3.
This is a part that controls the reading when the packets stored in the output highway 2 are output. As shown in the figure, the packet transfer rates of the input highway 1 and the output highway 2 are usually the same (Vb / s).

There are several types of methods for arranging the buffer memory 3 in FIG. 12, and FIGS. 13 and 14 show typical buffer memory type configurations. Figure 13 is called output buffer memory type (hereinafter referred to as output buffer type).
When there are N input highways 1 and output highways 2 as shown in (1) of the figure, the buffer memory (B
M) 3 is arranged corresponding to the output highway 2.

FIG. 13 (2) shows only one output highway 2 (output highway #i) in order to explain the operating principle. The packets input from the N input highways 1 are time-division multiplexed in the concentrator 33 and output to the output highway 2. When the transfer speed of the packets of the input / output highway is Vb / s, the time is At the time of division multiplexing, it is necessary to set the speed to NVb / s, which is N times, and write it in the buffer memory 3, then read it at the speed Vb / s and output it to the output highway 2. In this format, since the buffer memory 3 is aggregated for each output highway 2, the total memory amount is small, but it is necessary to increase the internal speed of the concentrator 33 and the write speed of the buffer memory. Becomes expensive and difficult to control.

FIG. 14 is called a crosspoint buffer memory type (hereinafter referred to as a crosspoint buffer type), which is a type in which a buffer memory is arranged at the intersection of an input highway and an output highway. Although (1) of FIG. 14 illustrates the position of the buffer memory 3 in the overall configuration, and (2) of the same figure illustrates only one output highway (output highway #i) 2 is extracted, (2) in the figure
Shows the principle of operation in which a packet is read from the buffer memory 3 that captures the circulating token and is output to the output highway 2 (the token is a well-known technique, and detailed description thereof is omitted).

Since the buffer memory 3 is dispersed in the crosspoint buffer format, if the packet discard rate due to the overflow of the buffer memory is kept at the same value as the output buffer format, the total amount of memory becomes large, but the writing of the buffer memory 3 is performed. Since the read speed may be Vb / s, which is the same speed as the input / output highway, the control becomes easy.

As described above, although the output buffer format and the crosspoint buffer format have advantages and disadvantages, a crosspoint buffer that can be used for a low-speed general-purpose memory device that is becoming cheaper even if the total amount of memory is increased. The format is often adopted. Hereinafter, description will be made on the premise of the crosspoint buffer format.

FIGS. 15 to 17 show the portions related to the buffer memory in the crosspoint buffer type packet switch according to the read control method of the buffer memory. Each of the figures shows an example in which a packet input from four input highways 1 is output to one output highway 2, but the input highway 1 has a packet that has passed through an address filter (see FIG. 12), that is, , Only packets for the same route are input, and the output highway 2 indicates the highway corresponding to that route. Note that the write controller is not shown in each drawing.

15 to 17, BM-A to B provided corresponding to the four input highways (# 1 to # 4) 1
The four M-D buffer memories 3 (hereinafter referred to as BM-A and BM-B when referring to individual buffer memories) are first-in first-out (hereinafter FI).
(Hereinafter referred to as FO) type memory, and the packets input first in each buffer memory are stored in the input order starting from the first packet. The packet accumulated at the head address is read by the control of the read control unit and output to the output highway 2 via the output unit 4. When the head packet is read, the subsequent packets are sequentially directed to the head address. It is designed to step forward.

The packet is read from the buffer memory 3 which captures the token circulating in the output unit 4. The tokens are circulated in the order of BM-A, BM-B, BM-C, and BM-D. Whether or not each buffer memory 3 can capture the token, in other words, whether it is read or skipped is read. Determined by the control of the controller. Figure 15 ~
The read control units of FIG. 17 have different read control methods, but each will be described below for each drawing.

FIG. 15 is a block diagram of a conventional technique using a skip polling type (or a buffer sequential reading type) as a read control method for a buffer memory. The skip polling control unit 41 of the read control unit 40 sets the token of the output unit 4 to BM-
A, BM-B, BM-C, and BM-D are read in this order, but the buffer memory 3 in which no packet is stored at the head address is skipped (skipping).

FIG. 18 is a diagram for explaining the storage state of the buffer memory 3 and the packet input / output state in the configuration of FIG. This figure shows the buffer memories BM-A-B at the packet input timing (shown by S1-S10) shown in (2) of FIG.
The packet accumulation state of each buffer memory when a packet is input to MD is described according to the passage of time. In the figure, A1 indicates the first packet input to the buffer memory BM-A and A2 indicates the packet input next to the BM-A, but the same applies to other packets. The height of each of the buffer memories BM-A to BM-D represents the number of stored packets, and the lowest packet is at the head position.

The token read cycle is shown at the bottom of FIG. 18, but for convenience of explanation, the packet is stored in the buffer memory 3
It is assumed that the time (hereinafter referred to as the input time) accumulated in is synchronized with the token read cycle, and that the read is one cycle after the packet input time at the earliest. Further, the reading order of the packets input at the same time is such that the packet stored in the buffer memory 3 in which the circulating token arrives earlier is read first.

In the read control by the skip polling control unit 41 shown in FIG. 15, the packet arrival sequence S as shown in FIG.
The packet A1 input to the BM-A at 1 is read at the next token read cycle, and the BM is sent at the packet arrival order S2.
With respect to the packets B1 and C1 which are simultaneously input to −B and BM-C, the packet B1 is read first from the token position, and then the packet C1 is read.

The packets are read out in the same manner, and the packets are output to the output highway 2 in the order shown in the output HW of FIG.
In the illustrated example, packets are continuously input from the input highway # 3 and are accumulated in the corresponding BM-C, but the tokens are circulated in the order of BM-A, BM-B, BM-C, BM-D. Therefore, packets are not continuously read from the same buffer memory 3. For this reason, the packets stored in the BM-C are often output earlier than the packets input from other input highways or even when they are input at the same time. In the example shown in the figure, C4, C
The packets of 5, C6, and C7 are output earlier than the packets stored in the other buffer memory 3 or the packets are input at the same time although they are input at the same time.

This means that packets waiting for output are gradually accumulated in the buffer memory 3 to which packets are continuously input. For convenience of explanation, if the storage capacity of each buffer memory 3 is three, packet C in the figure
5, C6 and C7 cannot be accumulated in BM-C and are likely to be discarded.

As described above, the skip polling type read control method is extremely simple in control, but in the case where packets are continuously input to the same route such as burst traffic, the output delay time is increased. Is large, and the packets are accumulated in the buffer memory accordingly, and the packet discard rate also becomes high.

Next, FIG. 16 will be described. FIG. 16 is a block diagram of a prior art using a read control method of the maximum storage buffer priority read type devised to eliminate the drawbacks of the skip polling type. The maximum storage buffer priority read-out method is to perform polling so as to read from the buffer memory having the maximum number of stored packets (number of queues).
(Largest Number of cells in the Queue, Note) Described as a polling method. (Note. IEICE, Communication Technique SS
E92-88, Somiya et al., "A Study on Burst Traffic Characteristics in ATM Concentrators," Nov. 26, 1998).

In the configuration of FIG. 16, the storage amount monitoring unit 53 monitors the packet storage amount of each of the buffer memories BM-A to BM-D, and the monitoring result is the LNQ polling control unit of the read control unit 50.
Notify 51. The LNQ polling control unit 51 compares the packet storage amounts of the buffer memories BM-A to BM-D,
The identification information of the buffer memory 3 having the largest storage amount is sent to the token of the output unit 4, and the packet stored in the buffer memory 3 is read out. When there are a plurality of buffer memories 3 with the maximum storage amount, for example, two buffer memories 3, the two buffer memories 3 are read alternately in accordance with the token circulation order.

FIG. 19 is a diagram for explaining the storage state of the buffer memory 3 and the packet input / output state in the configuration of FIG. The packet input order is the same as in FIG. 18, and the illustrated method is also the same as in FIG.

In the method of FIG. 16, when the buffer memory 3 having the maximum storage amount is generated, the packet stored in the buffer memory 3 is preferentially read. In the example of FIG. 19, BM-C and BM-A (temporary) have the maximum storage time for a long time, but as a result of being preferentially read, for example, packets such as C4, C5, and C6 are shown in FIG. It is read much faster than in the skip polling method. Further, along with this, the amount of packets accumulated in the BM-C decreases, and the time during which the accumulated amount increases becomes shorter, so the packet discard rate becomes lower than that of the skip polling method. Figure
In the case of 19, if the storage capacity of each buffer memory 3 is three, the packet C6 is discarded, but if C6 is discarded, C7 is likely to be able to be stored. The number is smaller than in Fig. 18.

However, while the LNQ polling method preferentially reads the buffer memory 3 having a large storage amount, the buffer memory 3 having a small storage amount is read later. Figure
As shown in FIG. 19, although the packet B2 accumulated in the BM-B, which has a small accumulation amount, is input earlier, the output time is later than the later input packets C3 to C6 and A3. There is. That is, the LNQ polling type is
The output delay time of the packet input from the input highway 1 with less traffic to the one-way path becomes large, and the output delay time depends on the storage state of the other buffer memory 3, so that the output delay time also fluctuates. It has the drawback of becoming large.

Next, FIG. 17 will be described. FIG. 17 is a block diagram of a prior art using a read control method that prevents an increase in packet output delay and an increase in output time fluctuation in a route with a lot of traffic or a route with a small amount of traffic, such as a skip polling type or an LNQ polling type. . In the configuration of FIG. 17, the arrival order storage unit 62 is connected to the input highway 1 to store the arrival order of the packets input to all the input highways 1. The information stored in the arrival order storage unit 62 is information for identifying a packet that has arrived (hereinafter referred to as packet information), and for example, address information or the like is used. FIG. 7B shows a state in which the packet information is stored in the memory (not shown) in the arrival order storage unit 62.

The arrival order storage unit 62 notifies the read control unit 60 of the stored packet identification information by the FIFO method in the order of arrival. In the example of (2) of FIG.
Of the packet A1 is transmitted, and then the information of the packets B1 and C1 of the packet arrival order S2 is transmitted. Thereafter, the arrival order of the packets is similarly notified, but the FIFO polling control unit 61 of the read control unit 60 uses the arrival order storage unit.
The tokens of the output unit 4 are instructed to be read in the order input from 62.

FIG. 20 is a diagram for explaining the storage state of the buffer memory 3 and the packet input / output state in the configuration of FIG. 17, but the packet input conditions and the illustrated method are the same as in FIG. As shown in FIG. 20, the input packets are output almost in the order of arrival, although the packets may move back and forth depending on the position of the token. Therefore, according to this method, only a specific packet is not accumulated in the buffer memory 3 for an extremely long time, but it is not preferentially output even if the accumulated amount increases, so that the burst traffic is input. In this case, the packet discard rate is higher than that of the LNQ polling method in FIG. When comparing the packet accumulation states of BM-C in FIG. 19 and FIG. 20, the maximum number of accumulated packets is the same, but in FIG. 20, the time for accumulating the maximum number of packets is longer. It is clear that there is a difference in the packet discard rate between the two.

[0030]

As described above, in the packet output control method of the prior art, the skip polling type read control method is stored in the buffer memory in which packets destined for the same route are continuously input. In addition, the packet output delay time becomes large and the packet discard rate also becomes high. Further, the LNQ polling type read control method has a drawback that the output delay time of a packet input from an input highway with less traffic to the same route and the fluctuation of the output delay time are large. Furthermore, F
The IFO polling type read control method has an advantage that input packets are output in the order of input, but has a problem that the packet discard rate is not necessarily low.

Therefore, there is a demand for a packet output control method that can obtain a low packet discard rate without the output delay time of an input packet and its variation becoming extremely large.

An object of the present invention is to reduce the packet discard rate in the buffer memory provided at the intersection of the input / output highways.

[0033]

FIG. 1 is a diagram for explaining the principle of the present invention, and FIGS. 2 and 3 are diagrams for explaining another principle of the present invention. In the figure, 1 is a plurality of input highways into which packets destined for the same route are input, 2 is an output highway corresponding to the destination route of the input packets, and 3 is an intersection of a plurality of input highways 1 and output highways 2. First-in first-out (FIFO) type buffer memory provided for input highway,
An output unit 4 outputs the packets stored in the buffer memory 3 to the output highway 4, and 10 and 20 sequentially read the packets temporarily stored in the buffer memory 3, and output the output unit 4
It is a read control unit that controls the output to the output highway 2 via.

Reference numeral 5 monitors the amount of packets accumulated in each buffer memory 3, and when the buffer memory 3 has accumulated the amount of packets exceeding a predetermined threshold value, the packet accumulation amount of the buffer memory 3 becomes the threshold value. Storage amount monitoring means for sending out information indicating that the packet storage amount has exceeded the threshold value, 6 is identification information of the packet input from the input highway 1 and the arrival order of the buffer memory 3 in which the packet is stored. Are stored so that they can be identified, and the identification information is sequentially transmitted in the order of arrival.

Reference numerals 11 and 12 are provided in the read control unit 10, and
Is a buffer sequential read control unit that controls the output unit 4 to select the buffer memory 3 in a fixed order and output the packet stored at the head of the selected buffer memory 3 to the output highway 2, and 12 is a storage amount monitoring unit. 5, while the information indicating that the buffer memory 3 in which the packet storage amount exceeds the threshold value is generated is sent, the buffer memory in which the packet storage amount exceeds the threshold value is given priority over the read control by the buffer sequential read control means 11. 3 is a maximum storage buffer priority read control means for controlling the output unit 4 so as to read the packet from the packet 3 and output it to the output highway 2.

Reference numerals 21 to 23 are provided in the read control section 20, and each time 21 receives the identification information of the packets sequentially sent from the arrival order storage means 6, the packets are read from the buffer memory 3 in which the packets are stored. Arrival order read control means for controlling the output section 4 to read out and output to the output highway 2, 22 is sent from the storage quantity monitoring means 5 information indicating that the buffer memory 3 in which the packet storage quantity exceeds the threshold value is generated. During this time, the maximum storage buffer priority is controlled so that the output unit 4 is read out from the buffer memory 3 whose packet storage amount exceeds the threshold value and output to the output highway 2 in preference to the read control by the arrival order read control means 21. Read control means, 23 is maximum storage buffer priority read control means 22
Of the packet identification information of the packet in the buffer memory 3 which has been preferentially output by the maximum storage buffer priority reading control means 22 and stored in the arrival order storage means 6, It is a preferential read packet information erasing means for controlling to erase the identification information.

Reference numeral 24 is provided in the read control section 20 in place of the priority read packet information erasing means 23, has a built-in counting means corresponding to the buffer memory 3, and is controlled by the maximum storage buffer priority read control means 24. When a packet is read from the buffer memory 3, 1 is added to the numerical value indicated by the counting means corresponding to the buffer memory 3, and the buffer memory instructed when the arrival order read control means 21 receives a subtraction instruction. 1 from the numerical value indicated by the counting means corresponding to 3
Is a priority read packet number storage means for reducing

25 is provided in the arrival order read control means 21 when the priority read packet number storage means 24 is provided in the read control section 20, and the arrival order read control means 21 outputs the buffer memory 3 to the output section 4. When performing control to read out the packets stored in, the numerical value indicated by the counting means corresponding to the corresponding buffer memory 3 in the priority read packet number storage means 26 is confirmed, and if the numerical value is 1 or more, the packet is read out. It is a read skip processing means for omitting the control and instructing the counting means corresponding to the corresponding buffer memory 3 in the priority read packet number storage means 26 to subtract 1 from the numerical value displayed by the counting section.

[0039]

In FIG. 1, packets input from a plurality of input highways 1 and addressed to the same route are temporarily stored in a buffer memory 3 provided corresponding to the input highways 1.
The buffer sequential read control means 11 sequentially selects the buffer memory 3 in a fixed order and controls the output unit 4 to output the packet accumulated at the head of the selected buffer memory 3 to the output highway 2. By this control, the output unit 4 causes the head packet of each buffer memory 3 to be output to the output highway 2. Since the buffer memory 3 is a FIFO memory, when the leading packet is read, the packets inputted afterward step by one toward the leading position.
Since the buffer memory 3 in which no packet is stored in the first packet indicates that no packet is stored, the buffer sequential read control means 11 skips (skips) the buffer memory 3.

On the other hand, the storage amount monitoring means 5 monitors the amount of packets stored in each buffer memory 3,
When the buffer memory 3 in which the accumulated amount of packets exceeds the preset threshold value is generated, the information notifying the occurrence of the buffer memory 3 in which the threshold value is exceeded is continuously transmitted to the read control unit 10 until the accumulated amount becomes equal to or less than the threshold value.

When this information is received, the maximum storage buffer priority read control means 12 of the read control unit 10 gives priority to the read control by the buffer sequential read control means 11 until the information is exhausted, and the buffer whose packet storage amount exceeds the threshold value. Memory 3
The output unit 4 is controlled so that the packet is read out and output to the output highway 2. When a large number of packets are input to the buffer memory 3 and the accumulated capacity of the buffer memory 3 is exceeded, the subsequent packets are discarded, but in FIG. 1, as described above, when the accumulated amount of packets exceeds the threshold value. Since the packet is preferentially read from the buffer memory 3, the possibility that the packet will be discarded is reduced.

Next, the operation of FIG. 2 will be described. Similar to FIG. 1, packets destined for the same route input from a plurality of input highways 1 are temporarily stored in the buffer memory 3 provided corresponding to the input highways 1, but in the case of FIG. The storage unit 6 stores the identification information of the packets input from the input highway 1 so that the arrival order and the buffer memory 3 in which the packets are stored can be identified, and then sequentially outputs the arrival order information to the read control unit 20.

Each time the arrival order read control means 21 of the read control section 20 receives this arrival order information, it controls the output section 4 to read the packet from the corresponding buffer memory 3 and output it to the output highway 2. Therefore, in the configuration of FIG. 2, the packets are output in the order of arrival.

On the other hand, the storage amount monitoring means 5 monitors the amount of packets stored in each buffer memory 3 as in FIG. 1, but when the buffer memory 3 in which the packet storage amount exceeds the threshold value is generated, Read out information to inform
Send to 10. When this information is received, the maximum storage buffer priority read control means 22 of the read control unit 10 gives priority to the read instruction from the arrival order read control means 21 to read the packet from the buffer memory 3 and outputs the highway 2 until the information is exhausted. Then, the output unit 4 is instructed to output. Therefore, even if packets destined for the same route are intensively input to a specific input highway, the packet discard rate does not increase.

By the way, in the reading by the maximum accumulation buffer priority reading control means 22 in FIG. 2, a situation occurs in which the packet arrival order stored in the arrival order storage means 6 is ignored and the packet arriving later is output first. Therefore, it is necessary to delete, from the packet identification information stored in the arrival order storage means 6, the identification information of the packet that is output with priority.

Therefore, when the maximum accumulation buffer priority reading control means 22 preferentially reads a packet from the buffer memory 3 in which the packets exceeding the threshold value are accumulated, the identification information of the packet is notified to the priority readout packet information erasing means 23. To do. Upon receiving this notification, the priority read packet information erasing means 23 erases the identification information of the packet from the identification information of the packet stored in the arrival order storage means 6.

Next, the operation of FIG. 3 will be described. Also in FIG. 3, as in FIG. 2, the arrival order read control means 21 of the read control unit 20 normally reads the packet from the corresponding buffer memory 3 according to the information from the arrival order storage means 6 and outputs it to the output highway 2. Also in 3, the packets are output in the order of arrival. Further, when the buffer memory 3 in which the packet storage amount exceeds the threshold value is generated, the maximum storage buffer priority read control means 22 preferentially reads the packets stored from the buffer memory 3 as in the case of FIG. is there.

In FIG. 3 as well, when the maximum storage buffer priority read control means 22 performs the read operation, the packet arrival order stored in the arrival order storage means 6 is ignored and the packets that arrive later are output first. Occurs,
In FIG. 3, the packet identification information in the arrival order stored in the arrival order storage unit 6 is not erased, and processing is performed so that the output of the packet is not confused.

Therefore, the priority read packet number storage means 24 of FIG. 3 is provided with a counting means (not shown) corresponding to the buffer memory 3. This counting means has an initial value of 0.
The maximum storage buffer priority read control means 22
Each time a packet is read from the buffer memory 3 whose threshold value has been exceeded by the control of step 1, 1 is added to the numerical value indicated by the counting means corresponding to the read buffer memory 3. Therefore, the numerical value of the counting means indicates the number of packets read out with priority.

When the packet storage amount of the buffer memory 3 becomes equal to or less than the threshold value, the reading of the buffer memory 3 is again performed by the arrival order reading control means 21. The arrival order read control means 21 controls the reading of packets according to the packet identification information output from the arrival order storage means 6 as in the first case. At this time, the packet identification information output from the arrival order storage means 6 includes the identification information of the packet preferentially output under the control of the maximum accumulation buffer priority reading control means 22, but the arrival order reading control is performed. Prior to the means 21 instructing the output section 4 to read, the read skip processing means 25 accesses the priority read packet number storage means 24 and displays the numerical value of the counting means corresponding to the buffer memory 3 in which the packets are accumulated. Check.

When the numerical value indicates 1 or more, the packet read out preferentially from the buffer memory 3 is 1
Since there are more than one, the read skip processing means 25 causes the arrival order read control means 21 to omit the read from the buffer memory 3. Therefore, the arrival order read control means 21
The read skip processing means 25 subtracts 1 from the value of the counting means corresponding to the corresponding buffer memory 3 of the priority read packet number storage means 24. Therefore, the numerical value indicated by the counting means indicates the number of times (the number of packets) from which reading from the buffer memory 3 should be omitted thereafter.

By repeating the above, the numerical value of the counting means corresponding to the corresponding buffer memory 3 sequentially decreases, but when the numerical value of the counting means becomes 0, it indicates that there is no preferentially output packet. Therefore, thereafter, the arrival order read control means 21 controls the reading of the packets in the arrival order according to the packet identification information output from the arrival order storage means 6.

The method of FIG. 3 has the same operation as that of FIG. 2 in that it does not perform further reading from the buffer memory 3 which has been preferentially read, or prevents the already read packets from being read in duplicate. However, the processing becomes simpler than that of the priority read packet information erasing means 23 of FIG.

[0054]

FIG. 4 to FIG. 6 are configuration diagrams of an embodiment of the present invention, FIG. 4 is a principle explanatory diagram of FIG. 1, FIG. 5 is a principle explanatory diagram of FIG.
FIG. 4 is a configuration diagram of an embodiment based on the principle explanatory diagram of FIG. 3. FIG. 7 is an explanatory diagram of a packet information storage state in the arrival order storage unit of the embodiment of the present invention, FIGS. 8 and 9 are buffer memory accumulation state explanatory diagrams of the embodiment in the configuration of FIG. 4, and FIGS. FIG. 7 is an explanatory diagram of a buffer memory storage state of the embodiment in the configurations of FIGS. 5 and 6.

Throughout the drawings, the same reference numerals denote the same objects, 11 is a skip polling control unit for realizing the buffer sequential read control unit 11 in FIG. 1, and 12 is an LNQ polling control unit in FIG. An embodiment of the read control means 12, 21 is a FIFO polling control unit shown in FIGS.
2, an LNQ polling control unit 22 is an implementation form of the maximum storage buffer priority read control unit of FIG. 2 and FIG. 24A to 24D are counters (hereinafter referred to as CNT) provided in the FIFO polling control unit 21.
-A to CNT-D), and corresponds to the one explained as the counting means in the explanation of the action. Reference numeral 25 is a read skip processing unit (NRC), which is an implementation of the read skip processing means 25 in FIG.

In the configuration diagrams of FIGS. 4 to 6, only four input highways # 1 to # 4 are described as the input highway 1, and the buffer memory 3 also corresponds to the four input highways 1 and the BM-A. Only four of BM-D are described. In the following, if the buffer memory 3 is explained individually, B
M-A to BM-D are used.

Next, each drawing will be described. The configurations and basic operations of the input highway 1, the buffer memory 3, the output unit 4 (including the token) and the output highway 2 are the same as those described in the prior art. Since it exists, only a brief explanation will be given. Further, since the basic operation of the configurations of FIGS. 4 to 6 is the same as the contents described in the explanation of the operation, duplication is avoided, and a concrete model will be described focusing on packet input / output and storage conditions.

First, the configuration of FIG. 4 will be described with reference to FIGS. 7, 8 and 9. Packets input to the four input highways # 1 to # 4 of FIG. 4 are stored in the corresponding buffer memories BM-A to BM-D in the order of input. The storage amount monitoring unit 5 uses the buffer memories BM-A to BM.
Although it is monitored whether the number of packets accumulated in -D exceeds a preset threshold value, this threshold value is set to "2" for convenience of explanation. As described above, since the buffer memory 3 is a FIFO memory, when the first packet is output, the subsequent packets sequentially advance toward the first packet, but the above-mentioned premise is a state in which two packets are accumulated. Then, when the third packet is input, the read control unit 10 is notified that the accumulated amount of the buffer memory 3 exceeds the threshold value.

First, the operation in the state where all the buffer memories 3 do not exceed the threshold value will be described. (1) of FIG. 7 is used as the packet input order. FIG. 7 is a diagram for explaining the storage state of the arrival order storage unit 6 described later, but it is also used as a model of the input order. Of FIG.
(1) is the packet A1 to the BM-A at the input time S1.
It is illustrated that the packet B1 and the like are similarly input to the BM-B at the time of S2, but the input timing of S1, S2, etc. is the same as in the prior art from the convenience of the description, as in the prior art, the read cycle of the token of the output unit 4. It is assumed to be synchronized with. In the BM-A, these packets, for example, the packets A1 to A4 are packed and stored in order from the head address (not shown), and disappear when output. The arrow in the token direction in FIG. 7 indicates the buffer memory 3 related to the output order of packets.
It shows the selection order of. FIG. 8 shows the storage states of the buffer memories BM-A to BM-D and the input / output states of packets when a packet is input according to the input model of (1) of FIG. 7. The output HW of FIG. 2 shows the order in which packets are output. In the configuration of FIG. 4, when there is no buffer memory 3 that stores packets exceeding the threshold value, output is performed under the control of the skip polling control unit 11. However, as shown in FIG. 8, in this input model, BM-A, BM- All of the three buffer memories B and BM-D are set to 1 before the second packet is input.
Even if the BM-C outputs two packets and the BM-C stores two packets at the same time, packets exceeding the threshold (three) are not stored.

The tokens of the output unit 4 are BM-A and BM-
After circulating through B, BM-C, and BM-D and then returning to BM-A again, it may be output after being input earlier than packet B2 as in packet C2 in FIG.
In some cases, such as the packet C4, the packet A4 and the packet B3 are input before the packets A4 and B3, but the packets are output after the packet A4 and the packet B3. Even in the skip polling control, there are few packets that are not output for an extremely long time after being input.

Next, the case where the buffer memory 3 accumulating the packets exceeding the threshold value occurs will be described. In this case, (2) in FIG. 7 is used as the input model. In addition,
This input model is the same as that used to describe the prior art.

FIG. 9 shows the buffer memories BM-A to BM- when a packet is input at the input time shown in (2) of FIG.
The storage status of D and the input / output status of packets are shown. In the example of FIG. 9, after the packet A2 is output to the output HW,
The packet B2 should have been output by the skip polling control, but since the packet C4 is stored in the BM-C as the third packet when the read cycle comes, the storage amount monitoring unit 5 in FIG. From the read control unit 10 to BM-
It is notified that the packet storage amount of C has exceeded the threshold value.
Here, for convenience of explanation, it is assumed that the read control unit 10 immediately shifts to the control by the LNQ polling control unit 12 upon receiving this notification.

In the control by the LNQ polling control unit 12, the packet is read out preferentially from the buffer memory (BM-C in this case) that exceeds the threshold, so that the BM-
The packet C2 accumulated at the head of C is read. When the packet C2 is read, the packet storage amount of the BM-C becomes two below the threshold value, but since the third packet C5 is stored in the next read cycle, the packet from the BM-C continues. Reading is performed. Thereafter, similarly, the packets are read from the BM-C only up to the packet C5.

When the packet C5 is output, the packet storage amount of the BM-C becomes equal to or less than the threshold value, so the control of the read control unit 10 returns to the skip polling control unit 11. At this time, the token is BM immediately after the end of reading the packet C5, and thus BM
Starting with reading -D, packet D2 is read. Hereinafter, the packets A3 and B2 are read in this order.

Here, FIG. 9 is compared with FIG. 18 of the prior art in which reading is performed only by skip polling control. Although the input models of FIG. 9 and FIG. 18 are exactly the same, comparing the output timing of each packet, in FIG. 18, the packets C4 to C7 continuously input to the BM-C are output last. On the other hand, in FIG. 9, when the accumulated amount exceeds the threshold value, BM-
Since packets are read from C first, packets C4 to C7
Does not occur until the end of the output is not output.

As described above, in FIG. 9, even if packets are continuously input to the same buffer memory BM-C, the packets are not accumulated as they are, so that the possibility that the packets overflow from the buffer memory 3 is reduced, and the packet discard rate is reduced. Is reduced. This can be confirmed by comparing FIG. 9 and FIG. That is, in FIG. 18, four or more (maximum five) packets are accumulated, whereas in FIG. 9, BM-C is used.
There is no situation where four or more packets are accumulated in. If the storage capacity of the BM-C is three, the packets C5, C6, and C7 are likely to be discarded in FIG. 18, but
In FIG. 9, packets are not discarded. That is, it is clear that the packet discard rate of FIG. 9 is lower than that of FIG.

Next, FIG. 9 will be compared with FIG. 19 of the prior art in which reading is performed only by LNQ polling control. 9 and 18 have the same input model, it is clear that the packet discard rate is lower in FIG. 9 here as well.

Further, in the configuration of FIG. 4, when the buffer memory 3 in which the accumulated amount of packets exceeds the threshold value is generated, the read of the buffer memory is prioritized, so that the packet B2 of FIG. Occurs. In this respect, there does not seem to be a large difference between FIG. 9 and FIG. 19, but this is due to the threshold being set low from the convenience of explanation. If the threshold is set high, a packet whose output time is greatly delayed occurs only when concentrated traffic is added to a specific buffer memory 3. On the other hand, in FIG. 19, even if the traffic is low, if there is the buffer memory 3 accumulating more packets than BM-B, the output timing of the packets accumulated in BM-B may be significantly delayed. high.

From the above, it is apparent that the configuration of FIG. 4 is superior to the prior art in which reading is performed only by LNQ polling control in both the discard rate and the packet delay time.

Next, FIG. 7, FIG. 10 and FIG.
11 will be explained together. In the configuration of FIG. 5, if there is no buffer memory 3 that stores packets exceeding the threshold value,
The output is performed under the control of the O polling control unit 21, and when the buffer memory 3 accumulating the packets exceeding the threshold value is generated, the control is switched to the control of the LNQ polling control unit 22.

First, a case will be described in which a packet is input according to the input model of (1) in FIG. 7 and the accumulated packets of all buffer memories 3 do not exceed the threshold value. FIG. 10 is a diagram for explaining the storage states of the buffer memories BM-A to BM-D and the input / output states of packets in that case.

In FIG. 5, the arrival order storage unit 6 stores the arrival order of packets input to the input highway 1 in a memory (not shown). Although FIG. 7 has been used to explain the input model up to now, it is a diagram for explaining a state in which the arrival order of packets is originally stored in the memory of the arrival order storage unit 6. The arrival order storage unit 6 stores the arrival order of packets for each buffer memory. In this case, S1 to S in FIG.
Reference numeral 12 corresponds to the relative address of the memory area in the arrival order storage unit 6 provided corresponding to BM-A to BM-D, and it can be considered that S1 indicates the head address of each memory area.
Further, as described in the description of the conventional technique, A1 to D4 are not the packet body accumulated in the buffer memory 3 but the packet information such as address information.

The memory of the arrival order storage unit 6 is also a FIFO type memory. For example, when the packet information A1 stored in S1 at the head address is output to the read control unit 20, S2 is output.
The packet information B1 stored in 1 is advanced to the head address, and the following packet information is also sequentially advanced by 1 address. However, the packet information stored in this memory is stored in the buffer memory 3
Unlike the packet stored in, the packet is not stored in the arrival order storage unit 6 in the buffer memory unit at the head address.

As described above, the arrival order storage unit 6 is shown in FIG.
The packet information stored as shown in (1) is stored at the head address S.
FIFO polling control unit in the reading control unit 20 sequentially from 1
The FIFO polling control unit 21 controls the output unit 4 to read the packets designated by the packet information from the corresponding buffer memory 3 in the order in which the packet information is received. As a result, the packets are output in the order shown in the output HW of FIG.

In FIG. 10, all buffer memories BM-A to BM
-D does not accumulate packets above the threshold, so there is no big difference from the output order in FIG. 9, but in the case of FIG.
Although the output order of the packets input at the same time may be changed depending on the position of the token, the packets input later will not be output first, unlike FIG. 9.

Next, when the buffer memory 3 in which the packet storage amount exceeds the threshold occurs, that is, when the packet is input as shown in (2) of FIG. 7, the storage information of the buffer memory 3 and the input / output status of the packet Will be described with reference to FIG. In this case, the FIFO polling control unit 21 tries to output the packet B2 after outputting the packet A2 to the output HW, but since the packet accumulation amount of the BM-C exceeds the threshold because the packet C5 is input, this From the time point, the read control unit 20 shifts to the control by the LNQ polling control unit 22. After that, only the BM-C is read until the packet C5 is output, and when the output of the packet C5 is finished, the control is returned to the control by the FIFO polling control unit 21.

Here, the storage state of the memory of the arrival order storage unit 6 will be described. The storage state of the memory of the arrival order storage unit 6 in this case is shown in (2) of FIG. Since the memory of the arrival order storage unit 6 is a FIFO memory, the packet information stored in S4 of (2) of FIG. 7 is at the head address when the packet A2 is output.
Before the polling control unit 21 reads the packet B2, L
Packet C at address S5 by NQ polling controller 22
3, packet C4 at address S7, packet C5 at address S8
Is read.

Each time the packets C3, C4, C5 are read, if the memory of the arrival order storage unit 6 is stepped up, the information of the packets B2, D2, A3, A4 which have not been output yet is lost, so the FIFO polling control unit 21 To LNQ
When the control is transferred to the polling control unit 22, the stepping (FIFO operation) of the memory of the arrival order storage unit 6 is stopped. Therefore, in this case, the process is stopped with the address S4 being the leading address.

When the LNQ polling control unit 22 starts the control, it controls the output unit 4 to read the BM-C as described above. The identification information of the packet read at that time (received from the arrival order storage unit 6). Stored packet information) is sent to the priority read packet information erasure processing unit 23. The priority read packet information deletion processing unit 23 sends this packet information to the arrival order storage unit 6 and deletes the packet identification information from the memory of the arrival order storage unit 6.

Therefore, when the packet storage amount of the BM-C becomes less than or equal to the threshold value, that is, when the output of the packet C5 is completed, the memory of the arrival order storage unit 6 stores the S in (2) of FIG.
The packet information of No. 4 is at the head address, and C3, C
The packet information of C4 and C5 has been deleted. The packet accumulation amount of BM-C becomes less than or equal to the threshold value, and FI
When the control returns to the FO polling control unit 21, the FIFO polling control unit 21 restarts the reading of the buffer memory from the packet stored in S4 of FIG. 7 (2), but does not remember that the reading of the packet A2 is completed. Since the packet B2 is already read, the packet B2 is restarted.

When the reading of the packet B2 is completed by the packet information stored in S4, the packet information stored in the memory of the arrival order storage unit 6 advances by one address, but the identification information of the packet C3 is deleted. For S5
Does not remember anything. Therefore, the memory further advances, and S6 becomes the leading address. Since the FIFO polling control unit 21 controls to read the packet stored in S6, the packet B as shown in the output HW of FIG.
Packet D2 is output subsequent to 2.

Here, FIG. 11 is compared with FIG. 20 of the prior art in which reading is performed only by the FIFO polling control.
Although the input model is exactly the same in Fig. 11 and Fig. 20, looking at the output order of each packet, Fig. 18 shows that the output in the input order, which is a feature of FIFO polling, is maintained. On the other hand, in FIG. 11, since priority is given to the reading of the BM-C exceeding the threshold value, the output of some packets, such as the packet B2, stored in the other buffer memory 3 is delayed.

However, comparing the storage amounts of the buffer memory 3, the BM-C with a large number of input packets is shown in FIG.
And there is a big difference between Fig. 20. That is, in FIG. 11, the packet accumulation amount is 3 or less even after the third packet C5 exceeding the threshold is input, whereas in FIG. 20, the time when the packet accumulation amount is 4 or more is compared. Lasts for a long time. If the storage capacity of the buffer memory 3 is, for example, three packets, the packets C6 and C7 are likely to be discarded in FIG. 20, while the packets are not discarded in FIG.
That is, the packet discard rate is obviously lower in FIG.

Next, FIG. 11 is compared with FIG. 19 of the prior art in which reading is performed only by LNQ polling control. If the two figures are compared taking into account the comparison results of each method so far, it is clear that the packet discard rate is lower in FIG. 11 here as well. Further, in FIG. 11, the output order of the packets is substantially in accordance with the input order except during the time of preferentially outputting the packets of the buffer memory BM-C in which the packets exceeding the threshold value are accumulated. Therefore, it is apparent that FIG. 11 is superior in terms of packet transmission delay and delay variation.

Next, the configuration of FIG. 6 will be described.
11 is exactly the same as that of FIG. 5, and since the storage state of the buffer memory 3 and the input / output status of the packet are the same as those of FIG. 11, the description of the packet read control is omitted and the priority read packet number storage The section 24 and the read skip processing section (NRC) 25 will be mainly described.

As described with reference to FIG. 5, in the read control method in which the FIFO polling control is performed in the normal state and the read of the buffer memory 3 is prioritized when the buffer memory 3 storing the packets exceeding the threshold occurs. The packet information output by the arrival order storage unit 6
It is necessary to perform processing such that the buffer memory is not preferentially read even after the packet storage amount of the buffer memory 3 that has been subjected to the preferential reading becomes equal to or less than the threshold value. FIG. 6 shows the latter process.

When the packet polling control unit 21 of FIG. 6 outputs the packet A2 to the output HW and the packet C5 is input to the BM-C, the packet storage amount of the BM-C exceeds the threshold value. The read control unit 20 shifts to the control by the LNQ polling control unit 22, and the LNQ polling control unit 22 first reads the packet C3. At this time, L
The NQ polling control unit 22 stores the priority read packet number storage unit 24.
The information for informing the execution of the priority read is sent to. When the packet C3 is read from the BM-C in this state, a signal (hereinafter referred to as a read signal) that can detect that the packet is read from the BM-C, for example, a read enable signal of the buffer memory 3 (a known technique). Therefore, detailed description is omitted) is output to the counter CNT-C in the priority read packet number storage unit 24. Counter 24A to 24D
Has an initial value of "0", but when the read signal is sent from the buffer memory 3 in the state where the information notifying the execution of the priority read is sent from the LNQ polling control unit 22, the buffer read A counter (CNT-C in this case) corresponding to the memory 3 is incremented. Since the priority reading is performed until the packet C5 is output, the CNT-C is incremented even when the packets C4 and C5 are read, and when the priority reading is completed, the numerical value stored in the CNT-C is “3”. Becomes

When control returns to the FIFO polling control unit 21 in this state, the FIFO polling control unit 21 obtains packet information in the arrival order from the arrival order storage unit 6 and restarts the packet reading control by the FIFO polling control. At this time, the memory of the arrival order storage unit 6 is as shown in FIG.
Although S4 in (2) is the head address, the identification information of the packets C3 to C5 is not deleted in the configuration of FIG. 6 and remains as it is.

When the FIFO polling control unit 21 restarts the read control, it first starts the operation of reading the packet B2 as in FIG. 5, but at this time, the read skip processing unit 25 in the FIFO polling control unit 21 stores the packet B2. Counter CNT corresponding to the stored buffer memory BM-B
-Check the value of B. Since the corresponding buffer memory BM-B has not been preferentially read in CNT-B, the numerical value indicates "0" which is the initial value. The read skip processing unit 25 informs the main body of the FIFO polling control unit 21 of this. If the numerical value of the counter does not indicate a number of 1 or more, the FIFO polling control unit 21 controls the reading so that the packet B2 is read from the BM-B.

As a result, the memory of the arrival order storage unit 6 advances and S5 shown in (2) of FIG. 7 becomes the head address. FI
The FO polling control unit 21 obtains the identification information of the packet C3 stored in S5 and starts the read operation, and like the case of the packet B2, the read skip processing unit 25 stores the packet C3 in the buffer memory BM-C. Check the value of the counter CNT-C corresponding to. At this time CNT-C
Displays "3" as described above, but if the value of the counter indicates a number greater than or equal to 1, the read skip processing unit 25 decrements the value of the counter and
The O polling control unit 21 is made to omit the reading of the packet (packet C3 in this case) at that time.
Therefore, even if the packet information remains in the memory of the arrival order storage unit 6, the packet C2 may be output again, or another packet may be preferentially read from the buffer memory BM-C that is below the threshold value. There is no. At this point, the numerical value of the counter CNT-C becomes "2".

Thereafter, similarly, the FIFO polling control unit 21 reads the packets D2, A3, A4, but omits the read control of the packets C4, C5 in the meantime. When the reading of the packet C5 is omitted, the value of the counter CNT-C becomes "0", so that the subsequent reading from the buffer memory BM-C is normally performed. As a method of preventing the reading from the buffer memory 3 that has been preferentially read from being confused after the packet storage amount becomes equal to or less than the threshold value, the method of FIG. Figure 5
There is a feature that processing is simpler than the method of.

Although the embodiment of the present invention has been described with reference to FIGS. 4 to 11, FIGS. 4 to 11 merely show a part of the embodiment of the present invention, and the contents illustrated by the present invention. It goes without saying that it is not limited to only. For example, FIGS.
In the description of 11, the token is circulated in the output unit 4, but there are various methods for the output unit 4 to select the buffer memory 3 in addition to the method of using the token. It is clear that the effect of does not change. In addition, the priority read packet number storage unit 2
4, especially counters CNT-C to C provided therein
Although the NT-C is provided inside the read control unit 20 in FIG. 6, the effect of the present invention does not change even if these are provided outside the read control unit 20.

Further, in FIGS. 8 to 10, the input / output status of the packet is explained by using a specific input model. However, since the characteristics are qualitative, each characteristic is lost even if the input model changes. It is clear that the superiority or inferiority does not change between each configuration or the conventional technology.

[0094]

As described above, in the packet switching system in which the buffer memory is provided at the intersection of the input highway and the output highway to temporarily store the input packet and then output the packet to the output highway, the same packet is output from the specific input highway. When burst-shaped packets are input to a route, the packets are concentrated and accumulated in the buffer memory corresponding to the input highway, which may increase the packet discard rate. When the packet amount reaches or exceeds a predetermined threshold value, the packets accumulated in the buffer memory are output preferentially, so the packet discard rate can be reduced. Output delay time of packets stored in a small buffer memory and fluctuation of output delay time are extremely large. That phenomenon is avoided. Therefore, the present invention greatly contributes to the performance improvement and the quality of service of the packet switch.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (1)

FIG. 2 is an explanatory diagram of the principle of the present invention (2)

FIG. 3 is an explanatory view of the principle of the present invention (3)

FIG. 4 is a block diagram of an embodiment of the present invention (1)

FIG. 5 is a configuration diagram of an embodiment of the present invention (2)

FIG. 6 is a configuration diagram of an embodiment of the present invention (3)

FIG. 7 is an explanatory diagram of a storage state of an arrival order storage unit according to the embodiment of this invention.

FIG. 8 is an explanatory diagram (1) of the storage state of the buffer memory according to the embodiment in the configuration of FIG. 4;

FIG. 9 is an explanatory diagram (2) of the storage state of the buffer memory according to the embodiment in the configuration of FIG. 4;

FIG. 10 is an explanatory diagram (1) of the storage state of the buffer memory according to the embodiment in the configuration of FIGS.

FIG. 11 is an explanatory diagram (2) of a buffer memory storage state according to the embodiment in the configuration of FIGS. 5 and 6.

FIG. 12 is an explanatory diagram of the structure of an ATM switch.

[Figure 13] Output buffer format configuration diagram

[Figure 14] Crosspoint buffer format configuration diagram

FIG. 15 is a configuration diagram (1) of a conventional technique.

FIG. 16 is a block diagram of a conventional technique (2)

FIG. 17: Configuration diagram of conventional technology (3)

FIG. 18 is an explanatory diagram (1) of a storage state of a buffer memory according to the related art.

FIG. 19 is an explanatory diagram of a storage state of a buffer memory according to the related art (2)

FIG. 20 is an explanatory diagram (3) of a buffer memory accumulation state of the related art.

[Explanation of symbols]

 1 Input Highway 2 Output Highway 3 Buffer Memory 4 Output Unit 5 Accumulation Amount Monitoring Means 6 Arrival Order Storage Means 10, 20 Read Control Unit 11 Buffer Sequential Read Control Means 12, 22 Maximum Accumulation Buffer Priority Read Control Means 21 Arrival Order Read Control Means 23 priority read packet information erasing means 24 priority read packet number storage means 25 read omission processing means

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Hiroshi Tomonaga Hiroshi Tomonaga 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Kazushi Kamoi, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A first-in-first-out system provided at the intersection of a plurality of input highways (1) to which packets addressed to the same one-way route are input and an output highway (2) corresponding to the one-way route corresponding to the plurality of input highways (1). After temporarily storing the packets input to the buffer memory (3) of the method, the read control unit (10) controls the read from the buffer memory (3), and the output unit (4) outputs the output highway (2 ) Is a packet output control method of a packet switch, the amount of packets accumulated in each buffer memory (3) is monitored, and the buffer memory (3) that accumulates an amount of packets exceeding a predetermined threshold value. When the above occurs, the storage device includes a storage amount monitoring means (5) for transmitting information indicating that the packet storage amount of the buffer memory (3) exceeds the threshold value until the packet storage amount becomes equal to or less than the threshold value, and control In (10), select the buffer memory (3) in a certain order, and output the packet stored at the head of the selected buffer memory (3) to the output highway (2). ) Is controlled by the buffer sequential read control means (11), and the storage amount monitoring means (5) while the information indicating that the buffer memory (3) in which the packet storage amount exceeds the threshold value is generated is sent, The output unit (4) reads the packet from the buffer memory (3) whose packet accumulation amount exceeds the threshold and outputs it to the output highway (2) in preference to the read control by the buffer sequential read control means (11). A packet output control method comprising a maximum storage buffer priority read control means (12) for controlling the packet output. 2. The first-in first-out provided at the intersection of a plurality of input highways (1) to which packets destined for the same one-way route are input and an output highway (2) corresponding to the route, corresponding to the plurality of input highways (1). After temporarily storing the packets input to the buffer memory (3) of the method, the read control unit (20) controls the read from the buffer memory (3), and the output unit (4) outputs the output highway (2 ) Is a packet output control method of a packet switch, the amount of packets accumulated in each buffer memory (3) is monitored, and the buffer memory (3) that accumulates an amount of packets exceeding a predetermined threshold value. When an error occurs, a storage amount monitoring means (5) for transmitting information indicating that the packet storage amount of the buffer memory (3) exceeds the threshold value until the packet storage amount becomes equal to or less than the threshold value, and the input highway (1 ) The storage device further comprises arrival order storage means (6) for storing the identification information of the input packets so that the arrival order can be identified from the buffer memory (3) in which the packets are stored, and then sequentially transmitting the identification information in the arrival order. And each time the read control unit (20) receives the identification information of the packets sequentially transmitted from the arrival order storage unit (6),
Arrival order read control means (21) for controlling the output unit (4) to read the packet from the buffer memory (3) in which the packet is stored and output the packet to the output highway (2)
And the read control by the arrival order read control means (21) while the information indicating that the buffer memory (3) in which the packet storage amount exceeds the threshold is generated is sent from the storage amount monitoring means (5). The maximum storage buffer priority read control means (22) for controlling the output unit (4) to read the packet from the buffer memory (3) whose packet storage amount exceeds the threshold and output it to the output highway (2) ), And the identification information of the packet preferentially output by the maximum storage buffer priority read control means (22) is received from the maximum storage buffer priority read control means (22), and the arrival order storage means is received.
(6) A packet output control method comprising a priority read packet information erasing means (23) for controlling to erase the identification information of the packet from the identification information of the packet stored in (6). 3. The priority read packet information erasing means (23)
Instead of the above, the counting means provided corresponding to the buffer memory (3) is built-in, and the maximum storage buffer priority reading control means (2
When a packet is read from the buffer memory (3) by the control of 4), 1 is added to the numerical value indicated by the counting means corresponding to the buffer memory (3), and the arrival order read control means (21) If a subtraction instruction is received, a priority read packet number storage means (24) for subtracting 1 from the value indicated by the counting means corresponding to the instructed buffer memory (3) is provided, and the arrival order read control means is provided. In the (21), the arrival order read control means (21) stores the buffer memory for the output section (4).
When controlling to read the packets stored in (3),
The numerical value indicated by the counting means corresponding to the corresponding buffer memory (3) in the preferential read packet number storage means (26) is confirmed, and if the numerical value is 1 or more, the packet read control is omitted and the priority is given. A read skip processing means (25) for instructing the counting means corresponding to the corresponding buffer memory (3) in the read packet number storage means (26) to subtract 1 from the numerical value indicated by the counting means is provided. The packet output control system according to claim 2, characterized in that