JP3848962B2 - Packet switch and cell transfer control method - Google Patents

Description

  The present invention relates to a packet switch and a fixed-length packet transfer control method, and more particularly to an asynchronous transfer mode (ATM) packet switch having a congestion control function and a cell transfer control method in an ATM network.

Regarding the transfer of fixed-length packets (hereinafter referred to as “cells”) in ATM networks, for example, “Data Commu-nication Using ATM: Architecture, Protocols, and Resource Management” IEEE Communication Maggin August 1994, p24-31, “ SVC Signaling: Calling All Nodes ”DATA COMMUNICATIONS JUNE 1995, p123-128, etc.
In an asynchronous transfer network, a signaling process at the time of outgoing call is performed along a communication path from a transmission source device (calling terminal) serving as a user cell transfer route to a destination device (destination terminal) via a switch (switch). A call (connection) is set, and cell transfer is controlled based on the connection identification information attached to the header part of each user cell.

  The call setup procedure is described in, for example, ITU-T standard Q.2931, and by executing the call setup procedure, connection information is transmitted to the source device, each node device (switch) on the route, and the destination device. Is set. The connection information includes an identifier for identifying a call on each link between the transmission source and the switch, between the switch and the switch, and between the switch and the reception destination, a traffic class indicating the priority of cell transfer within the switch, etc. Is included. The identifiers for identifying the connection (call) are called VPI (Virtual Pass Identifier) and VCI (Virtual Connection Identifier), and are set as address information in the header portion of each cell.

Each switch searches for connection information necessary for the switching process based on the VPI and VCI of each input cell received from the transmission path. The connection information includes, for example, internal routing information (output port number), an identifier to be assigned to an output cell (output VPI / VCI), a traffic class indicating cell priority in the switch, and the like.
Regarding traffic classes indicating cell priority, for example, `` Multimedia Traffic Management Principles for Guaranteed ATM Network Performance '' IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS VOL.8, NO 3 APRIL 1990 p437-446, and `` Traffic Management for B -ISDN Services ", described in IEEE Network, September 1992, p10-19.

There are two traffic classes indicating cell priority, namely, CBR (Constant Bit Rate) and VBR (Variable Bit Rate). CBR is a traffic class in which a predetermined cell transfer rate is contracted between a network and a terminal at the time of call setup, and the network side guarantees cell transfer at the above-mentioned transfer rate. This is a traffic class that allows a certain degree of statistical fluctuation to occur for the contracted transfer rate. A method of performing traffic control by making a contract in advance between a network and a terminal in this way is called “Preventive Control”.
As a traffic to be transmitted using the remaining bandwidth allocated to other terminals in the above-mentioned CBR and VBR without making a special contract regarding the transfer rate between the network and the terminal at the time of call setting, “Best Effor Control There is a traffic class group called. One reason for not making a transfer rate contract is that it is difficult for a terminal that outputs burst traffic to predict traffic characteristics at the time of call setup.
These Best Effor Control traffic groups include UBR (Unspecified Bit Rate) traffic class that the network does not guarantee any cell transfer, and cell loss by performing feedback control during congestion between the network and the terminal. There is an ABR (Available Bit Rate) traffic class that guarantees that no occurrence of the error occurs. The ABR traffic class is described in, for example, “The Rate-Based Flow Control Framework for the Available Bit Rate ATM Service” IEEE Network March / April 1995, p25-39.

  Regarding the configuration of a switch that performs transfer control according to the traffic class, for example, in Japanese Patent Laid-Open No. 6-197128 (prior art 1), two output buffers for CBR and VBR are provided for each output port, The table information indicating the empty / blocked state of the two buffers is stored corresponding to the output port, and by referring to this table information, the input buffer control unit determines the buffer for storing the cell addressed to each output port. A packet switch designed to do this is described. In this case, by setting the output priority of the cells stored in the CBR buffer to be higher than the cell output of the VBR buffer, the communication delay time in the switch for the CBR traffic cell group having severe restrictions on the communication delay. Can be kept within a certain value.

  Also, for example, when there is no space in the CBR buffer, if there is space in the VBR buffer, cells are stored in the VBR buffer, so that the bandwidth can be effectively used in the switch. When supporting ABR and UBR traffic classes, an output buffer corresponding to another traffic class may be added in addition to the CBR and VBR traffic classes.

In the 1996 B-598 “Development of a 622Mbps 8 × 8 ATM Switch LSI with 5 Class Delay Priority Control Function” (Prior Art 2), the same information was applied to each CBR and VBR traffic class. Shows a technique for storing cell number counter information for each connection in the traffic class and threshold information for each connection in the switch and discarding the cell when the value of the cell number counter exceeds the threshold value. .
In addition, for example, the B-765 “Electronic Information Communication Society Annual Conference B-765“ Selective Cell Discarding by Counter Control ”” (Prior Art 3) includes a delimiter of upper protocol packets (information units handled by upper protocols consisting of multiple cells). A technique called packet level discard is described in which selective and continuous discard of cells in units of packets when congestion occurs.
As a configuration of a switching system that handles ATM cells, for example, in Japanese Patent Laid-Open No. 4-276743 (prior art 4), instead of providing a physically independent buffer for each output port, a plurality of output ports can be provided. A configuration in which a common cell storage buffer is provided is shown.

`` The Rate-Based Flow Control Framework for the Available Bit Rate ATM Service '' IEEE Network March / April 1995, p25-39

  As described above, several traffic classes have already been proposed for asynchronous communication. In addition to using these traffic classes separately, cell forwarding is controlled in a form that further subdivides the characteristics within each traffic class. It is desirable to do. However, conventionally, for traffic classes that do not give a special guarantee for cell transfer, such as UBR, there is no means for controlling the quality of communications belonging to these traffic classes when the network is congested. It was. In the prior art 2, a technique for determining whether or not to discard a cell based on a threshold value for each connection more finely in the same traffic class is shown, but when the cell buffer is simply divided by the threshold value Even when the cell buffer is not yet congested, cells exceeding the threshold value are discarded, and there is a problem that the use efficiency of the entire cell buffer is lowered.

The object of the present invention is to make it possible to control communication quality without degrading the use efficiency of the entire cell buffer for the Best Effor Control traffic class group that does not contract the transfer rate between the network and the terminal at the time of call setup. An object of the present invention is to provide a packet processing apparatus and a cell transfer control method.
Another object of the present invention is to provide a node device such as an ATM switch capable of performing selective cell discard control when congestion occurs in a traffic class group in which bandwidth reservation from a terminal device is difficult at the time of call setup, and an ATM cell transfer control method Is to provide.

  In order to achieve the above object, in the cell transfer control method of the present invention, at the time of setting a connection belonging to a specific traffic class that does not reserve a bandwidth, any one of the node devices in the ATM (Asynchronous Transfer Mode) network Corresponding to the identifier of the connection, information indicating the priority for cell discard reported from the originating device or network management device is stored, and congestion occurs on the route of the connection, and the cells waiting for output in the node The node device selects a cell belonging to the specific traffic class according to a predetermined discard condition determined by the relationship between the state of the cell buffer and the priority. It is characterized in that a disposal process is performed.

More specifically, for example, the node device constantly updates and maintains a counter value for each connection in which the number of cells remaining in the cell buffer is counted for each connection, and the priority and the counter value for each connection. Whether to discard each cell belonging to the specific traffic class is determined according to a predetermined discard condition determined by the above. Further, the node device constantly updates and maintains a cell buffer counter value obtained by counting the total number of cells staying in the cell buffer, and determines the congestion of the entire cell buffer, the cell buffer threshold value and the total number of cells. In accordance with the relationship, the predetermined discard condition is weighted only when the cell buffer is congested, and the discard process is selectively performed on the cells belonging to the specific traffic class according to the discard condition to which the weight is added. In this case, for each cell of the specific traffic class, whether the data block included in the data portion of the cell is divided from the same transmission message as the data portion of the preceding cell or from a new transmission message It is preferable to perform discard processing in units of transmission messages for cells that meet the discard conditions.
For example, cell discard in units of messages starts a discard process for a cell that matches a predetermined discard condition determined by the relationship between the congestion state and the priority, and even if the cell is out of the discard condition due to a change in the congestion state, For subsequent cells including a part of the same transmission message as the data portion of the already discarded cell, the discarding process is continued. As a modification of cell discard on a message basis, for example, among cells that meet the discard condition, a cell including the data block of the same transmission message as the data part of the already transmitted cell is excluded from the discard target, and the subsequent new message The discarding process may be started from the cell including the head data block.

  Further, the present invention provides a packet switch that is connected to a plurality of input lines and a plurality of output lines and transfers a fixed-length packet (cell) input from each input line to any output line determined by cell header information. When storing a connection belonging to a specific traffic class that does not reserve a bandwidth, in order to store subclass information indicating the priority regarding cell discard reported from the calling device or the network management device in correspondence with the identifier of the connection. Means for detecting a congestion state corresponding to each output port, and for a cell belonging to the specific traffic class inputted from each input port, the congestion state at the output port serving as a transfer destination and the subclass Means for selectively performing disposal processing in accordance with predetermined disposal conditions determined by the relationship with information And it said that there were pictures.

More specifically, the packet switch of the present invention has a plurality of input ports and a plurality of output ports, and a fixed-length packet (cell) input from each input port is set to any output port determined by cell header information. Switch means for forwarding, input line interface connected between each input port and input line, output line interface connected between each output port and output line, and said switch means and each input line interface A call control device for transmitting / receiving a call control cell to / from the switch means and transmitting control information including header rewriting information to each input interface, and for each output port and each output cell for each connection. Congestion monitoring means that detects congestion status and notifies each input interface as congestion status information Now,
When the call control device sets a connection belonging to a specific traffic class that does not reserve a bandwidth, the connection identification information for the input interface that accommodates the calling device that has made the connection setting request source. And means for notifying the control information including the traffic class information declared by the control message from the calling device and the subclass information indicating the priority for cell discard, and each input interface is configured to Concerning user cells belonging to the specific traffic class received from the input line, the congestion state at the transfer destination output port of the user cell determined from the congestion state information, the congestion state for each connection, and the cell notified from the call control device Determined by relationship to disposal priority Characterized by comprising a cell discard control means for selectively cell discard according constant disposal conditions.
Each of the input line interfaces includes, for example, header conversion means for rewriting header information of input cells from each input line, and input buffer means for temporarily storing the header-converted data. The discard control unit selectively stores the input cell of the specific traffic in the input buffer unit according to the discard condition.

The switch means includes output buffer means corresponding to each output port, and means for distributing each user cell header-converted by each input line interface to any output buffer means specified by the header information. Thus, the congestion monitoring means detects the congestion state of the output cell from the accumulation state of the user cell in each output buffer means.
The switch means may include a plurality of output buffer means for each output port, and one of the output buffer means may be assigned to a cell of a CBR traffic class with a guaranteed transfer rate. Good. The output buffer means in the switch means holds cells from a plurality of output ports in common, and the congestion monitoring means is also configured to monitor the free buffer capacity of the output buffer means corresponding to the plurality of output ports. May be. When the output buffer means in the switch means is configured in common, the cell discard control means and the input buffer means may be arranged in the switch means instead of the input line interfaces.

  According to the configuration of the present invention, priority information related to cell discard is defined as a subclass for a traffic class that does not reserve a bandwidth, such as the Best Effor Control traffic class group described above, and at the time of call setup, However, when the above priority is notified to the network and congestion occurs in the Best Effor Control traffic class, the cell with the same traffic class has the lowest priority according to the priority information specified by the subclass. A connection cell that is discarded from a connection cell and has a high priority can be excluded from the discard target. In addition, when the degree of congestion progresses despite cell discard, cell discard occurs for the cell with the next highest priority connection, and discards in order from the cell with the highest priority connection as the congestion recovers. Processing is to be canceled. As a result, it is possible to guarantee the communication quality for connections with high priority among the Best Effor Control traffic class group.

  As is clear from the above description, according to the present invention, when congestion occurs, cells are discarded from connections with a low threshold by referring to threshold information for each connection set in advance, If the connection has the same threshold value, discard cells preferentially from connections with a large number of staying cells, and if threshold value is given priority, discard cells preferentially from cells with low priority connections. Therefore, the traffic of the high priority connection is protected.

As a first embodiment of the present invention, an ATM switch having a FIFO output buffer for each output port and performing cell transfer control using CBR as priority traffic will be described.
FIG. 1 shows the configuration of an ATM switch (switch) 100 according to the present invention connected to N input lines and N output lines.
Here, for convenience of explanation, the above exchange shows a network configuration in which A, B, and two terminal devices 162 and 164 are accommodated via input / output lines (subscriber lines). A part of the entry output line may be a trunk for connecting the exchange 100 to another exchange. In this example, the terminal A: 162 is arranged on the left side of the switch 100, and the transmission cell from the terminal is shown to be transferred to the terminal B: 164 arranged on the right side of the switch. In the exchange, the i-th input line and the i-th output line are paired with each other, and the output cell from the first output line in FIG. The cell is input to the Nth input line. The network management terminal 180 is a terminal for managing the network.

  The switch 100 is provided for a plurality of input line corresponding units (input line interfaces: LIFi) 102 (102-1 to 102-N) provided for each input line, a switch core unit 120, and each output line. A plurality of output line corresponding units (output line interface: LIfo) 108 (108-1 to 108-N) and a call control device (connection processing unit: CP) 140 are configured. Each input line corresponding unit 102 includes a header conversion circuit 132, a cell discard determination unit 136, and a cell buffer 134. The switch core unit 120 includes a crossbar switch circuit 105, a plurality of FIFOs 107 (107-1 to 107-N) prepared for output lines, and a FIFO congestion state determination circuit 106 connected to each of the FIFOs 107. It is configured.

FIG. 2A shows the format of the cell 210 that is input from each input line to the input line corresponding part of the switch 100.
A message (packet) transmitted from terminal A to terminal B is divided into a plurality of fixed-length data blocks, and a cell header is attached to each data block to form a cell 210. Each cell 210 is composed of a header part and a data part 212. In the header part, the input VCI 216 and the position of the data block included in the data part in the packet (transmission message) handled by the upper protocol are indicated. Information (PTY) 214 to be displayed. In the following description, the case where a cell includes the first data block of the upper packet is referred to as “packet delimiter”.

  When the input cell 210 is input from the input line, the header conversion circuit 132 reads the header conversion information corresponding to the input VCI 216 of the cell from the header conversion table, and converts it into the format of the internal cell 220 shown in FIG. Convert.

  The header portion of the internal cell 220 includes an output VCI 221 instead of the input VCI 216 of the input cell 210, routing information (output port information) 222, a traffic class 224, a subclass 225, and a VCI cell discard indicating a discard threshold for each connection. A threshold value 227 and packet discard state information 228 indicating whether or not the VCI packet is being discarded are added. If no congestion occurs in the corresponding output port, the internal cell 220 is sent to the switch core unit 120 without being discarded in the cell buffer 134, and is routed to the routing information (output port) via the crossbar switch circuit 105. Information) is sent to a specific output buffer FIFO 107.

FIG. 2C shows a control message (connection information) 230 for call setting sent from the calling terminal 162 to the switch 100 prior to communication with the called terminal 164.
The connection information 230 includes destination address information 232 for identifying a destination terminal, traffic class information 234, subclass information 236 indicating priority regarding cell discard, a VCI cell discard threshold 238 indicating a discard threshold for each connection, and a calling terminal. Terminal protocol information 250 indicating a higher-level protocol. The connection information 230 is divided into a plurality of fixed-length blocks at the calling terminal, and is supplied to the switch 100 as a control cell having the same format as in FIG. 2A obtained by adding a cell header to each block. It is sent.

The control cell is transferred from the switch core unit 120 to the call control device (connection processing unit: CP) 140 via signal processing means omitted in FIG. The signal processing means is for assembling the contents (data block) of the data portion 212 of each control cell into the original connection information (message format) shown in FIG. The connection interface with 120 may be configured as part of the call control device 140.
In the call setting sequence executed in response to the connection information, the call control device 140 sends the output VCI 226 assigned to the call to the conversion table unit (not shown) of the header conversion circuit 132 connected to the calling terminal. The output port information 226 specified from the destination address, the traffic class 234 and the traffic subclass 236 extracted from the connection information 230 are set. Similarly, in the connection setting sequence from the network management terminal 180, the call control device 140 is set in a conversion table section (not shown) of a predetermined header conversion circuit 132. When the call (connection) setting between the terminals is completed, the calling terminal 162 starts sending the cell (user cell) 210 to the called terminal 164.

FIG. 3 shows an example of the configuration of the FIFO output buffer 107.
The FIFO output buffer 107 includes two FIFOs 301 and 302 for CBR and UBR, a FIFO control circuit 109, a FIFO length counter 304, a counter control circuit 306 for each VCI, and a counter 308 for each VCI, and performs FIFO control. The circuit 109 preferentially outputs the storage cell of the CBR FIFO 301 over the storage cell of the UBR FIFO 302.
In a normal state where congestion does not occur, the user cells output from each FIFO output buffer 107i are input to the corresponding line output control unit LIFO 108i, and unnecessary internal header information 222 to 228 is removed here. And output to the output line in the output cell format composed of the information elements 212-221.

The information indicating the accumulation state of the cells in each FIFO output buffer 107i includes 2 of a FIFO length counter 304 indicating the number of staying cells in the FIFO output buffer 107i and a counter 308 for each VC indicating the number of staying cells for each connection (VCI). There is one.
First, the FIFO length counter 304 monitors the cell accumulation state in the two FIFOs 301 and 302 for CBR and UBR in the FIFO output buffer 107, and the cell accumulation state of all the FIFO output buffers 107 is determined via the signal line 156. Collected in circuit 106. The congestion state determination circuit 106 edits the cell accumulation state into congestion state information corresponding to the output port, and notifies each of the input line corresponding units 102-1 to 102-N via the signal line 152.

Here, the congestion state determination circuit 106 will be described.
The FIFO congestion state determination unit 106 shown in FIG. 5 includes a comparison unit for each output line, and includes a register 512 that holds FIFO length counter information, a register 510 that holds FIFO length threshold information, and a comparison circuit 514. In order to make a determination on a plurality of congestion levels, a plurality of registers 510 and comparison circuits 514 may be configured. The signal 156 from the FIFO length counter 304 collected in the FIFO congestion state determination means 106 is set in the register 512 and compared with the register 510 holding the FIFO length threshold information by the comparison circuit 514. The comparison result is sent to the line input control unit LIFi102-i via the signal line 152 and used as reference information for cell discard determination. For example, the congestion state determination circuit 106 classifies the cell accumulation state at each output port as a “subclass congestion state” and edits it as the congestion state information.

  Next, the VCI-specific counter 308 cooperates with the VCI-specific counter control circuit 306 to hold the current value of the number of cells for each VCI of the cells in the FIFO circuit 302. First, when a cell is input to the FIFO circuit 302, the number of cells of the corresponding VCI is counted up based on the output VCI 226 information of the internal cell format 220 sent from the crossbar switch circuit 105 to the FIFO circuit 302. Conversely, at the time of output from the FIFO circuit 302, the number of cells of the corresponding VCI is counted down based on the output VCI 226 information. As a result, the current value of the number of cells for each VCI is held. When a read request instruction from the line input control unit LIFi102 arrives via the signal line 322, the current value of the number of cells for each VCI held in the VCI-specific counter 308 is read, and line input control is performed via the signal line 324. To the cell discard determination circuit 430 in the unit LIFi102.

  FIG. 4 is a configuration diagram of the line input control unit LIFi102-i. The line input control unit LIFi102-i includes a header conversion circuit 132, a cell discard determination unit 136, and a cell buffer 134 as cell discard means. The cell discard determination unit 136 includes a packet delimiter recognition circuit 420, a FIFO congestion level determination circuit 430, a VCI congestion level determination circuit 440, and a packet discard determination circuit 410.

The packet delimiter recognition circuit 420 receives the PTY 214 in the internal cell format 2202 and the packet discarding state 226 from the header conversion unit 132, detects the packet delimiter, and determines the packet discard via the signal line 422 together with the packet discarding state. Output to the circuit 410.
The FIFO congestion level determination circuit 430 receives the traffic subclass 225 from the header conversion unit 132 and the congestion information 152 from the FIFO congestion state determination circuit 106, and determines the active traffic subclass state according to the flow described in the explanation part of FIG. It is obtained for each output line, held in the register 432, and the comparison result with the traffic subclass of the received cell is output to the packet discard determination circuit 410 via the signal line 442.
The VCI congestion level determination circuit 440 receives the VCI cell discard threshold value 227 from the header conversion unit 132, the congestion information 152 from the FIFO congestion state determination circuit 106, and the VCI-specific counter 308, and performs the discard determination in the light congestion state. 8 is performed, a light congestion discard instruction signal 442 is output to the packet discard determination circuit 410.
The packet discard determination circuit 410 receives the light congestion discard instruction signal 442 as a result of comparison between the packet delimiter signal from the signal line 422 and the packet discarding state, the traffic subclass of the received cell from the signal line 442, and FIG. The processing of the flow shown is performed, and an input cell discard instruction 154 is output to the cell buffer 134 which is a packet discard unit. When the cell buffer 134 receives the discard instruction 154, the cell buffer 134 does not transfer the cell to the switch core unit 120.

  FIG. 6 shows the state transition of the active traffic subclass state held in the register 432. The subclass congestion state has a state from N to 1, and when the signal 152 from the FIFO congestion state determination circuit indicates a heavy congestion state, the subclass congestion state transitions to a state of “+1” (for example, 612 to 610), When a light congestion state is indicated, the subclass congestion state transitions to a state of “−1” (for example, 610 to 612).

FIG. 7 shows the operation of the packet discard determination circuit 410.
In step 712, the upper packet level discard determination (step 730) shown in FIG. 8 is performed on the cell in which the subclass congestion state and the traffic subclass match, and if the condition is met, the upper packet level discard is performed. Cells with a traffic subclass larger than the subclass congestion state are not discarded (step 718), and cells with a traffic subclass smaller than the subclass congestion state are discarded (step 714).

In the upper packet level discard determination 730, as shown in FIG. 8, when the packet discarding state 226 received via the signal line 422 is cell discarding (step 732) and the PTY 214 is not a packet delimiter (step 734), A cell discard instruction is given to the cell buffer 134, and a packet discarding state lighting instruction is given to the header conversion circuit 132 (step 736). As a result, the packet discarding state of the corresponding VCI in the header conversion circuit 132 is turned on.
If the packet discarding state 226 received via the signal line 422 is not discarding a cell (step 732), or if the PTY 214 is a packet delimiter (step 734), the VCI cell is discarded at the level F of the light congestion state by the signal 152 A result S ′ obtained by dividing the threshold value S is obtained (step 738), and the value C of the output signal 324 of the VCI-specific counter 308 is compared with S ′ (step 740). Here, if F is a power of 2, the division can be performed by a shift operation, and the operation can be performed even within a fast switching time.

  If C> S 'as a result of step 7407, it is determined whether or not there is a break in the upper packet as in step 734 (step 472). If it is a break, a cell discard instruction is issued (step 736). As a result of step 740, if C> S 'is not satisfied, or it is determined whether or not the upper packet is interrupted in the same manner as in step 734 (step 742). . Here, Steps 738 and 740 explain the operation of the VCI congestion level judgment circuit 440, and the other steps explain the operation of the packet discard judgment circuit 410.

  FIG. 9 shows the function of steps 738 and 740. In the cell discard determination based on the relationship between the threshold for each connection: S and the number of cells for each connection: C, the number of cells being discarded increases as the congestion state progresses depending on the degree of the light congestion state of the FIFO. In addition, by setting the threshold value for each connection: S, fairness for each connection can be realized, and when a large threshold value: S is given for an important connection, the cell is compared with other connections. It can be set so that discarding is unlikely to occur.

According to the present invention, when a congestion state occurs in the entire output port in the switch, the cell is discarded based on the output of the connection comparison means. In the subclass shown in FIG. Cell is discarded. When the degree of congestion progresses despite cell discard, cell discard also starts from a connection with a large sub-level. As the switch recovers from the congestion state, cell discard is stopped in order from the cell with the connection with the large sub-level, and the cell with the connection with the large sub-level is protected against the congestion state generated in the switch.
In the above embodiment, the cell buffer is provided for the output port. However, the present invention can be applied to the case where the cell buffer is provided for the input port, or the buffer is provided for both input and output.

Next, as another embodiment of the present invention, an ATM switch sharing a cell buffer by a plurality of ports will be described.
In FIG. 10, reference numeral 110 denotes a common buffer switch unit which is a main part of the ATM switch. This switch unit 110 replaces the switch core unit 120 of the switch 100 shown in FIG. 1, and replaces the cell discard determination unit 136 that is distributed and arranged in each input line corresponding unit 102 in FIG. A common cell discard determination unit 137 is provided in the line corresponding unit.
The switch core unit 1 includes, for example, a 155 Mbps / 600 Mbps multiplexer 12 connected to the input lines L10 to L13, a 600 Mbps / 155 Mbps separator 13 connected to the output lines L50 to L53, a common buffer memory 11, and a buffer And a memory control circuit 10. The input line corresponding unit 120 shown in FIG. 1 is inserted in each of the input lines L10 to L13, but is omitted in this figure.

The buffer memory control circuit 10 includes a write address memory 111, a read address memory 112, a free address buffer 113, a bandwidth control table 114, a counter 115, a common buffer memory congestion state determination circuit 106, a VCI-specific counter control circuit 306, and a VCI-specific counter. 308 and a cell discard determination unit 137.
The input cells subjected to header conversion by an input line corresponding unit (not shown) are input from the input lines L10 to L13 to the multiplexer 12 and output from the line L2 as a time-series cell string. The basic configuration and operation of the switch core unit 120 shown here are the same as those described in Japanese Patent Application Laid-Open No. 4-276743, and the buffer memory control circuit performs cell writing and reading to the common buffer memory 11. 10 to control.

In the cell write cycle, output port information (routing information) attached to the header portion is extracted from each cell output from the multiplexer 12 to the line L2, and the write address memory 111 is accessed by using this as an address. The issued address is given as the write address WA to the common buffer memory 11 via the line L32. At this time, an empty address used as a pointer address to the next cell is taken out from the empty address buffer 103 in which the empty address of the common buffer memory 11 is accumulated, and the write address memory 111 and the common buffer memory are obtained via the line L31. 11 is given as input data.
The pointer address is written in the same memory area in the write address memory 111 instead of the current write address WA, and when the next cell addressed to the same port arrives, a new write address WA to the common buffer memory 11 is written. It becomes. On the other hand, a pointer address written to the common buffer memory 11 as a pair with an input cell is read from the common buffer memory 11 as a pair with a cell in a cell read cycle to be described later, and held in the read address register 112. . As a result, each time a cell is read, a pointer address indicating a cell to be read next time is stored in the read address register 112 in correspondence with the output port, and in the common buffer memory 11 in correspondence with each output port, A queue chain (list structure) logically connected by the next address is formed.

In a cell read cycle alternately performed with a cell write cycle, the band control table 114 is accessed using the output value (count value) of the counter 115 that performs a count-up operation for each cell read cycle as an address. The count value corresponds to the output port of the cell selected by the separator 13, and the bandwidth control table 114 has an address for designating a specific queue chain from which the cell is to be read in advance corresponding to the count value. I remember it.
The queue address read from the bandwidth control table 114 is given to the read address memory 112 as a read address (RA) and a write address (WA), and from the address memory 112, the first cell of the specific queue chain is assigned. The pointer address pointed to is read. The pointer address is given as a read address to the common buffer memory 11 via the line L33, whereby the head cell of a specific queue chain is read. Since the pointer address becomes an empty address after reading of the cell from the common buffer memory, it is stored in the empty address buffer 1113 via the line L33. At this time, the next pointer address is read from the common buffer memory 11 in a pair with the cell, and this pointer address is written to the read address memory 112 as a new pointer address.
As a result of the above-described operation, a new cell is added to the tail of any queue chain in each write cycle in the common buffer memory 112, and any queue chain in each read cycle unless the designated queue chain is empty. The first cell is removed.

  The common buffer memory congestion state determination circuit 106 has a function similar to that of the FIFO congestion state determination circuit 106 of the switch core unit shown in FIG. 1, and calculates the buffer usage amount for each port from the FIFO length counter 309 via the line L52. The congestion state is output to the line L45. In the FIFO congestion state determination circuit 106 of FIG. 1, the capacity of the FIFO 302 is the maximum value of the FIFO length counter 304, whereas in the case of the FIFO length counter 309, the FIFO corresponding to the buffer usage for each port. As the set value of the long threshold register 510, a value larger than the value obtained by dividing the capacity of the entire common buffer memory 11 by the number of ports can be set, which has an advantage of improving the buffer utilization rate when congestion occurs.

The VCI counter control circuit 306 counts up the cell count value in the VCI counter 308 corresponding to the VCI information input from the line L42 in the cell write cycle to the common buffer 11, and conversely, In the cell read cycle, the cell count value in the VCI-specific counter 308 corresponding to the VCI information input from the line L41 is counted down.
When the VCI information of the cell being multiplexed by the multiplexer 12 is input from the line L43, the VCI-specific counter 308 outputs a cell count value corresponding thereto to the line L44.
In the cell write cycle to the common buffer 11, the FIFO length counter control circuit 307 counts up the cell count value for each port in the FIFO length counter 309 corresponding to the port information input from the line L42, and conversely, In the cell read cycle from the buffer, the cell count value for each port in the FIFO length counter 309 corresponding to the port information input from the line L41 is counted down. The cell count value for each port, that is, the FIFO length value is transferred to the common buffer memory congestion state determination circuit 106 via the line L52.

  The cell discard determination unit 137 has a configuration similar to that of the cell discard determination unit 136 shown in FIG. 1, and from the line L43, the PTY 214, output VCI 226, output port 221 and traffic class of the cell being multiplexed by the multiplexer 12 222, traffic subclass 225, cell discard threshold 227, and packet discarding information 228 are received, congestion state information of the common buffer memory is received from line L45, and the output of the cell being multiplexed by multiplexer 12 is received from line L44. The VCI 226 is received, and the cell count value corresponding to the output VCI 226 is received from the VCI-specific counter 308. The line L45 is a signal line corresponding to the line 152 in FIG. Unlike the cell discard determination unit 136 shown in FIG. 4, the cell discard determination unit 137 receives the empty address amount (free buffer capacity) of the entire common buffer memory 11 from the empty address buffer 103 via the line L51. When it disappears, the multiplexer 12 discards the cell being multiplexed unconditionally.

As described above, the N × N cell switch has been described as an example of the embodiment of the present invention. However, the cell discard control according to the present invention is, for example, an N-input 1-output multiplexer or a 1-input 1-output multiplexer. The present invention can also be applied to other communication devices such as a speed conversion buffer.
In the embodiment, the mode of recognizing the delimiter of the upper protocol packet and discarding the cell in units of packets has been described. However, when congestion occurs, cell discard is immediately started without waiting for the delimiter of the upper protocol packet. A packet in which a cell is lost may be in a discard mode in which discarding is continued up to a packet-delimited cell. Further, these discard modes may be selectively switched according to the congestion state, or cell discard may be performed without recognizing the upper protocol packet.

The block diagram which shows one Example of the packet switch to which this invention is applied. The figure which shows an example of an input cell, an internal cell, and a control message format. The block diagram which shows one Example of the output FIFO 107 in FIG. The block diagram which shows one Example of the cell discard determination unit 136 in FIG. The block diagram which shows one Example of the FIFO congestion state determination circuit 106 in FIG. FIG. 5 is a state transition diagram showing the function of the FIFO congestion level determination circuit 430 shown in FIG. 4. 5 is a flowchart showing functions of the packet discard determination circuit 410 shown in FIG. The flowchart which shows the detail of the high-order packet level discard determination process 730 in FIG. The graph showing the function of the VCI congestion level determination circuit 440 in FIG. The block diagram which shows the other Example of the packet switch to which this invention is applied.

Explanation of symbols

100: Switch, 102: Input line corresponding part, 106: Congestion state judgment circuit,
107: FIFO output buffer, 108: Output line compatible part, 132: Header converter,
136: Cell discard determination unit, 140: Connection processing unit.

Claims (2)

Is connected to the one or more input lines and one or more output lines, the data constituting the packet that is input from the input line, one of the output lines determined in accordance with the header information of data constituting the packet A packet switch that outputs to
A first buffer that temporarily holds data constituting a packet for which a use band is not reserved in advance for each output line that outputs the data ;
A second buffer that temporarily holds data that constitutes a packet whose bandwidth is reserved in advance, for each output line that outputs the data;
First counter means for counting the number of data constituting the packet held in the first buffer;
Congestion state determination means for determining the congestion state of data constituting the packet held in the first buffer for each priority determined for each destination of the data ;
The number of data constituting the packet counted by the first counter means, the packet configuration data discard threshold information that is changed according to the congestion state determined by the congestion state determination means, and the reserved use band are reserved in advance. Packet configuration data discard determining means for determining whether or not to discard the data that constitutes a packet that has not been reserved for the band in advance according to the priority of the data that constitutes a non- packet switch. The packet switch according to claim 1, wherein
The packet switching data discard threshold information is an upper limit value of the number of staying packet configuration data in the first buffer for each destination of a packet whose bandwidth is not reserved in advance .

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