JP2682434B2 - Output buffer type ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch for exchanging information divided into fixed-length cell units in an asynchronous transfer mode, and more particularly to a structure of an ATM switch having a traffic control function.

[0002]

2. Description of the Related Art An ATM switch, which divides information into fixed-length cell units and exchanges them in an asynchronous transfer mode, is regarded as a promising switch for the next-generation broadband communication. The ATM switch switches cells for each cell based on the identifier written in the header area of each cell. FIG. 3 shows an example of the configuration of an output buffer type ATM switch which is the basis of the present invention. In the figure, 2-1 is the internal bus of the ATM cell switch, 2
-2 ₁ ~2-2 _n input ports, 2-3 ₁ ~2-3 _n output ports, 2-4 ₁ ~2-4 _n transmission circuit to the internal bus, 2-5 ₁ ～2-5 _n is a receiving circuit from the internal bus, 2
-6 _{1 to} 2-6 _n are output buffers, and 2-7 is a switch controller.

Generally, in the output buffer type ATM switch, the throughput of the internal bus 2-1 is larger than the total throughput of the input ports. Here each input port 2
-2 ₁ ~2-2 _n and the output ports 2-3 ₁ ~2-3 _n
If all line speeds are set to Mbps, internal bus 2-1
Has a throughput of n × Mbps or more. Therefore, from the perspective of each input port, even if cells arrive consecutively,
Since one cell can be sent to the internal bus without fail during the time when one cell arrives at the port, it is sufficient to prepare a buffer for several cells on the input port side for timing adjustment. That is, no cell is discarded on the input port side. Cells inputted from the input port 2-4 ₁ ~2-4 _n is transmitted to the internal bus 2-1 via the transmitting circuit 2-4 ₁ ~2-4 _n. The transmission right from each port to the internal bus 2-1 is controlled by the switch control unit 2-7. Specifically, a method of cyclically giving transmission rights to each port in a time division manner may be used. The transmission circuits 2-4 _{1 to} 2-4 _n of the respective ports use buffers for several cells inside and transmit cells to the internal bus 2-1 according to the transmission right signal of the switch control unit 2-7. With respect to the cells multiplexed on the bus, the port destination information in the header section is checked by the receiving circuits 2-5 _{1 to} 2-5 _n of the respective ports, only the cells addressed to this port are selected, and the output buffer 2-6 ₁ ~ 2-6 _n .

Generally, on the receiving side, cells received in the output buffer may be sent to the outgoing line in the order in which they are received. However, on the output port side, cells may be discarded due to congestion, and the output buffer filtering function is required. Becomes
In addition, a filtering function of the output buffer is required to identify the destination address of the LAN.

Filtering for congestion control of the output buffer is performed, for example, when cells addressed to a particular output port arrive from a plurality of input ports at the same time, a plurality of cells arrive at a particular output port within one cell time. Therefore, only one cell is output within one cell time, more cells enter, and cells accumulate in the buffer until the buffer overflows and the cells are discarded. As one countermeasure against such a buffer overflow, there is a discard process according to the priority level of the cell. This is a method of actively discarding cells with low priority when the remaining capacity of the output buffer becomes a certain amount or less, and preventing discarding of cells with high priority. In this case, the receiving circuit checks the priority level written in the cell header and discards the low priority cell. Japanese Patent Application No. 3-150123 shows a configuration example in which such control is performed, but in this configuration, the output buffer must be filtered at the switch speed.

In addition, packet data on the LAN is transferred to ATM.
In the case of forwarding with, the filtering for identifying the destination address of the LAN divides the packet used in the LAN and sends the ATM header with each divided. In this case, the address of the ATM header is used as the routing method. There is a method in which a broadcast display is made to be temporarily received by all ports, then the destination address of the packet is checked by each receiving circuit, and the packet other than its own port is discarded at each port. Even in this configuration, filtering must be done at switch speed.

[0007]

When the above-described filtering process is performed by the receiving circuit of the conventional switch, the process must be performed at the speed of the internal bus because it is performed before it is put into the output buffer. As mentioned above, the speed of the internal bus is more than the number of lines of each line speed,
For example, in a 16 × 16 switch at each line speed of 600 Mbps, cells input at a speed of 9.6 Gbps must be filtered. The object of the present invention is to provide two buffers on each output port side of the ATM switch.
In the stepwise configuration, the first output buffer once receives all the cells addressed to the output port to absorb the switch speed, and then the filtering required when transferring from the first output buffer to the second output buffer. It is an object of the present invention to provide an ATM switch capable of performing filtering processing at a speed lower than the switching speed by performing processing such as the above.

[0008]

The output buffer type ATM switch of the present invention is used in an ATM switching system.
In an output buffer type ATM switch having a cell switch, a first output buffer corresponding to each output port, and a switch control unit, a cell switch is provided for each output buffer corresponding to each output port, and cells are output from the first output buffer. The second output buffer that reads at a bit rate higher than the line speed of the outgoing line and extracts and stores only the cells that should be output to that line.
Output traffic control means including a buffer .

Furthermore, the output traffic control means, the
A read control circuit for reading at a line speed more than the bit rate of the line out of the cell from the first output buffer, and filtering circuit for extracting cells only to be output by the line speed to the outgoing line from the header of a cell out read A second for accumulating cells extracted by the filtering circuit
And the output buffer of.

Further, the filtering circuit has means for detecting the priority level of the cell and means for detecting the remaining capacity of the second output buffer.

Furthermore, the second output buffer has a plurality of second output buffers for accumulating cells corresponding to the priority level.

[0012]

According to the present invention, the output buffer on each output port side of the ATM switch has a two-stage configuration, and the first output buffer once receives all the cells addressed to the output port to absorb the switch speed, Since the processing such as filtering required when the data is transferred from the first output buffer to the second output buffer after that is performed at a speed lower than the switch speed, the filtering processing can be performed at a speed slower than the switch speed.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of an output buffer type ATM switch of the present invention, and FIG. 2 is an operation explanatory diagram of an embodiment of an output traffic control unit of the present invention. Output buffer type A of the present invention
Similar to FIG. 3, the TM switch has an internal bus 1-1, input ports 1-2 _{1 to} 1-2 _n , and output ports 1-3 _{1 to} 1-3.
_n , transmitting circuit 1-4 _{1 to} 1-4 _n , receiving circuit 1-5 ₁ to
1-5 _n, the output buffer 1-6 ₁ ~1-6 _n, output traffic control unit of the switch control unit 1-7 and the present invention 1-
8 _{1 to} 1-8 _n , and the output traffic control unit further includes a read control circuit 1-9 _{1 to} 1-9 _n , a filtering circuit 1-10 _{1 to} 1-10 _n, and a second output buffer 1-11. _It consists of _{1 to} 1-11 _n .

Receiving circuits 1-5 ₁ to ₁ corresponding to each output port
-5 _n, among the cells flowing over internal bus 1-1, header
Port destination information parts is checked, and received by selecting only the cells destined to the own output port, the output buffer 1-6 ₁ to 1
Store once at -6 _n . Output buffer 1-6 _{1 to} 1-6 _n
The cells once stored in the read control circuit 1-9 ₁ to 1
By -9 _n , the signal is input to the filtering circuits 1-10 _{1 to} 1-10 _n at a speed several times higher than the line speed.

Here, the reason why the line speed is read at a speed several times higher than the line speed is to absorb fluctuations in cell arrival and to absorb surplus due to broadcasting of LAN packets. Assuming that the above is performed in advance, a speed of about 2 to 3 times the line speed is sufficient. That is, the processing speed which is several times as fast as the line speed is necessary because the maximum line speed can be maintained except the cells discarded by the filtering.

Filtering circuit 1-10 _{1 to} 1-10
_n is the LA of the input cell header or cell contents
N destination address part, etc. are checked, cells are discarded as necessary, and cells not discarded are output to the second output buffer 1
Input in -11 _{1 to} 1-11 _n . The cells input to the second output buffers 1-11 _{1 to} 1-11 _n are output to the output ports 1-3 _{1 to} 1-3 _n at the line speed.

Next, the operation of the output traffic control unit having a plurality of second output buffers will be described with reference to FIG. A priority level detecting means (not shown) in the filtering circuit transfers cells to a corresponding second output buffer (hereinafter referred to as a buffer) for each priority level according to the priority level written in the header of the input cell. . At this time, each priority level buffer is provided with buffer remaining capacity detecting means (not shown), and the remaining capacity signal of each detected buffer is notified to the filtering circuit by the remaining capacity signal. The filtering circuit knows the usage of the buffer from the remaining capacity signal notified from each buffer. For example, if the level of the cell to be transferred to the priority level buffer next from the filtering circuit is 2 and the remaining capacity of the level 2 buffer is constant. If it is smaller than the amount, the cell to be transferred is discarded. If the level of the cell to be transferred next to the priority level buffer from the filtering circuit is 1, and the remaining capacity of the level 1 buffer is smaller than a certain amount, the remaining capacity of the level 1 buffer is set to the certain amount. The reading circuit stops reading the next cell from the switch due to the back pressure signal while stopping the filtering circuit until the above. The cells stored in the priority level buffers are read according to the priority level and output to the output port. For example, various types of filtering control such as reading only from the level 1 buffer until the remaining capacity of the level 2 buffer is below a specified amount, and alternately reading when the remaining capacity of the level 2 buffer exceeds a specified amount Corresponding to.

[0018]

According to the present invention, once the first switch speed
After being absorbed by the first output buffer, the cell can be processed while being transferred to the second output buffer at the line speed, so it is possible to perform discard processing for each of multiple priority levels according to the congestion state or write inside the cell header. It is possible to perform a wide variety of processing such as filtering using the destination address of the LAN at a low speed processing of about several times the line speed by using a switching element that has a large number of records and is stable.

For example, 16 × 1 at a line speed of 600 Mbps
In the case of the switch of No. 6, the processing of the bit stream of 9.6 Gbps is required in the conventional configuration, whereas the processing of the present invention may be performed at a speed several times higher than the line speed of 600 Mbps.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of an output buffer type ATM switch of the present invention.

FIG. 2 is an operation explanatory diagram of an embodiment of an output traffic control unit of the present invention.

FIG. 3 is a configuration diagram of a conventional output buffer type ATM switch.

[Explanation of symbols]

1-1 Internal Bus 1-2 _{1 to} 1-2 _n Input Port 1-3 _{1 to} 1-3 _n Output Port 1-4 _{1 to} 1-4 _n Transmission Circuit 1-5 _{1 to} 1-5 _n Reception Circuit 1 -6 _{1 to} 1-6 _n output buffer 1-7 switch control unit 1-8 _{1 to} 1-8 _n output traffic control unit 1-9 _{1 to} 1-9 _n read control circuit 1-10 _{1 to} 1-10 _n Filtering circuit 1-11 _{1 to} 1-11 _n Second output buffer

Claims (4)

(57) [Claims] 1. An ATM cell switch in an ATM switching system, a first output buffer corresponding to each output port, and an output buffer type ATM switch having a switch controller, wherein each output buffer corresponding to each output port is provided. An output traffic control means including a second output buffer for reading cells from the first output buffer at a bit rate higher than the line speed of the output line and extracting and accumulating only cells to be output to the line. Output buffer type ATM switch characterized by: Wherein said output traffic control unit, the line and read control circuit for reading at a first line speed than the bit rate of the line out of the cell from the output buffer, from the header of a cell out read to the outgoing line speed
Second output buffer type ATM switch according to claim 1, wherein comprising the output buffer for storing a filtering circuit for extracting only the cells to be output, a cell extracted by the full Irutaringu circuit by. Wherein the filtering circuit, an output buffer type ATM switch according to claim 2 Symbol mounting having means for detecting a priority level of the cell Le, means for detecting a remaining capacity of the second output buffer. Wherein said second output buffer, an output buffer type ATM switch according to claim 1 having a plurality of second output buffer for storing cell corresponding to the priority level.