JP3197152B2 - Cell switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of information and communication in the field of personal computer and workstation data,
ATM (Asynchrono) for dividing various information such as telephone voice and multimedia image information into blocks called cells or packets for high-speed transmission and exchange.
us Transfer Mode, asynchronous transfer mode) The present invention relates to a cell or a packet switching device in communication or high-speed packet communication.
The present invention also relates to an apparatus for temporarily storing and exchanging data.

[0002]

[Prior art]

Conventional example 1. FIG. 35 shows, for example, the document International Confer
ence on Communications, 1987, Session 22, Paper No. 2, Jean-Pierre Coudreuse, Michel Servel, PR
ELUDE: An Asynchronous Time-Division Switched Netwo
The rk, ■ high-speed packet switch is shown in a slightly modified form for explanation. This document relates to a high-speed packet switch in an asynchronous transfer mode (ATM) communication system for efficiently multiplexing and transmitting circuit-switched data and packet-switched data.

In the ATM communication system, for example, continuous signals such as line signals and voices, and burst signals such as data and moving images are all divided into fixed lengths, and destination information and the like are indicated thereon. A header is added to create a packet, and information is transferred in the same format packet. This packet has been internationally standardized and is called a cell. Hereinafter, this packet is called a cell, but the meaning is the same. The terminal and the transmission path do not need to synchronize frames and the like, and the speed between the terminal and the transmission path may be independent, so that any terminal can be handled. However, since cells arrive at the high-speed cell switch at random, a large number of cells may flood at one destination at a certain moment, and it is necessary to wait for cells in order to prevent loss of information. Occurs.

[0004] To solve this problem, see, for example,
And Fig.6 proposes a high-speed cell switch.
FIG. 35 shows a block diagram of one example. 11. ₁ to 1 _n are n (n ≧ 2) input lines to which data is input, and cells arriving here are of fixed length. 2 _{1 to} 2 _m are m (m ≧ 2) outgoing lines from which cells are output. Reference numeral 7 denotes a cell multiplexing circuit that multiplexes input cells. Reference numeral 11 denotes a common buffer memory that can write data to a specified address and can read data regardless of the writing order by specifying the address. Reference numeral 8 denotes a cell separation circuit for separating the read cells. Reference numeral 15 denotes a control circuit for controlling cell exchange.

[0005] A plurality of input lines 11 to ₁ of this high-speed cell switch are provided.
The cells arriving at 1 _n are multiplexed by the cell multiplexing circuit 7,
The data is written to the common buffer memory 11. The header including the destination information of the arriving cell is sent to the buffer control circuit 15, the destination outgoing line 2 ₁ to 2 _m is determined. At the same time, address vacant in the shared buffer memory 11 is allocated, the address is a matrix to the destination outgoing line 2 ₁ to 2 _m corresponds. At this address in the common buffer memory 11, an arrival cell is written.

On the other hand, the buffer control circuit within 15, If there is a address the forefront of the destination output line 2 ₁ to 2 _m corresponds to made the address matrix, takes out the address. In accordance with the read address, reads a cell from the shared buffer memory 11, are separated by the cell separation circuit 8, the cell is outputted to a predetermined output line 2 ₁ to 2 _m. Above, by the operation of the cell switch, the cells on the input line 1 ₁ to 1 _n is outputted to the desired outgoing line 2 ₁ to 2 _m, the exchange of cells are realized.

Conventional example 2. FIG. 36 is a diagram showing the configuration of a conventional ATM switch capable of efficiently expanding the buffer capacity of a multimedia service. The ATM switch shown in FIG. 36 is described in the IEICE Technical Report (IEICE Technical Report V).
ol. 93 No. 11, SSE93-1-6) 199
FIG. 23 is a configuration diagram of an ATM switch shown in “ATM switch capable of expanding buffer capacity: XATOM” published on April 23, 3rd, p31-p36. In this configuration,
By combining the advantages of the input buffer method and the output buffer method, accumulating cells in a large-capacity low-speed buffer, and using a small amount of output buffer, scheduling is performed independently and at low speed at each input port. In this system, when the output buffer has more than the number of input lines (n) cells, the output buffer is notified that the cells can be accepted so that the input buffer can operate independently. In FIG. 36,
1 ₁ and 1 _n are incoming lines and 2 ₁ and 2 _n are outgoing lines. 900 ₁
To 900 _n are input control units, 901 _{1 to} 901 _n
Is an input buffer, 910 _{1 to} 910 _n are output control units, 911 _{1 to} 911 _n are output buffers, and 920 is a time division bus.

[0008] Figure 37 is a diagram showing the configuration of input control unit 900 _1. The input control unit 901 is a memory 9 that manages cells by destination of the cells and in the order of arrival.
And a 30 ₁ ~930 _n. The destination of the packet arriving at the input control unit is detected, and the corresponding memory 930 is detected.
_{1 to} 930 _n .

Next, the operation will be described with reference to FIGS. 36 and 37. If each of the output buffers 911 _{1 to} 911 _n is not in a congestion state, the input control unit continues to output cells arriving from the input line from the input buffer. If the number of accumulated cells in the output buffer 911 ₁ is increased, the output buffer 911 ₁ becomes congested, the input control unit 900 ₁ to 900 _n
Controls the cell accumulation to the input buffers 901 _{1 to} 901 _n so as not to output the cells addressed to the output buffer 911 ₁ . Therefore, the input buffer 90
From 1 ₁ ～901 _n, the cell is not outputted to the output buffer 911 _1, the output buffer 911 ₁ during this time,
Congestion can be eliminated.

Conventional example 3. For example, FIG. 38 shows EUROPEAN PATEN
T APPLICATION Application number: 92104389.9 Publ
FIG. 21 is a block diagram illustrating a transmission channel switching method and a switching device for transmitting the multiplexed cell described in ication number: 00503663A1. In FIG. 38, 1001a is c
A working multiplexer (hereinafter referred to as MUX) having N input lines h1 to chN, and 1001b is also a protection MUX.
It is. The cells input to the MUXs 1001a and 1001b connect the transmission lines 1003a and 1003b to the cells 1002a and 1003b.
02b. The cell order for any of the N input lines is determined by the transmission line 1003.
a and 1003b. For example, in ch1, cells 1, 4, and 6 are input to the working MUX and the protection MUX in this order.
a and 1003b. However, in different input lines, for example, cell 1 of ch1 and ch1
The order of the active transmission line 1001a and that of the standby transmission line 1001b are different, as in cell 2 of FIG. This is because even if the protection MUX operates in the same state as the working MUX, a difference occurs in the processing order when cells are filled between input lines due to a delay time difference due to the line length of the cable. .

Whether intentional or unintentional, cells having user information are interrupted, and there are empty cells indicated by E in FIG. 38 that do not have user information. An empty cell detector (EMPTY CELL DETECT) 1004 detects an empty cell. The timing determination unit (TIMINGDETERMINE) uses the empty cell detected by the empty cell detection unit as a trigger to transmit the transmission line 1003.
a and 1003b The switching timing is determined. At this switching timing, the selector (SEL) 1006 switches the active transmission line 1003a to the standby transmission line 1003b. Then, a series of cells multiplexed from the N input lines are output without interruption.

Conventional Example 4. FIG. 39 shows Endo et al., "ATM
39 is an example of a common buffer type ATM switch described in the IEICE Autumn National Convention SB-4-3, 1988. In FIG.
01 is an input port, 2002 is an output port, 2003 is serial / parallel conversion (S / P) and time division multiplexing (MUX),
004 is a header conversion table (HD CNV), 200
5 is an address filter (AD FLT), 2006 is a buffer memory (BFM), 2007 is a write address register (WA), 2008 is a read address register (RA), and 2009 is an empty address buffer (IA).
BF) and 2010 are output control counters (OUT CN
T) and 2011 are output decoders (OUT DE
C) and 2012 are parallel / serial conversion (P / S) and demultiplexer (DMUX).

The cell input from the input port 2001 is written in the write address register 2 together with the write address of the next cell read from the empty address buffer 2009.
007 is written to the address of the buffer memory 2006. Next, the write address of the next cell is written to the write address register 2007. If there is no free address in the free address buffer 2009, the input cell is discarded. Output control counter 2
Read address register 2008 designated by 010
Is read out from the buffer memory 2006 and sent to the corresponding port. The read address of the next cell read at the same time is read address register 2
008 is set.

Conventional Example 5 FIG. 40 shows Japanese Patent Application No. Hei 3-30047.
FIG. 7 is a block diagram showing a configuration of the conventional cell switching device shown in FIG. In FIG. 40, a cell 3011 including a header portion and a data portion including an output line number as input destination information is input, and output to a predetermined output line based on the destination information.
The cell switch to be replaced. A cell switch 3012 receives the same cell from the same input line and has the same configuration as the cell switch 3011. One operates as an active system and the other operates as a standby system. 3002a-3
002n denotes n (n ≧ 2) input lines for inputting cells to the cell switches 3011 and 3012 in the same manner. 30
03a to 3003m and 3004a to 3004m
M (m ≧ 2) output lines from which cells exchanged by the cell switches 3011 and 3012 are output.

Reference numerals 3005a to 3005m denote cell switches 3
A selector for selecting one of the outputs 011 and 3012 and switching between the active system and the standby system. 3006a-3
006m outputs the cell selected by the selector m (m
≧ 2) outgoing lines. FIG. 41 illustrates a configuration example of the selectors 3005a to 3005m in FIG. In the figure, reference numeral 3007 denotes an idle cell detection circuit which detects an idle cell input to the selector, and instructs a selection circuit, which will be described later, the timing of system switching, and 3008, a selection circuit which selects and outputs one of the output lines. Circuit.

Next, the operation will be described. In FIG.
02a to 3002n and the outgoing lines 3006a to 3006n
Description will be made using an example in which the number m of 3006 m is four each. Also, the cells used here are randomly input with a fixed length, the cell input phase is adjusted before being input to the input lines 3002a to 3002d, and the cell input from all the lines is supplied with the same phase. Shall be. Also,
A cell inserted when there is no valid information to be transmitted is called an idle cell. It is assumed that an idle cell input to a cell switch is discarded at the entrance of the cell switch, and that the cell switch outputs an idle cell when the cell switch does not have a valid cell to output.

First, the operation of the cell switch will be described. Since the cell switches 3011 and 3012 have the same configuration, the cell switch 3011 will be described.
FIG. 42 shows input lines 3002a to 3002d and output line 300.
It is a timing chart which shows the timing of the signal of 3a-3003d. (A) to (D) show the incoming line 300 respectively.
2 (a) to 3002d, and (e) to (g) correspond to the output lines 3003a to 3003d. Further, in the figure, the numbers written inside the cells are the input line numbers 3001 to 3003.
004 are input lines 3002a to 3002d and output line number 30
01 to 3004 correspond to the output lines 3003a to 3003d, and the time slot number indicates the time slot arriving at the incoming line. Portions where cells are not shown, such as time slot 2 in (a), are idle cells.

The cells input to the cell switch are sorted for each destination outgoing line and output to an output line. here,
It shall be output in the next time slot. When a plurality of cells to be exchanged for the same output line are input at the same time, they are sequentially output under the control of the cell switch.
Although various control methods are conceivable, as an example, here, the input line number is simply 3001 → 3002 → 3003.
The cells are cyclically output in the order of → 3004 → 3001, and if there is no cell to output, the incoming line number is skipped.

For example, in FIG.
This is the case where the cell with the input line number 3001 was output most recently before 01. Line 3 in time slot 3001
002a to 3002d, output lines 3003a
Cell to be exchanged into
In steps 002 to 3005, input numbers are output in the order of 2 → 3 → 4 → 1. The cell input from the input line 3002d to the time slot 3 is output from the output line 3003 in the time slot 6.
output to a. In such a cell switch, the cells on both sides of the output line, with the idle cell interposed therebetween, are not replaced. For example, the cell of the time slot number 3 and the cell of the time slot number 7 are not replaced in (e) of FIG. The cell is controlled by a first-in first-out method so that a cell having a smaller time slot number is always replaced first.

Next, regarding the operation of the selector, the selector 3
005a will be described. Cell switch 301
A case where the cell switch 3012 switches from a state in which 1 operates as the active system to a state in which the cell switch 3012 operates as the active system will be described with reference to FIGS. 43 and 44. In the timing chart of FIG. 43, (i) to (ヲ) correspond to the incoming lines 3002a to 3002d, respectively.
Is an example of output to the output line when input is made as in (i) to (ヲ). The time slots are the same as those in FIG. FIG. 44 is a time chart showing the appearance of outgoing lines.

As shown in FIGS. 43 (i) to (ヲ), cells output to the output line 3006a, that is, cells output to the output lines 3003a and 3004a of the cell switch are input to the cell switch from the respective input lines. Suppose. The input cells are exchanged by the cell switches 3011 and 3012 and output to the output lines as shown in (W) and (F).
(W) is a case where the cell output starts from the input line number 1,
(F) is a case where it starts from the incoming line number 2. The cell switches 3011 and 3012 exchange cells according to the same control algorithm, but both operate independently, and the order in which input cells are output may be different depending on each cell switch. Therefore, output line 3
The order of cell output may differ between 003a and 3004a. For example, in the output line 3003a, FIG.
As shown in FIG. 44 (a), when a signal is output as shown in FIG. 43 (f) in 3004a and switching is performed at a timing such as point A, as shown in FIG. Will happen.

However, if the switching is performed at the time point B,
Cell dropout and duplication do not occur as in (ta). This is because, as described above, the cells on both sides of the output line sandwiching the idle cell are not replaced. When the selector receives the system switching signal, the idle cell detection circuit 3007 detects the idle cell. When the idle cell comes to both output lines as shown at point B in FIG. 43, this is notified to the selection circuit. The selection circuit switches the output line when receiving this notification from the idle cell detection circuit. The switching of the entire switch ends when switching has been performed by all selectors. As a result, it is possible to perform switching without overlapping or missing cells.

Conventional Example 6 Also, FIG.
FIG. 3 is a block diagram illustrating a configuration of a conventional cell switching device described in US Pat. In FIG. 45, 3110,
Reference numeral 3120 denotes a cell switch for exchanging cells composed of a header part and a data part including an outgoing line number as input destination information based on the destination information. Here, an output buffer type switch having a buffer memory for accumulating cells output corresponding to the switch output line is assumed. Cell switch 3110
And 3120 have the same configuration, one operating as the active system and the other operating as the standby system. Reference numerals 3002a to 3002n denote a plurality of input lines of the cell switching apparatus, which are connected to input side selectors 3041a to 3041n, respectively. 3051
a to 3051n and 3052a to 3052n are switch input lines of the cell switch 3110 and the cell switch 3120, respectively. 3003a to 3003m, 300
4a to 3004m are output lines, 3006a to 3006m are outgoing lines, 3050a to 3050m are outgoing side selectors, 302
1a to 3021m, 3022a to 3022m are cell monitors, 3031a to 3031m, 3032a to 3032m
Is a cell presence / absence signal line. Reference numeral 3060 denotes a controller that gives the cell switches 3110 and 3120 permission for cell output for each switch output line.
Reference numeral 3062 denotes a cell output permission signal line for transmitting an instruction from the controller 3060 to the cell switches 3110 and 3120, respectively.

Next, the operation will be described. Now, cell switch 3
Assume that 110 is operating as an active system. At this time, the controller 3060 has given cell output permission to the cell switch 3110. Incoming line 3021 of cell exchange
The cells arriving at a to 3021n are switched into input lines 3051 at input side selectors 3041a to 3041n, respectively.
a to 3051n are selected and input to the cell switch 3110. The cell switch 3110 performs a switching operation, and switches the cells to switch output lines 3003a to 3003m.
Output to The cells output from the cell switch 3110 are input to output selectors 3050a to 3050m, and output to output lines 306a to 306m via the output selector. On the other hand, the cell switch 3120 is in a standby state.

In this state, it is assumed that a system switching instruction signal is input to switch the active system of the cell switch from the cell switch 3110 to the cell switch 3120. In the input side selectors 3041a to 3041n, the switch input line 30
52a to 3052n are selected. Therefore, the input of the cell to the cell switch 3110 is stopped,
Cells arriving at the input side selectors 3041a to 3041n are input to the cell switch 3120. Cell switch 31
The cell input to 20 is subjected to the same processing as the cell switch 3110. However, until the cell output permission from the controller 3060 is received, the cell switch 312
From 0, no cell is output and is stored in the buffer memory corresponding to the outgoing line inside the cell switch 3120. Even after the system switching instruction is given, the cell switch 3110 outputs the cell stored therein, if any. For example, when a system switching signal is input and a cell is input to the cell switch 3120, as shown in FIG.
4 is stored in the buffer memory corresponding to switch outgoing line 3003a.
Assume that two cells have been stored. Cell switch 311
0 sequentially outputs these four cells. On the other hand, the cells input to the cell switch 3120 and output to the switch output line 3004a are the cell switches 3120
Is stored in the buffer memory corresponding to the switch output line 3004a.

When all the cells output to the switch output line are lost, it is determined that the cell output to the switch output line 3003a is not in the cell switch, and the output selector 3050a is output via the cell presence / absence signal line 3031a. Is transmitted to the controller 3060. Then, the output selector 3050a selects the switch output line 3004a instead of the switch output line 3003a. Further, the controller 3060 notifies the switch 3120 of the output permission of the cell output to the switch output line 3004a through the cell output enable signal line 3062, and the switch output line 3004a.
The cell stored in the buffer memory corresponding to 4a starts to be output to the switch output line 3004a. In this way, switching is performed sequentially for each switch outgoing line, that is, for each outgoing line, and all switch outgoing lines are switched to complete the entire switching. Cell switch 312
0 switches from the state of operating as the active system to the cell switch 3
When the system 110 switches the system to the state of the active system, the operation opposite to the above is performed.

[0027]

Since the data queuing device shown in the prior art 1 is constructed as described above, for example, traffic in which cells are temporally continuous, that is, bursty When high traffic is input and they are destined for a single outgoing line, the common buffer memory 11 becomes full, and there is a problem that cells are discarded. In order to keep the cell discard rate low, the capacity of the common buffer memory may be expanded. However, since the common buffer memory 11 needs to operate after multiplexing cells and requires high-speed operation, it is very expensive and cannot have a large capacity technically. In addition, an increase in the capacity also increases the scale of the buffer control circuit, so there is a limit to the capacity expansion of the common buffer memory.

In the ATM switch shown in the conventional example 2, the capacity can be expanded in the input buffer, and by mounting a large-capacity low-speed buffer, the cell exchange can be efficiently performed with a small output buffer. However, the input control unit needs to detect the destination of the cell arriving from the incoming line and to distribute the destination for each outgoing line. This is because the output buffer is provided for each output line, and congestion occurs separately in each output buffer. For the output buffer where the congestion occurred,
In order to stop the supply of cells, it is necessary to determine in advance which output buffer the cells arriving at the input buffer are to be stored in, so that the control of the input buffer becomes complicated. there were.

The present invention has been made in order to solve the above-mentioned problems, and has a low operating speed while keeping a common buffer memory which is expensive and technically limited in expansion. It is an object of the present invention to obtain a cell switching device capable of suppressing cell loss due to input of burst traffic by adding a buffer.

It is another object of the present invention to provide a cell switching apparatus which can easily control a buffer even when a buffer having a low operation speed is added.

If the switching method described in the third conventional example is applied to the ATM switch shown in the fourth conventional example, the ATM switch can be switched instantaneously without interruption, but when a burst load is applied. In the ATM switch, there is a problem that cells are easily discarded.

In the cell switching apparatuses shown in the conventional examples 5 and 6, the cell switches are duplicated and the instantaneous interruption double switching can be performed by switching the cell switches by the selector. There is a problem that the cell is easily discarded when it is added.

The present invention has been made in order to solve the above-described problems, and it is difficult to cause cell discard even when an ATM switch is blocked, and it is possible to achieve high reliability in which instantaneous interruption and double switching can be performed. The purpose of the present invention is to obtain a cell switching device.

[0034]

[0035]

[0036]

[0037]

[0038]

[Means for Solving the Problems] (a) Data part and its address
Multiple cells to enter cells consisting of header
Depending on the line and, (b) the destination information specified in the header portion of the cell
A plurality of outgoing lines from which cells are output, and (c) a buffer memory.
Memory cell, and the stored cell is designated by its header.
A plurality of cell switches for outputting to a predetermined outgoing line; and (d) cells of a buffer memory of the plurality of cell switches.
Monitoring the hold status and judging the congestion status
A constant section, fill front between the plurality of cell switch to the previous entry line (e)
Provided for each of the lines,
Arrive at the incoming line based on the congestion status determined
Cell evacuation means for temporarily storing the selected cells, wherein the congestion determination means is provided in correspondence with the plurality of cell switches, and a plurality of congestion determination circuits for determining the congestion state of each cell switch; An OR circuit for calculating a logical sum of outputs from the plurality of congestion determination circuits and outputting the result to the cell saving means.

(A) A header including a data portion and its destination information
A plurality of incoming lines to enter the cell made of the reader unit, according to (b) address information specified in the header portion of the cell
A plurality of outgoing lines from which cells are output, and (c) a buffer memory.
Memory cell, and the stored cell is designated by its header.
A plurality of cell switches for outputting to a predetermined outgoing line; and (d) cells of a buffer memory of the plurality of cell switches.
Monitoring the hold status and judging the congestion status
A constant section, fill front between the plurality of cell switch to the previous entry line (e)
Provided for each of the lines,
Arrive at the incoming line based on the congestion status determined
And a cell saving means for temporarily storing the cells before
The congestion determination means includes one congestion determination circuit that monitors the congestion state of the plurality of cell switches, determines the congestion state of the plurality of cell switches, and outputs the result to the cell evacuation means. Features.

The cell switching device further includes an input selector for inputting the cell output from the cell retreating unit to one of the cell switches, and a control for controlling switching to the cell switch selected by the input selector. A circuit is provided.

[0041]

[0042]

[0043]

Further, the cell switching apparatus of the present invention comprises a plurality of incoming lines for inputting a cell comprising a data portion and a header portion including destination information thereof, and a plurality of outgoing lines for outputting the cell.
A cell evacuation circuit that is provided corresponding to the incoming line for temporarily storing the input cells and that has an evacuation buffer in which the cells are actually stored and an evacuation buffer control for managing writing and reading of the cells in the evacuation buffer; A first cell switch having a common buffer type switch for actually exchanging cells and a congestion judgment circuit for judging whether the common buffer type switch is in a congestion state, and a first cell switch having the same configuration as the first cell switch. A second cell switch, an input selector that can switch whether or not to input a cell read from the cell evacuation circuit to the first cell switch and the second cell switch; and The logical sum of the output of the congestion determination circuit of the cell switch and the output of the congestion determination circuit of the second cell switch is input to the cell evacuation circuit. An OR circuit provided for the output line, and an output-side selection circuit that selects one of the cells output from the first cell switch and the second cell switch and outputs the selected cell to the output line; A control circuit that gives the first cell switch output permission of the cell corresponding to the outgoing line, and also provides the second cell switch with the output permission of the cell corresponding to the outgoing line,
When a cell switch switching request is generated, first, the input side selector switches the cell switch for inputting a cell, and the other cell switch is sequentially switched from the output line where the cell output from the cell switch where the cell is no longer input is completed. The switching is performed in such a manner that the output of the cell is started and the corresponding output side selection circuit is switched to select the cell.

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

The cell switching device according to the present invention has a buffer memory.
Detects congestion from cell hold status in
Notify the congestion state to the corresponding cell evacuation circuit
And restricts cells from entering the cell switch,
In cell switch without increasing buffer memory
Cell waste caused by exceeding the capacity of
A cell switching device that can reduce the loss rate is realized. Ma
In addition, the cell switch is duplicated and can be switched
A highly reliable cell switching device is realized. In addition, the cell switching device according to the present invention is provided with a congestion determination circuit corresponding to a cell switch, and when a congestion state is detected in any of the cell switches by a simple hardware called an OR circuit, the cell evacuation unit is provided. To report the congestion state of the cell switch.

The cell switching device according to the present invention comprises a buffer
Detect congestion state from cell pending state in memory and enter
The congestion state in the cell evacuation circuit provided corresponding to the line
Notify, restrict cells from entering the cell switch,
Cell switching without increasing expensive buffer memory
Cells caused by exceeding the capacity of the buffer memory in the switch
Realization of a cell switching device that can reduce
You. In addition, the cell switch is duplicated,
A highly reliable cell switching device is realized. Also, the cell switching apparatus according to the present invention determines the congestion state by providing only one congestion determination circuit for a plurality of cell switches. Therefore, the hardware circuit for determining congestion can be simplified as compared with the above-described cell switching apparatus.

In the cell switching apparatus according to the present invention, an input selector is provided in front of a plurality of cell switches, and a control circuit controls switching to the cell switch selected by the input selector, thereby providing a consistent cell switch. Can be switched.

[0056]

[0057]

[0058]

Further, the cell switching apparatus according to the present invention comprises:
Each of the duplicated cell switches has a congestion determination circuit, and the outputs are ORed to store cells in one of the cell switches when the cell switch is congested. At the time of switching the cell switch, first, the input side selector at the preceding stage of the cell switch switches the cell switch for inputting the cell, and sequentially switches the output line from the output line where the output from the cell switch where the cell is no longer input is completed.

[0060]

[0061]

[0062]

[0063]

[0064]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are views showing an embodiment of the present invention. 35, the same reference numerals as those in FIG. 35 indicate the same or corresponding parts as those in FIG.

In FIG. 1, reference numerals 1 ₁ to 1 _n designate an ATM comprising a header portion including an outgoing line number as destination information and a data portion.
The n incoming lines 21 ₁ to 2 _m input by the cell are the m outgoing lines from which the cell is output according to the destination specified in the header thereof, and these are the conventional outgoing lines (FIG. 35). Is equivalent to

[0066] 3 ₁ to 3 _n, the switch input lines for transferring the cell input provided corresponding to the incoming line ₁ 1 to 1 _n the shared buffer switch, 4 ₁ to 4 _m is the output line 2 ₁ to 2 _m switch output line for outputting the cell from the shared buffer switch provided corresponding to, 9 distributes the cell on the basis of the destination information of the cell entered in the output line 2 ₁ to 2 _m, also inside the output line 2 ₁ - It has a buffer memory that is shared and used between 2 _meters , and is a necessary switch for waiting.

Reference numeral 20 denotes a congestion determination circuit for judging whether or not the buffer memory of the common buffer type switch 9 is in a congestion state, and reference numeral 21 denotes a common buffer type switch 9.
Is a switch internal monitor that monitors the buffer memory of the switch and notifies the congestion determination circuit. Reference numeral 31 denotes a congestion judgment output line for notifying the judgment result of the congestion judgment circuit to cell saving circuits 22 _{1 to} 22 _n to be described later.

Also, 22 _{1 to} 22 _n are input lines 1 ₁ to 1 _n
And a cell evacuation circuit for accumulating cells input to the input lines ₁₁ to 1 _n and suppressing the input of cells to the common buffer type switch 9 when the congestion determination circuit 20 determines that the congestion state has occurred. The cell save circuit 22 includes a save buffer 23 and a save buffer control circuit 24. 23
₁ ~ 23 _n are provided in the cell save circuit 22 ₁ through 22 _n, respectively, a save buffer that actually store the input cell, 24 ₁ to 24 _n may each cell save circuit 22 ₁
It provided inside the through 22 _n, save buffer 23 _1-23
This is a save buffer control circuit that controls writing and reading of cell _n .

FIG. 2 shows an embodiment of the common buffer type switch 9 in FIG. 1 in detail. In FIG. 2, the suffix a such as 9a indicates that it is one form of the common buffer type switch of the present embodiment. 3 _{1 to} 3 _n , 4
₁ to 4 _m, 9a, 21a is 3 in FIG. 1, respectively ₁
~3 _n, 4 ₁ ~4 _m, indicate the same parts and 9, 21.

[0070] 10 ₁ to 10 _n are, each of said switch input lines provided corresponding switch input lines 3 ₁ to 3 from the header portion of the cells inputted from _n of the destination output line 4 _1-4
This is a header processing circuit that detects _m .

Reference numeral 11 denotes a common buffer memory for storing the cells at a designated address and reading the stored address by designating the address irrespective of the writing order. A plurality of cells can be stored in one common buffer memory 11.

A reference numeral 12 is provided corresponding to the common buffer memory 11 and manages free addresses using, for example, a FIFO type memory, and provides a free address for providing a read address and a write address to the associated common buffer memory 11. An address management circuit.

Reference numeral 7 denotes the header processing circuits 10 ₁ to 10 _n
And the common buffer memory 11 are connected, the input cells are multiplexed in cell units or predetermined bit units, and the speed is increased or multi-bit parallel processing is performed. It is a cell multiplexing circuit that enables it. 8 connects said shared buffer memory 11 and the switch output lines 4 ₁ to 4 _m, a cell read at a high speed or multi-bit parallel from the shared buffer memory,
Separated into a cell unit or bit units determined, a cell separation circuit for distributing cells to the switch output line 4 ₁ to 4 _m.

15a manages the addresses of the cells stored in the common buffer memory 11 for each cell destination and controls reading of the common buffer memory 11 based on the addresses managed for each destination. the switch output lines ₄₁ to be designated the cell in its header
_This is a buffer control circuit that outputs to _m in a predetermined order.

[0075] Further, in the buffer control circuit 15a, 16a, when the cell arrives at the switch input lines 3 ₁ to 3 _n, the header processing circuits 10 ₁ ~ associated with the switch input lines 3 ₁ to 3 _n detected by 10 _n the outgoing line 2 ₁ to 2 _m or switch output line of the cell 4 ₁
Undergoing 4 _m number, also receives a write address for the shared buffer memory 11 of the cell than the available address management circuit 12, and the presence or absence of the arrival of a cell to each switch input line 3 ₁ to 3 _n, the destination, This is a write buffer selection circuit that sets a write address to the common buffer memory 11 and notifies the address exchange circuit 17 to be described later.

17 is the write buffer selection circuit 1
6a of the detected outgoing lines 2 ₁ to 2 _m or switch output line 4
₁ to 4 _m numbers referring to the destination switch divided output lines 4 ₁ to 4 _m apart of cells arriving to the address queue 18 _1-18 to be described later write address in the buffer memory 11 to which the cell has been written _An address exchange circuit for writing to _m .

[0077] 18 ₁ ~ 18 _m is its address queue, is constituted by a FIFO (First In First Out) type of memory, it is provided corresponding to each of the switch output lines 4 ₁ to 4 _m. This address queue 18
₁ ~ 18 _m, it is the switch output line 4 for each _one to 4 _m correlated, stored write address in the buffer memory 11 of the cell to the switch output lines 4 ₁ to 4 _m destined The address exchange circuit 1 in the order of arrival.
7 is written.

The reference numeral 19a denotes the address queues 18 ₁ to 18a.
18 with reference to the _m determines the cell to be read out from the buffer memory 11, an example is shown which is provided corresponding to each of the _m read out from the address queue 18 ₁ ~ 18 _m, the delay request class to handle Accordingly, when the shared buffer type switch 9 for priority control, it is also possible to provide a plurality of address queue for one switch output line 4 ₁ to 4 _m.

The reference numeral 21a monitors the number of cells stored in the common buffer memory 11, and
Is a switch internal monitor that notifies the switch.

Next, the operation will be described. Here cells described fixed length, which arrives as a random or burst traffic, and the cell input phase is adjusted prior to input to the input line 1 ₁ to 1 _n, the cell input from all incoming identical It shall be supplied in phase.

First, the common buffer type switch 9 will be described. When the switch input lines 3 cells in ₁ to 3 _n arrives, the destination information written in the internal header is read by the header processing circuit 10 ₁ to 10 _n, is notified to the buffer control circuit 15a internal write buffer selection circuits 16a You.

The free address management circuit 12 stores unused free addresses in the common buffer memory 11.
Hold. Switch input lines 3 ₁ to 3 _n is n this but, n
Since cells may arrive at all of the switch input lines, the empty address management circuit 12 can provide n empty addresses to the write buffer selection circuit 16a.

The cells input to the switch input lines 3 _{1 to} 3 _n and then passed through the header processing circuits 10 ₁ to 10 _n are:
The signal is input to the cell multiplexing circuit 7. The cell multiplexing circuit 7 performs high-speed processing so that outputs of the plurality of header processing circuits 10 ₁ to 10 _n can be input to one common buffer memory 11. If the limit operation speed of the common buffer memory 11 is low, the data may be expanded into multiple bits and parallel processing may be performed. Various methods for multiplexing cells in the cell multiplexing circuit 7 are conceivable. For example, there is a method of increasing the speed by rearranging cells. There is also a method of rearranging the data in a predetermined bit unit such as a byte multiplexing method.

The cells multiplexed by the cell multiplexing circuit 7 are input to the common buffer memory 11 and written to the address specified by the empty address management circuit 12. If there is no free address, this input cell is discarded.

The write buffer selection circuit 16a inside the buffer control circuit 15a
₁ to 10 _n receives the number of the destination output line 2 ₁ to 2 _m or destination switch output lines 4 ₁ to 4 _m of the presence or absence of cell arrival and the cell from, also shared buffer memory 11 of the cell than the available address management circuit 12 Receive write address to The destination and the write address to the common buffer memory 11 are paired and notified to the address exchange circuit 17 for each arrival cell.

[0086] address exchange circuit 17, with reference to the detected destination outgoing line 2 ₁ to 2 _m or number of the destination switch output lines 4 ₁ to 4 _m of the write buffer selection circuits 16a,
The common buffer memory 11 in which the arriving cells are written
The above write address is changed to the destination switch output line 4 _1-
Distribute every 4 _m . Then, write the write address into the address queue 18 ₁ ~ 18 _m.

[0087] address queue 18 ₁ ~ 18 _m are provided corresponding to each of said switch output lines 4 ₁ to 4 _m,
Each is constituted by a FIFO type memory. The address queue 18 ₁ ~ 18 _m, it is the switch output line 4 for each _one to 4 _m associated, shared buffer memory 11 that is accumulated in the cells that the switch output lines 4 ₁ to 4 _m and destination A queue of the above write addresses can be created.

Here, the address queues 18 ₁ to 18
_m, the shows an example provided corresponding to each of the switch output lines 4 ₁ to 4 _m, but the delay request class to handle the case of shared buffer switch 9 for priority control, one switch it is also possible to provide a plurality of address queue to the output lines 4 ₁ to 4 _m.

The write addresses arranged in the address queues 18 ₁ to 18 _m wait for the turn to come.
Read buffer selecting circuit 19a includes, as with reference to the front row to determine the cell to be read out from the buffer memory 11, reads the address read from the address queue 18 ₁ ~ 18 _m addresses of the address queues 18 ₁ ~ 18 _m , To the empty address management circuit 12 corresponding to the buffer memory 11.

The free address management circuit 12 receives the next address to be read from the read buffer selection circuit 19. Read address, to present corresponding to each of switch output lines 4 ₁ to 4 _m, is m number notified at most one cell slot. The free address management circuit 12
Indicates the read address to the common buffer memory 11 and reads the cell. The cells read from the common buffer memory 11 are transmitted to the cell separation circuit 8. Further, the read address used for reading is released, stored in a circuit for storing free addresses in the free address management circuit 12, and used cyclically.

The cell separation circuit 8 includes the common buffer memory 1
A plurality of cells read at high speed from ₁ are separated into switch output lines 41 to 4 _m . If the read signal is arranged in a predetermined bit unit such as byte multiplexing, it has a function of converting the read signal into a cell unit or another predetermined bit unit.

As described above, the common buffer type switch 9
a, the input cell is stored in one common buffer memory 11;
And outputs the address to the switch output lines 4 ₁ to 4 _m
The cells are exchanged by queuing them in units. Also, the used addresses can be used cyclically.

Next, the operation of the congestion determination circuit 20 will be described. The congestion determination circuit 20 monitors the number of cells stored in the common buffer memory 11 inside the common buffer type switch 9a by the switch internal monitor 21, and compares the number with a preset threshold to indicate a congestion state. Is determined.

FIG. 3 is a diagram showing a system in which the switch internal monitor 21 monitors the number of cells stored in the common buffer memory 11. In FIG. 3, (a), (b),
(C) shows three methods. The method (a) shows a case where the switch internal monitor 21a counts the number of accumulated cells based on the number of write pulses and the number of read pulses. The empty address management circuit 12 supplies a write pulse and a write address and a read pulse and a read address to the common buffer memory 11 when writing and reading a cell to and from the common buffer memory 11.
The write pulse and the read pulse are pulses indicating write and read timings. By monitoring these pulses, it is possible to know the number of cells written to the common buffer memory 11 and the number of cells read. it can. Therefore, the number of cells stored in the common buffer memory 11 can be detected by using the following expression: cell storage number = write pulse number−read pulse number.

Next, the method (b) will be described. The free address management circuit manages free addresses. The number of stored cells may be calculated from the number of free addresses. That is, assuming that the number that can be stored in the common buffer memory 11 is the total storage number and the number of free addresses is the free number, the number of cells stored in the common buffer memory 11 is calculated by the following formula: Can be detected.

Next, the method (c) will be described. The methods (a) and (b) describe the case where the number of stored cells is directly calculated. However, the method (c) determines whether a cell exists for each address in the common buffer memory. It has a flag indicating whether or not it is, and outputs this flag sequence. The position of this flag may be inside the common buffer memory 11 or inside the free address management circuit 12. In the example shown in FIG. 3, when the common buffer memory 11 can store a total of 12 cells, six addresses are already occupied by cells, and the remaining six are empty. ing. This flag is transmitted to the congestion determination circuit 20, and the congestion determination circuit 20 can detect the number of stored cells by counting the number of times that the flag is on.

FIGS. 4 and 5 show the procedure of the congestion determination circuit 20. The threshold T used for congestion determination is
Set at initial time. The procedure of the congestion determination circuit 20 shown in FIG. 4 is as follows. As shown in FIG. 5, the number of stored cells in the common buffer type switch 9a is read from the monitor inside the switch for each cell slot and compared with the previously set threshold value. In this way, the congestion state is determined.

Next, the operation of the cell save circuit 22 will be described. The cell save circuit 22 includes a save buffer 23 and a save buffer control circuit 24. Save buffer 2
3 can be constituted by a FIFO (first in first out) type memory, for example. The save buffer control circuit 24 is a circuit that controls writing and reading of the save buffer 23. When the save buffer 23 is a FIFO type memory, the save buffer control circuit 24 generates a write pulse and a read pulse.

Separately, the save buffer 23 is a RAM
In the case of (random access type memory), the save buffer control circuit 24 manages the write address and the read address, and performs control to circulate and use the addresses. That is, 1 is added to the write address when the cell is written, and 1 is added to the read address when the cell is read. In this case, the save buffer control circuit 24 gives the write address and the write pulse and the read address and the read pulse to the save buffer 23.

FIG. 6 is a flowchart of the cell save circuit 22 and mainly shows the control procedure of the save buffer control circuit 24. When a cell arrives at the incoming line 1, the save buffer control circuit 24 performs control to write the cell into the internal save buffer 23. However, if the save buffer 23 is full, the input cell is discarded. On the other hand, the save buffer control circuit 24 monitors the congestion determination circuit 20, and reads out the cells stored in the save buffer 23 when the congestion is not in the congestion state. If the state is congested, no cell is read from the save buffer 23.

FIG. 7 is a diagram showing a specific operation of the save buffer. Figure 7 shows the operation of the save buffer when the cell A, the cell C, the cell E, cell H is input to the input line 1 ₁ shown in FIG. Here, cell slot 1
In cell slot 4, the congestion determination circuit 20 determines that the state is not a congestion state, and in cell slot 2 and cell slot 3, the congestion state is detected. First, in the cell slot 1, the cell A is stored in the evacuation buffer.

Next, in cell slot 2, cell A
Is output from the save buffer and the cell C is accumulated. In the cell slot 1, since the congestion determination circuit detects that the state is not congested, the cell A is output from the evacuation buffer.

Next, in the cell slot 3, since the congestion determination circuit 20 has detected the congestion state in the cell slot 2, the cell C remains stored in the save buffer. In the cell slot 3, the cell E is input and stored in the save buffer.

Next, in the cell slot 4, since the congestion determination circuit 20 has detected the congestion state in the cell slot 3, the cells C and E remain stored in the save buffer. In the cell slot 4, a cell H is newly stored.

Next, in the cell slot 5, since the congestion determination circuit 20 in the cell slot 4 has detected that the congestion is not in the congestion state, the cell C is output from the save buffer.

As described above, this embodiment is characterized in that a cell save circuit is provided for the common buffer type switch 9 to reduce the cell discard rate of the cells of the common buffer memory in the common buffer type switch. It is the point which did so. In particular, the cell save circuit only needs to control the accumulation of cells based on the report of the congestion state from the congestion determination circuit, and the cell save circuit can be easily configured.

In the case of the prior art 2 described in the prior art,
Buffers are provided corresponding to the outgoing lines. A circuit is provided to temporarily accumulate cells corresponding to each of the so-called output buffer switches, and it is determined that the output buffer corresponding to the outgoing line is in a congestion state, and whether the output buffer is a cell corresponding to the output buffer. After judging,
It was necessary to determine in advance whether cells should be stored or not, and a complicated configuration had to be taken. In contrast, in the case of the common buffer type switch as shown in this embodiment, since one common buffer is provided for the outgoing line, it is simple to determine whether or not the common buffer is in a congestion state. Based on your judgment, and
This is to perform cell accumulation control without individually judging the destination of the cell arriving by the cell retreat circuit.

Next, FIG. 8 is a diagram showing an example of a mounting form of the cell switching apparatus shown in FIG. In FIG. 8, 100
Is a common buffer type switch 9 and a congestion determination circuit 20
This is a common buffer type switch board on which is mounted. 200
₁ to 200 _n are interface boards. Each interface board is provided corresponding to one input line and one output line, and has an interface circuit for connecting the pair of input and output lines to the common buffer type switch 9. For example, when the incoming and outgoing lines are constituted by optical fibers, a photoelectric conversion circuit and an electro-optical conversion circuit are mounted. Further, an interface circuit for synchronizing and performing an error check is mounted. Further, the above-described cell evacuation circuit is provided on the incoming line side. Each interface board and the common buffer type switch board are connected by a switch input line and a switch output line. The congestion determination output line 31 from the congestion determination circuit 20 is connected to the respective interface boards 200 ₁ to 2 from the common buffer type switch board 100.
00 is connected to the cell save circuit of _n.

Embodiment 2 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. 1 and 9 are block diagrams showing a configuration of a cell switching device according to one embodiment of the present invention. In the figure, the same or corresponding parts as those of the cell switching apparatus according to the first embodiment (FIGS. 1 and 2) are denoted by the same reference numerals.

In FIG. 1, reference numerals 1 ₁ to 1 _{n denote} ATs each composed of a header portion including an outgoing line number as destination information and a data portion.
N number of incoming lines which are M cells enter, 2 ₁ to 2 _m, the cell is a m number of outgoing lines is output in accordance with a specified destination by the header portion.

[0111] 3 ₁ to 3 _n, the switch input lines for transferring the cell input provided corresponding to the incoming line ₁ 1 to 1 _n the shared buffer switch, 4 ₁ to 4 _m is the output line 2 ₁ to 2 switch output line for outputting the cell from the shared buffer switch provided corresponding to _m, 9 are distributed cells on the basis of the destination information of the cell entered in the output line 2 ₁ to 2 _m, also, the output line 2 ₁ therein A common buffer type switch is provided with a buffer memory commonly used between .about.2 _m , and a cell requiring a wait is written into the buffer memory to exchange cells.

Reference numeral 20 denotes a congestion determination circuit for judging whether or not the buffer memory of the common buffer type switch 9 is in the congestion state, and 21 monitors the buffer memory of the common buffer type switch 9 and notifies the congestion determination circuit. Monitor inside the switch. Reference numeral 31 denotes a judgment result of the congestion judging circuit, which is referred to as a cell evacuation circuit 22 _{1 to} 22 _n described later.
Is a congestion determination output line for notifying the user.

Also, 22 _{1 to} 22 _n are input lines ₁₁ to 1 _n
And a cell evacuation circuit for accumulating cells input to the input lines ₁₁ to 1 _n and suppressing the input of cells to the common buffer type switch 9 when the congestion determination circuit 20 determines that the congestion state has occurred. The cell save circuit 22 includes a save buffer 23 and a save buffer control 24. 23 ₁ ~
23 _n are respectively provided inside the cell save circuit 22 ₁ through 22 _n, a save buffer that actually store the input cell, 24 ₁ to 24 _n may each cell save circuit 22 ₁ -
22 _n provided inside of the save buffer 23 ₁ ~ 23 _n
Is a save buffer control circuit that controls writing and reading of the cell.

FIG. 9 is a diagram showing in detail one embodiment of the common buffer type switch 9 in FIG. In FIG. 9, the suffix b such as 9b indicates that it is one form of the common buffer type switch of the present embodiment. 3 _{1 to} 3 _n , 4
₁ to 4 _m , 9b and 21b respectively correspond to 3 ₁ in FIG.
~3 _n, 4 ₁ ~4 _m, indicate the same parts and 9, 21.

10 ₁ to 10 _n are provided corresponding to the respective switch input lines, and the output lines 4 ₁ to 4 of the destination from the header portion of the cell input from the switch input lines 3 _{1 to} 3 _n.
This is a header processing circuit that detects _m .

Also, 11 _{1 to} 11 _p are _p number of cells in which the cells can be stored at a specified address and the stored address can be read by specifying the address, regardless of the order of writing. common buffer memory, capable of storing a plurality of cells also one of the common buffer memory 11 ₁ to 11 _p of.

[0117] 12 ₁ to 12 _p are provided corresponding to each of the shared buffer memory 11 ₁ to 11 _p, such as F
It manages the free address using the IFO types of memory, an empty address management circuit for providing a read address and write address to the buffer memory 11 ₁ to 11 _p associated.

Reference numeral 13 denotes the header processing circuits 10 ₁ to 10
The _n is the incoming line side cross-point switch for selectively connecting a predetermined shared buffer memory 11 ₁ to 11 _p. 14
Is the outgoing line side cross-point switch for selectively connecting said common buffer memory 11 ₁ to 11 _p to a predetermined switch output lines 4 ₁ to 4 _m.

[0119] 15b, together with the cell by controlling the switching of the entering-line side cross-point switch for selecting the shared buffer memory 11 ₁ to 11 _p to be accumulated, stored in the shared buffer memory 11 ₁ to 11 _p Cell addresses are managed for each cell destination, and the common buffer memory 11 ₁ is managed based on the addresses managed for each destination.
To 11 by controlling the _p reading, the cell to said switch output lines 4 ₁ to 4 _m designated by the header part is a buffer control circuit for outputting in a predetermined order.

[0120] Further, in the buffer control circuit 15b, 16b, when a cell arrives at the switch input lines 3 ₁ to 3 _n, the header processing circuits 10 ₁ ~ associated with the switch input lines 3 ₁ to 3 _n outgoing line 2 ₁ to 2 _m of the cell detected by 10 _n or switch output lines 4 _1,
Receiving a number of to 4 _m, the shared buffer memory 11 ₁ to 11 for it by selecting the _p connecting to the header processing circuit 10 ₁ to 10 _n to the previous entry line side cross-point switch 13 for storing the cell Is a write buffer selection circuit that controls the switching of. In addition, the write buffer selection circuit 16b includes the empty address management circuits 12 ₁ to 12 ₁
Receiving a write address for the shared buffer memory 11 ₁ to 11 _p than 2 _p. Then, each switch input line 3 ₁ -
Whether the arrival of the cells to 3 _n, the destination, and a set of numbers and the write address of the shared buffer memory 11 ₁ to 11 _p, and notifies the address exchange circuit 17 which will be described later.

Reference numeral 17 denotes this write buffer selection circuit 1.
6b of the detected outgoing lines 2 ₁ to 2 _m or switch output line 4
₁ to 4 _m numbers referring to the destination switch divided output lines 4 ₁ to 4 _m apart of cells arriving to the, number and address to be described later the write address of the buffer memory 11 ₁ to 11 _p in which the cell has been written An address exchange circuit for writing to the queues 18 ₁ to 18 _m .

[0122] 18 ₁ ~ 18 _m is its address queue, is constituted by a FIFO (First In First Out) type of memory, it is provided corresponding to each of the switch output lines 4 ₁ to 4 _m. This address queue 18
_1-18 The _m, it to the switch output line 4 for each _one to 4 _m correlated, stored the buffer memory 11 ₁ to 11 _p of cells the switch output lines 4 ₁ to 4 _m and destination
Are written by the address exchange circuit 17 in the order of arrival.

19b is the address queue 18 ₁ .
18 with reference to the _m determines the cell to be read out from the buffer memory 11 ₁ to 11 _p, the address queues 18 ₁ to 1
As a read address the address read from the 8 _m, and sends to the empty address management circuit 12 ₁ to 12 _p associated with the relevant buffer memories 11 ₁ to 11 _p, to control the switching of the outgoing line side cross-point switch 14 Te, the shared buffer memory 11 ₁ to 11
a read buffer selection circuit connecting the _p to the appropriate switch output lines 4 ₁ to 4 _m.

21b is a common buffer memory 11 ₁ to 1
Monitors the total number of accumulated and have cell 1 _p, a switch internal monitor to notify the congestion determination circuit 20.

Next, the operation will be described. Here cells described fixed length, which arrives as a random or burst traffic, and the cell input phase is adjusted prior to input to the input line 1 ₁ to 1 _n, the cell input from all incoming identical It shall be supplied in phase.

First, the common buffer type switch 9 will be described. When the switch input lines 3 cells in ₁ to 3 _n arrives inside the written address information header is read by the header processing circuit 10 ₁ to 10 _n, it is notified to the buffer control circuit 15b inside the write buffer selecting circuit 16b You.

The vacant address management circuits 12 _{1 to} 12 _p are:
A free address which is not used in the shared buffer memory 11 ₁ to 11 _p is memorized and stored. Switch input lines 3 ₁ to
3 _n are n. Since there is a possibility that cells may arrive at all n switch input lines, the empty address management circuit 12
₁ to 12 _p is to be able to provide a total of the n-number of buffer selection circuit 16b writes a free address.

The cells input to the switch input lines 3 _{1 to} 3 _n and then passing through the header processing circuits 10 ₁ to 10 _n are:
It is input to the incoming line side cross point switch 13. The incoming line side cross point switch 13 changes the switching for each cell slot in accordance with the instruction of the write buffer selection circuit 16b,
₁ to 10 _n are stored in a predetermined common buffer memory 11 _{1 to} 11 _p
Selective connection to

[0129] The connected cells in the shared buffer memory 11 ₁ to 11 _p by the entering line side cross-point switch 13 are input to a common buffer memory 11 ₁ to 11 _p, a free address management circuit 12 ₁ to 12 _p Written to the specified address. If there is no free address, this input cell is discarded.

The write buffer selection circuit 16b inside the buffer control circuit 15b
₁ to 10 _n receives the presence or absence of cell arrival and destination outgoing line 2 ₁ to 2 _m or number of the destination switch output lines 4 ₁ to 4 _m of the cell from and empty address management circuit 12 ₁ to 12 _p than of the cell receive a write address to the common buffer memory 11 ₁ ~11 _p. The destination and its common buffer memory 11 are sent to the address exchange circuit 17 for each arrival cell.
In the set ₁ to 11 _p number and the write address, and notifies.

The buffer control circuit 15b also controls the switching of the input-side cross point switch 13,
The shared buffer memory 11 ₁ to 1, which is selected to store the incoming header processing circuit 10 ₁ to 10 _n and the cells of the cell
An instruction to connect the 1 _p individually.

Here, the incoming line side cross point switch 1
3 ways of connection are various, but the cell is stored in the shared buffer memory 11 ₁ to 11 _p, to the same buffer memory 11 ₁ to 11 in the _p when it is read out later, that the read would like cells are two or more Since this is undesirable, cells are stored in a large number of common buffer memories 11 ₁ to 11 ₁ to prevent this.
It is a method of dispersing a 11 _p.

For this purpose, the buffer memories 11 ₁ to 11 ₁
1 _p is not enough as many switch input lines 3 ₁ to 3 _n, in order to solve the above problem, the Write as many shared buffer memory 11 ₁ to 11 _p is simplified control .

[0134] Alternatively a method of dispersing Separately, cells in a number of shared buffer memory 11 ₁ to 11 _p to that, there is a method of sequentially selected. N for a cell slot
When cells x number simultaneously of the switch input lines 3 ₁ to 3 _n arrives, the shared buffer memory 11 ₁ to 11
_{If x} is selected and y cells arrive in the next cell slot, the common buffer memories 11 _{x + 1 to} 11 _{x + y} are selected.

As still another method, the remaining cell remaining in each of the common buffer memories 11 _{1 to} 11 _p is recorded,
The common buffer memories 11 ₁ to 11 having the least cell reservation remaining amount
How to write the cells by selecting the 11 _p is also conceivable. That is, when the x number of cells arrive simultaneously at some cell slot is a method for selecting the smallest x-number of the shared buffer memory 11 ₁ to 11 _p of the cell holding the remaining amount. Thus, a plurality of shared buffer memory 11 ₁ to 11 _p can be regarded as one large common buffer memory.

[0136] address exchange circuit 17, with reference to the detected destination outgoing line 2 ₁ to 2 _m or number of the destination switch output lines 4 ₁ to 4 _m of the write buffer selecting circuit 16b,
Buffer memory 11, the arriving cell is written ₁ to
The number and the write address of 11 _p, distributes separately switch output lines 4 ₁ to 4 _m of the destination. Then, it writes them into the address queue 18 ₁ ~ 18 _m.

[0137] address queue 18 ₁ ~ 18 _m are provided corresponding to each of said switch output lines 4 ₁ to 4 _m,
Each is constituted by a FIFO type memory. The address queue 18 ₁ ~ 18 _m, it is the switch output line 4 for each _one to 4 _m associated buffer memories 11 ₁ stored in the cell to the switch output lines 4 ₁ to 4 _m and destination ~11 _p and the queue of the write address can be made.

Here, the address queue 18₁ ~ 18
_m Is the switch output line 4₁ ~ 4 _m Corresponding to each of
Although the example provided is shown, the delay request class to be handled
Of the common buffer type switch 9 that performs priority control
In case, one switch output line 4₁ ~ 4_m Multiple for
It is also possible to provide multiple address queues.

The write addresses arranged in the address queues 18 ₁ to 18 _m wait for the turn to come.
Read buffer selecting circuit 19b refers to the front row to determine the cell to be read out from the buffer memory 11 ₁ to 11 _p, read from the address queue 18 ₁ ~ 18 _m addresses of the address queues 18 ₁ ~ 18 _m as a read address, the buffer memory 11 ₁ to 11 _p
Sent to the empty address management circuit 12 ₁ to 12 _p corresponding to.

The read buffer selection circuit 19b
A common buffer memory 11 ₁ to 11 as cell being read from _p is output to the switch output line 4 ₁ to 4 _m is a predetermined destination, the outgoing line side cross-point switch 14
Control switching. This switching to the cell slot unit shows the individual connection of the shared buffer memory 11 ₁ to 11 _p and the switch output lines 4 ₁ to 4 _m.

The empty address management circuits 12 _{1 to} 12 _p are:
The next address to be read is received from the read buffer selecting circuit 19. The read address is the switch output line 4
_{Since there is one} corresponding to each of ₁ to 4 _m, a maximum of m totals are notified in one cell slot. Also, empty address management circuit 12 ₁ to 12 _p is shared buffer memory 11
The read address and instructs the ₁ to 11 _p, reads the cell. The shared buffer memory 11 ₁ to 11 the cells read from _p, the outgoing line side cross-point switch 14
Sent to. Further, the read address used for reading is opened, empty address management circuit 12 ₁ to 1
Stored in the circuit for storing the 2 _p vacant addresses of the internal, it is used circulating.

As described above, the common buffer type switch 9
b indicates that the input cells are stored in p common buffer memories 11 _1.
Write to to 11 _p, the switch output line 4 the address
_The cells are exchanged by queuing them in ₁ to 4 _m units.
Also, the used addresses can be used cyclically.

Next, the operation of the congestion determination circuit 20 will be described. The congestion determination circuit 20 monitors the number of cells stored in the common buffer memory 11 inside the common buffer type switch 9b by the switch internal monitor 21 and compares the number with a preset threshold value. Determine the status.

FIGS. 4 and 5 show the procedure of the congestion determination circuit 20. FIG. The threshold T used for congestion determination is
Set at initial time. The congestion state is determined by reading the number of cells stored in the common buffer type switch 9b from the monitor inside the switch for each cell slot and comparing the read number with the previously set threshold value.

Here, the difference from the first embodiment is that
The common buffer memory is composed of a plurality of memories. Therefore, the switch internal monitor 21b is provided with the number of cells stored in each common buffer memory. The cell save circuit detects the total number of stored cells by adding the number of stored cells sent from each common buffer memory. As a method of detecting the number of cells stored in each common buffer memory, a method as shown in FIG. 3 can be considered. Alternatively, the buffer control circuit 1
The number of stored cells may be calculated using the number of buffer selections of the write buffer selection circuit 16b and the read buffer selection circuit 19b in 5b. That is, the write buffer selection circuit 16b selects a common buffer memory for storing cells, and each time a common buffer memory is selected, a cell is recorded in one of the common buffer memories. Therefore, by counting the number of times the common buffer memory is selected by the write buffer selection circuit, the number of cells input to the common buffer can be known. Similarly, the read buffer selection circuit 19b
By counting the number of times the common buffer memory is selected, the number of cells output from the common buffer memory can be detected. Therefore, the number of stored cells may be calculated by the following formula: the number of stored cells = the number of selected common buffer memories of the write buffer selecting circuit−the number of selected common buffer memories of the read buffer selecting circuit, and may be provided to the switch internal monitor 21b. Absent.

Next, the operation of the cell save circuit 22 will be described. The cell save circuit 22 includes a save buffer 23 and a save buffer control 24. Save buffer 23
Can be constituted by, for example, a FIFO (first-in first-out) type memory. The save buffer control 24 is a circuit that controls writing and reading of the save buffer 23. When the save buffer 23 is a FIFO type memory, the save buffer control circuit 24 generates a write pulse and a read pulse.

Separately, the save buffer 23 is a RAM
In the case of (random access type memory), the save buffer control circuit 24 manages the write address and the read address, and performs control to circulate and use the addresses. That is, 1 is added to the write address when the cell is written, and 1 is added to the read address when the cell is read. In this case, the save buffer control circuit 24 gives the write address and the write pulse and the read address and the read pulse to the save buffer 23.

FIG. 6 is a flowchart of the cell save circuit 22 and mainly shows a control procedure of the save buffer control circuit 24. When a cell arrives at the incoming line 1, the save buffer control circuit 24 performs control to write the cell into the internal save buffer 23. However, if the save buffer 23 is full, the input cell is discarded. On the other hand, the save buffer control 24 monitors the congestion determination circuit 20, and reads out the cells stored in the save buffer 23 when the congestion is not in the congestion state. If the state is congested, no cell is read from the save buffer 23.

As described above, in this embodiment, even when the common buffer memory is composed of a plurality of memories, the cell save circuit is provided as in the first embodiment.
The cell loss rate in the common buffer memory can be reduced. Although there are a plurality of common buffer memories, they do not correspond to outgoing lines, and the cell save circuit does not need to perform complicated control of saving cells arriving for each outgoing line. That is, even when the common buffer memory includes a plurality of memories, the congestion determination circuit determines whether a congestion state has occurred in the plurality of common buffer memories as a whole, and based on the determination result, the cell evacuation circuit. Can control the accumulation of the cells that have arrived.

Embodiment 3 FIG. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a flowchart showing a procedure of the congestion determination circuit 20 of the cell switching apparatus according to one embodiment of the present invention. Cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6) and second embodiment described above
The same reference numerals are given to the same or corresponding parts as those of the cell switching device (FIG. 1, FIG. 4, FIG. 6, FIG. 9) of FIG.

FIG. 10 illustrates the operation of the congestion determination circuit 20. The congestion determination circuit 20 monitors the number of cells stored in the common buffer memory 11 inside the common buffer type switch 9 by the switch internal monitor 21 and compares the number with a preset threshold value. Determine the status.

FIG. 28 shows that the threshold value T is reset for each cell slot. Thus, a change in the congestion determination condition can be quickly responded to a change in call setting or a change in system conditions. For example, if a line fails and a certain route cannot be used,
A method of transferring cells using another line is generally used. In such a case, cells may be more concentrated on a line to be bypassed than in a normal case. In such a case, by setting the threshold value T to a large value, even if it is normally determined that the state is congested,
It is conceivable not to intentionally consider the congestion state to be a congestion state. Alternatively, as another example, when inspecting a specific line, or when inspecting the capability of a specific switching device, there is a case in which inspection or investigation is desired to be performed without intentionally evacuating a cell. In such a case, by setting the threshold value T to a large value or to the maximum value, it is possible to reduce the chances of determining a congestion state. By setting the threshold value T to a maximum value, that is, by setting the threshold value T = the maximum storage number that can be stored in the common buffer memory, the cells are not saved until the common buffer memory is full. be able to.

Embodiment 4 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a flowchart showing a procedure of the congestion determination circuit 20 of the cell switching apparatus according to one embodiment of the present invention. Cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6) and second embodiment described above
The same reference numerals are given to the same or corresponding parts as those of the cell switching device (FIG. 1, FIG. 4, FIG. 6, FIG. 9) of FIG.

FIG. 11 explains the operation of the congestion determination circuit 20. The congestion determination circuit 20 monitors the number of cells stored in the common buffer memory 11 inside the common buffer type switch 9 by the switch internal monitor 21, and compares the number with a preset threshold to congest. Determine the status.

If the accumulated number fluctuates frequently around the set threshold value, the congestion state determination becomes unstable. Therefore, the threshold value for judging the congestion state and the threshold value for judging the non-congestion state are set. Is provided. At this time, 2
By setting one threshold value and providing hysteresis, a stable congestion determination can be obtained.

Embodiment 5 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a detailed block diagram of the congestion determination circuit 20 of the cell switching apparatus according to one embodiment of the present invention, and FIG. 13 is a flowchart showing the operation procedure. Same or equivalent to the cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6) and the cell switching device according to the second embodiment (FIGS. 1, 4, 6, and 9). The same reference numerals are given to the portions, and the description is omitted.

In FIG. 12, reference numeral 20 denotes a congestion determination circuit, reference numeral 21 denotes a switch internal monitor for notifying the number of cells stored in the switch from the common buffer type switch 9, and reference numeral 31 denotes a congestion state to the cell evacuation circuit 22. This is a congestion determination output line. 32 to 34 are blocks inside the congestion determination circuit 20; 32 is a history storage pool capable of storing the past number of accumulated cells up to k cell slots before;
Performs a predetermined calculation from the information of the history storage pool,
The history calculation circuit 34 for calculating the cell storage index is a comparison circuit for comparing the cell storage index output from the history calculation circuit with a preset threshold value.

FIG. 13 illustrates the operation of the congestion determination circuit 20. For more stable and reliable determination, the feature is that a history of the past several slots is left, and a congestion state is determined when a predetermined criterion is exceeded. The congestion determination circuit 20 includes a switch internal monitor 21.
Monitors the number of cells stored in the common buffer memory 11 inside the common buffer type switch 9. In the initial state, a congestion determination threshold value T and the number of history storage slots k are set.

The history storage pool 32 holds the number of accumulated cells in the past k cell slots. This is F
It can be implemented with an IFO-based memory. Past k
Using the information of the cell slot, the history calculation circuit 33 calculates the cell accumulation index.

Here, there are various methods for the history calculation circuit 33 to calculate the cell accumulation index. For example, there is a method of simply averaging the past k cell slots. The larger the value of k, the more stable the determination. In addition, a rapid increase in the number of stored cells is taken into consideration, that is, a method of weighting the rate of increase in the number of stored cells is also conceivable. Furthermore, the congestion state may be determined by another method when the pattern of increase in the number of cells stored in the past several cell slots matches a preset pattern.
Alternatively, there is a method in which the number of stored cells in the k-cell slot is compared with a preset reference value of the number of stored cells, and a cell storage index is calculated based on how many of the k cells exceed the reference value.

The calculated cell accumulation index is calculated by the comparison circuit 34.
Is compared with a preset threshold value T to determine the congestion state. The congestion state is notified to the cell save circuit 22 by the congestion determination output line 31.

Embodiment 6 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a block diagram of a cell switching device according to an embodiment of the present invention, and FIG. 15 is a flowchart showing an operation procedure of the cell save circuit 22. Cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6),
The same or corresponding parts as those in the cell switching apparatus according to the second embodiment (FIGS. 1, 4, 6, and 9) are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 14, cells 25 _{1 to} 25 _{n transfer} cells input from input lines 11 ₁ to 1 _n to bypass links 27 _{1 to} 27 _n to be described later or to a cell in accordance with a switching instruction of the save buffer control circuits 24 _{1 to} 24 _n. Buffers 23 ₁ to 23
_This is an evacuation input selector assigned to _n . 26 ₁ to 2
6 _n according switching instruction saving buffer control circuit 24 ₁ to 24 _n, the bypass link 27 ₁ ~ 27 _n below
Or select either of the save buffer 23 ₁ ~ 23 _n, a retraction output selector connected to the switch input lines 3 ₁ to 3 _n.

Next, the operation will be described. Here, FIG. 15 is described with reference to a flowchart of operation of the cell save circuit 22 ₁ through 22 _n. Cell evacuation circuits 22 _{1 to} 22
_n monitors the presence / absence of congestion determination by the congestion determination circuit 20 through the congestion determination output line 31. If the state is congested, the evacuation input selector 25 ₁
To 25 _n are incoming lines ₁ 1 to 1 _n the save buffer 23 ₁ ~ 23 _n in accordance with an instruction of the save buffer control circuit 24 ₁ to 24 _n
Connected to, saving the entered cell buffer 23 ₁ ~ 23 _n
On hold.

On the other hand, if the state is not congestion, the cell save circuits 22 _{1 to} 22 _n can output cells to the common buffer type switch 9. Therefore, the output is performed from the FIFO rule, that is, the cell that arrives first in time. If, when I cell is accumulated inside the saving buffer 23 ₁ ~ 23 _n, for outputting from the cell, the save input selector 25 ₁ to 25 _n are incoming lines in accordance with an instruction of the save buffer control circuit 24 ₁ to 24 _n 1 ₁ to 1 _n and the connection to the saving buffer 23 ₁ ~ 23 _n, and at the same time held the inputted cell to the save buffer 23 ₁ ~ 23 _n, output selector 26 ₁ ~ 26 _n for saving, like saving buffer control circuit Evacuation buffers 23 ₁ to 23 according to the instructions of 24 _{1 to} 24 _n
The _n connected to the switch input lines 3 ₁ to 3 _n, and outputs the cell from the save buffer 23 ₁ ~ 23 _n. If the interior cells of the saving buffer 23 ₁ ~ 23 _n are not accumulated, the save output selector 26 ₁ ~ 26 _n and retraction input selector 25 ₁ to 25 _n, the reverse connection mode, That is connected to the bypass link 27 ₁ ~ 27 _n side, to output the input cell direct switch input lines 3 to ₁ to 3 _n.

Embodiment 7 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a block diagram of a cell switching device according to an embodiment of the present invention, and FIG. 17 is a flowchart showing an operation procedure of the cell save circuit 22. Cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6),
The same or corresponding parts as those in the cell switching apparatus according to the second embodiment (FIGS. 1, 4, 6, and 9) are denoted by the same reference numerals, and description thereof is omitted.

[0167] In FIG. 16, 25 ₁ to 25 _n is retracted according to switching instruction buffer control circuit 24 ₁ to 24 _n, the incoming line ₁ 1 to 1 _n below the cell inputted from the bypass link 27 ₁ ~ 27 _n or retracted Buffers 23 ₁ to 23
_This is an evacuation input selector assigned to _n . 26 ₁ to 2
6 _n according switching instruction saving buffer control circuit 24 ₁ to 24 _n, the bypass link 27 ₁ ~ 27 _n below
Or select either of the save buffer 23 ₁ ~ 23 _n, a retraction output selector connected to the switch input lines 3 ₁ to 3 _n. 28 ₁ ~ 28 _n reads a code or the like that represents the priority of a delay or the like that is attached in the header of the input cell is the priority cell determination circuit for notifying the priority to saving buffer control circuit 24 ₁ to 24 _n .

Next, the operation will be described. FIG. 17 illustrates the operation of the cell evacuation circuits 22 _{1 to} 22 _n using a flowchart. In the present embodiment, the priority regarding cell delay is set to two classes, and is hereinafter referred to as a delay sensitive cell and a delay insensitive cell. However, this priority may be two or more classes.

The priority cell discriminating circuits 28 _{1 to} 28 _n monitor the header of the arriving cell and detect the priority related to the delay or the like given in the header or the like of the cell. The priority may be given directly in the header in the form of a bit, or may be determined by VPI / VCI (channel identifier or the like), but one cell always belongs to one of the priority classes. .

When the arriving cells identified by the priority cell discriminating circuits 28 _{1 to} 28 _n are delay sensitive cells, even if the congestion judging circuit 20 detects the congestion state, the cell evacuation circuits 22 _{1 to} 22 _n Outputs the arrival cell as it is.

Conversely, when the priority cell discriminating circuits 28 _{1 to} 28 _n detect a delay insensitive cell, the cell saving circuits 22 ₁ to 28 _n
22 _n is processed differently depending on whether or not the congestion determination is performed by the congestion determination circuit 20. If it is in the congestion state, the evacuation input selectors 25 _{1 to} 25 _{n change the} input lines 11 to _{1 in} accordance with the instructions of the evacuation buffer control circuits 24 _{1 to} 24 _n.
Connect the _n in the save buffer 23 ₁ ~ 23 _n, thereby holding the inputted cell to the save buffer 23 ₁ ~ 23 _n.

On the other hand, if the state is not congestion, the cell save circuits 22 _{1 to} 22 _n can output cells to the common buffer type switch 9. Therefore, the output is performed from the FIFO rule, that is, the cell that arrives first in time. If, when I cell is accumulated inside the saving buffer 23 ₁ ~ 23 _n, for outputting from the cell, the save input selector 25 ₁ to 25 _n are incoming lines in accordance with an instruction of the save buffer control circuit 24 ₁ to 24 _n 1 ₁ to 1 _n and the connection to the saving buffer 23 ₁ ~ 23 _n, and at the same time held the inputted cell to the save buffer 23 ₁ ~ 23 _n, output selector 26 ₁ ~ 26 _n for saving, like saving buffer control circuit Evacuation buffers 23 ₁ to 2 according to the instructions of 24 _{1 to} 24 _n
3 _n was connected to the switch input lines 3 ₁ to 3 _n, and outputs the cell from the save buffer 23 ₁ ~ 23 _n. If the interior cells of the saving buffer 23 ₁ ~ 23 _n are not accumulated, the save output selector 26 ₁ ~ 26 _n and retraction input selector 25 ₁ to 25 _n, the reverse connection mode, That is connected to the bypass link 27 ₁ ~ 27 _n side, to output the input cell direct switch input lines 3 to ₁ to 3 _n.

Embodiment 8 FIG. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram of a cell switching device according to one embodiment of the present invention. Cell switching device according to the first embodiment (FIGS. 1, 2, 4, and 6),
The same or corresponding parts as those in the cell switching apparatus according to the second embodiment (FIGS. 1, 4, 6, and 9) are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 18, the cells 29 _{1 to} 29 _n multiplex the cells notifying the congestion when the congestion state is detected, that is, the control cells, to the switch output lines 4 ₁ to 4 _n according to the instruction of the congestion determination circuit 20. This is a control cell multiplexing circuit. 30 ₁ to 30 _n are cell evacuation circuits 22 _{1 to} 22 _n
n corresponding to the control cell multiplexing circuits 29 ₁ to 29 ₁ .
29 separates the control cell from the output of _n, is the control information in the control cell demultiplexing circuit which informs the cell save circuit 22 ₁ through 22 _n.

Next, the operation will be described. When congestion detection circuit 20 detects a congestion state of the shared buffer type switch 9, notifies the control cell multiplexing circuit 29 ₁ ~ 29 _n, wherein the control cell format predetermined is produced. Control cells in 4 ₁ to 4 _n switch output lines are multiplexed at the timing of such idle cells arrive at the control cell separation circuit 30 ₁ to 30 _n. In the control cell separation circuit 30 ₁ to 30 _n, extracts only the control cells, the other data is sent to the outgoing line 2 ₁ to 2 _n. On the other hand, the extracted control cell is interpreted, when congestion is determined, it is notified to the cell save circuit 22 ₁ through 22 _n.

FIG. 19 is a diagram showing an implementation of the cell switching apparatus shown in FIG. The control cell multiplexing circuit is mounted on the common buffer type switch substrate 100. The congestion determination circuit 20 connects the congestion determination output line 31 to the control cell multiplexing circuits 29 _{1 to} 29 _n . The control cell demultiplexing circuit 30 ₁ to 30 _n are respectively provided on the interface board. 19, the congestion determination output line 31 from the congestion determination circuit 20 exists only inside the common buffer type switch substrate 100, and the congestion determination output line 31 as shown in FIG. Need not be connected to each interface board. Therefore, the number of signal lines between the interface board and the common buffer type switch board can be reduced.

Embodiment 9 FIG. In Examples 1 to 8,
Although a single cell switching device is shown, this device may be connected in a link and connected in multiple stages.

Embodiment 10 FIG. Further, in the first to eighth embodiments, a single cell exchange device is shown, but this device may be connected in a grid and connected in a matrix.

Embodiment 11 FIG. Examples 1 and 2
Then, the common buffer type switch 9 sets the destination information as
Although an example in which the header portion of the cell is referred to directly is shown, a dedicated tag indicating the destination is added before or after the cell at the preceding stage of the common buffer type switch 9, and the destination information is detected by referring to this. Is also good. The destination information does not directly indicate the destination, but may be coded.

Embodiment 12 FIG. Further, in the embodiment 1-8, but one cell has been described a case where output to only one destination output line 2 ₁ to 2 _m, the specification of how the destination, a plurality of outgoing lines 2 ₁ - It is also possible to set to output to 2 _m , and a broadcast function may be provided.

Embodiment 13 FIG. Examples 1 and 2
In the above, the common buffer type switch 9 processes one cell collectively. However, the cell exchange may be performed using circuits of different speeds by separating a header portion and a data portion from each other due to the structure of the cell.

Embodiment 14 FIG. In addition, in the embodiment 1-8, although the speed of the incoming 1 ₁ to 1 _n of the speed and the output line 2 ₁ to 2 _m was the same, the traffic focused if increase the speed of the outgoing 2 ₁ to 2 _m are possible, it is also possible to increase the speed of the incoming 1 ₁ to 1 _n the contrary. In addition, when the cell switching device is connected by link, by setting the speed between the stages higher than the speed of the incoming line, the cell loss rate between the stages can be reduced.

Embodiment 15 FIG. In the first to eighth embodiments, the priority class for discarding a cell is set to a single. However, a priority class is defined for each cell or for each virtual path or virtual channel, and by discarding unimportant cells first. , The effect on the terminal can be minimized. Also, discard priority may be defined in burst units.

Embodiment 16 FIG. Further, in the first to eighth embodiments, the operation speed is not restricted. However, when the operation speed is restricted, the former and the latter stages of the cell switching device include:
A serial / parallel converter and a parallel / serial converter may be provided to reduce the operating speed as a parallel signal.

Embodiment 17 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 20 shows an embodiment of the present invention. In FIG. 20, reference numerals ₁₁ to 1 _{n denote} ATs each including a header portion including an outgoing line number as destination information and a data portion.
N number of incoming lines to enter the M cell, the 2 ₁ to 2 _m are output in response to a destination on which cell is designated by the header portion m
Outgoing book. 53 is a cell switch, and 53x,
It is duplicated as indicated by 53y. These suffixes x and y are used to distinguish between two doubled components, and so on. Cell switch 53x
Is the common buffer type switch 9x and the congestion determination circuit 20
x. Shared buffer switch 9x switch output lines 4x ₁ cells based on the destination information of the cell entered
Distributed to ～4X _m, also, the switch output line 4x therein
A buffer memory shared and used between _{1 to 4} × _m is provided, and cells requiring a wait are written into the buffer memory to exchange cells.

The congestion determination circuit 20x is a common buffer type
Whether the state of the buffer of switch 9x is more congested
Determine whether or not. 21x is a common buffer type switch 9
x is the switch internal monitor that outputs
Monitors the buffer memory of the shape switch 9x and contaminates it.
Notify the determination circuit 20x. Same for cell switch 53y
It has a configuration. 3₁ ~ 3_n Is incoming line 1₁ ~ 1_n Compatible with
A common buffer type switch for input cells
Switch input line to transfer to 9x, 9y, 4x₁ ~ 4x_m 
And 4y ₁ ~ 4y_m Is outgoing line 2₁ ~ 2_m Provided corresponding to
And the common buffer type switches 9x and 9y output cells.
Switch output line. 31x and 31y are respectively
Congestion determination circuits 20x and 20y output determination results
This is a congestion determination output line. Congestion determination output line 31
x and 31y are connected to an OR circuit 41,
The output of the signal 41 is transmitted via the congestion determination output line 31 to a
To the save circuit.

22 _{1 to} 22 _n are provided corresponding to the input lines 1 ₁ to 1 _n . When the OR circuit 41 transmits congestion, that is, when at least one of the cell switch 53x and the cell switch 53y becomes congested, Incoming line 1 ₁ to 1 _n
Is a cell evacuation circuit that accumulates cells input to the common buffer type switch and suppresses input of cells to the common buffer type switch. 23 _1-23
n each provided inside the cell save circuit 22 ₁ through 22 _n, a save buffer that actually store the input cell,
24 ₁ to 24 _n are provided in the respective save circuit 22 ₁ through 22 _n, a save buffer control for controlling the reading and writing of cells in the saving buffer 23 ₁ ~ 23 _n.
40 ₁ to 40 _m is provided on the output line 2 ₁ to 2 _m corresponds, the cell from the two switch output lines respectively paired at the switch output lines 4x ₁ ~4x _m and 4y ₁ ~4y _m selects one which is the exit-side selection circuit that outputs to the outgoing line 2 ₁ to 2 _m. Reference numeral 42 denotes a switching instruction signal for giving a switching instruction to the output side selection circuit.

The common buffer type switch 9 is, for example,
This is the same as that shown in FIG.

FIG. 21 shows output selector circuit 40 shown in FIG.
It is a diagram showing in detail an embodiment of ₁ to 40 _m.
4x, 4y, 4x ₁ of each 2,42 Figure 1 ～4X
_m, corresponding to _{4y 1 ~4y m, 2 1 ~2} m, 42. 4
A switching timing detection circuit 4 generates a switching signal 45 from the switch output lines 4x and 4y and the switching instruction signal. Reference numeral 43 denotes a selector for actually selecting one of the switch output lines 4x and 4y based on the switching signal 45 and switching the output line 2 to output the cell.

Next, the operation will be described. Here, the cells to be described are of fixed length and arrive as random or burst traffic, and the cell input phase is adjusted before being input to the input lines ₁₁ to 1 _n , and the cell input from all the input lines is It is assumed that they are supplied in the same phase. The operation of the common buffer type switch 9 is the same as that of the first embodiment.

The switch output lines 3 _{1 to} 3 _n similarly input cells to the cell switches 53x and 53y. The cell switches 53x and 53y are connected to the common buffer type switch 9 described above.
The cell is exchanged by the operation of
x ₁ ~4x _m, and outputs the cell to 4y ₁ ~4y _m.

The operation of the congestion determination circuit 20 is the same as that of the first embodiment. The operation of the cell save circuit 22 is the same as that of the first embodiment.

Next, the operation of the output side selection circuits 40 ₁ to 40 _m will be described based on the output side selection circuit 40 of FIG. For example, it is assumed that the switch output line 4x is selected by the selector 43, and the switching instruction signal 42 instructs the selection of the switch output line 4y from this state. Then, in the switching timing detection circuit 44, the switch output line 4
At the timing when idle cells appear in both x and 4y, the selector 43 is instructed by the switching signal 45 to select the switch output line 4y. In response, the selector 43 selects the switch output line 4y and outputs the cell of the switch output line 4y to the output line 2.

The switching instruction signal 42 outputs an instruction for simultaneously switching the switch output lines to all the output side selection circuits.
Since the switch output line is switched at the timing when the idle cell appears in both x and 4y, the output side selection circuit executes the switching at different timings. As described above, when the switch output lines are switched at the individual timings and the m output side selection circuits complete the switching of the switch output lines, the switching from the cell switch 53x to the cell switch 53y is completed.

Next, an example of the instantaneous switching of the duplicated cell switches will be described with reference to a timing chart. Here, for simplicity, n and m in FIG.
The time for the cell switch to process the input cell is defined as one cell time. It is also assumed that the cell switches 53x and 53y do not accumulate cells in the common buffer type switch in the initial state.

(A), (b), (c), and (c) shown in FIG.
(D), (e), (f), (g), (h), and (i) show reference points in the timing chart of FIG. The destination numbers 1 to 3 correspond to the switch output lines 4x ₁ to
4x correspond to ₃ and 4y ₁ ~4y _3, i denotes an idle cell. An idle cell is a cell conforming to the ATM defined by the international standard, and is a fixed pattern cell transmitted for speed adjustment when there is no data to be transmitted.

Now, FIGS. 23 (a), (b) and (c) shown in FIG.
, The cell switch 53x outputs (d), (e),
(F), and the cell switch 53y outputs (g)
Assume that the outputs shown in (h) and (i) are output. Now, the switch output lines 4x ₁ ~4x _m is selected as the working system,
Consider the case of switching the switch output line 4y ₁ ~4y _m to the working system from this state.

[0198] time to switch from the switch output line 4x ₁ to the switch output line 4y _1, is shown in FIG. 23 t = A
In this case, cell 1 overlaps and cell 2 is lost. However, when the time is switched to time t = B, no cell overlap or loss occurs. This is because when an idle cell is output to a certain switch output line, there is no cell addressed to that switch output line in the common buffer type switch.

The input phases of the cells are adjusted before being input to the input line, and the input cells from all input lines are supplied with the same phase. The same applies to the cells that have passed through the cell save circuit, and the cells input to the switch input line are input to the cell switch with the same phase. In addition, the cell switch requires at least one cell slot to exchange cells. Under such conditions, the cell switch of the switch output addressed in the cell switch is not present when idle cells are output simultaneously to switch output lines 4x _1, 4y _1. For example, FIG.
As shown in (b), when two cells (cell numbers 1 and 2) are input with respect to destination number 1 and the next cell with destination number 1 is the fourth cell slot, Is output in the third cell slot on the output side in either case of being output in the order of cell numbers 1 and 2 by the cell switch 53x, or in the case of being processed in the order of cell numbers 2 and 1 by the cell switch 53y. , An idle cell is generated. Thus, when the idle cells in both the switch output lines 4x ₁ and 4y ₁ occurs, it is guaranteed that there is no cell to be output to the switch output line.

The same applies to the switch output lines 4x ₂ , 4y ₂ and the switch output lines 4x ₃ , 4y ₃ .
Switching to t = C does not cause cell duplication or loss. For switch output line 4x _2, 4y _2, idle cells are generated in the fifth cell slot th output side. Since the cells of cell numbers 5, 7, and 8 have already been processed by the fourth cell slot, and there is no cell output to the switch output line in the fifth cell slot, switching is performed at time t = D. Execute. In the case of the switch output lines 4x ₃ and 4y ₃ , idle cells are generated in the fourth cell slot on the output side, and all cells are output by the third cell slot.
Perform switching at C. Switch output line 4y ₁
The opposite of the switching from ～4Y _m to the switch output lines 4x ₁ ~4x _m.

As described above, when the switching instruction is transmitted by the switching instruction signal 42, the output side selection circuit 40 ₁
In the range of に 40 _m , by performing switching at the timing when idle cells appear on both of the connected switch output lines, it is possible to perform instantaneous switching of the cell switch.

Next, FIG. 24 is a diagram showing an example of a mounting form of the cell switching device shown in FIG. In FIG.
100x and 100y are common buffer type switches 9x,
9y and a common buffer type switch board on which congestion determination circuits 20x and 200y are mounted. 200 ₁ to 200 _n
Is an interface board. Each interface board is provided corresponding to one input line and one output line, and has an interface circuit for connecting the pair of input and output lines to the common buffer type switches 9x and 9y. . For example, when the incoming and outgoing lines are constituted by optical fibers, a photoelectric conversion circuit and an electro-optical conversion circuit are mounted. Further, an interface circuit for synchronizing and performing an error check is mounted. Further, the above-described cell evacuation circuit is provided on the incoming line side. Further, an output side selection circuit is provided on the output line side.
Each interface board and the common buffer type switch board are connected by a switch input line and a switch output line. The congestion judgment output lines 31x and 31y from the congestion judgment circuits 20x and 20y are connected from the common buffer type switch boards 100x and 100y to the cell save circuits of the respective interface boards 200 ₁ to 200 _n .

Embodiment 18 FIG. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 25 is a block diagram showing the configuration of the cell switching device according to this embodiment. In this figure, the same reference numerals as those in FIG. 20 denote the same or corresponding parts as in FIG. In FIG. 25, the cell switches 531x, 5
31y is constituted by the common buffer type switch 9.
The common buffer type switch 9 is configured similarly to the first embodiment. Cell switch 531X, the switch internal monitor for output 531y is connected to a congestion judging circuit 201, congestion judgment output line 31 for outputting congestion determination circuit is connected to the cell save circuit 22 ₁ through 22 _n. Cell saving circuits 22 _{1 to} 22 _n , common buffer type switches 9x and 9
y operates similarly to the first embodiment. Cell switch 531
x, 531y, the common buffer type switches 9x, 9y are the switch internal monitors 21x,
21y is output. This switch internal monitor 21x, 2
The congestion determination circuit 201 selects the larger one of the numbers to be notified by 1y, and makes the congestion determination. The congestion determination procedure is the same as that described in the seventeenth embodiment. Therefore, if either one of the common buffer type switches 9x and 9y is in the congestion state, the congestion is determined. Egress selection circuit 40 ₁ to 40 _m is the same operation as in Example 17. In this way, the instantaneous switching of the cell switch can be performed by the same switching method as in the seventeenth embodiment.

Embodiment 19 FIG. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 26 is a block diagram showing the configuration of the cell switching device according to this embodiment. In FIG.
1 ₁ to 1 _n is the incoming lines of the n inputting the ATM cell, 2
₁ to 2 _m is a line out of the m pieces of the cell is output. Reference numerals 22 _{1 to} 22 _{n denote} cell evacuation circuits, and evacuation buffers 23 ₁ to 23 _n and evacuation buffer controls 24 _{1 to} 24 _{n, respectively.}
It consists of. 31x and 31y are congestion determination output lines connected to the OR circuit 41, and the outputs are input to the save buffer control. Reference numeral 42 denotes a switching instruction signal.
3 ₁ to 3 _n is a switch input line cells save circuit 22 ₁ through 22 _n outputs the cell, is connected to the inlet side selector. 47 _{1 to} 47 _n are input-side selectors which switch cells received from the switch input lines to the cell switches 532x, 53n.
Switching means for inputting to either one of 2y.

Reference numeral 532 denotes a cell switch.
Is duplicated in the same manner. Taking the cell switch 532x as an example, the cell switch 532x includes a common buffer type switch 92x and a congestion determination circuit 20x. The congestion determination circuit 20x monitors the switch internal monitor 21x output from the common buffer type switch 92x in the same manner as described in the first embodiment. The cell switch 532y has the same configuration. Also, 50x ₁ ~50x _m, 50
y ₁ ~50y _m is shared buffer switch 92x, 92
the presence or absence of cells in the y is the cell presence notifying unit that notifies the control circuit to be described later by the switch output lines, 51x ₁ ~51x
_m, 51y _{1 ~51y m} denotes an output enable signal line for providing the control circuit is shared buffer switch 92x, the output permission of the cells in the switch output line units 92y.

Reference numerals 4x _{1 to} 4x _m and 4y _{1 to} 4y _m are switch output lines from which the common buffer switches 92x and 92y output cells as in the seventeenth embodiment. 402 ₁ -40
2 _m, respectively, outgoing line at the outlet side selection circuit provided 2 ₁ to 2 _m corresponds to select one of the switch output lines and the switch output line of the cell switch 532y of the cell switch 532X. Reference numeral 48 denotes a control circuit for duplex switching control.
2 ₁ to 52 _m is a switching permission signal line for providing a switching permission egress selection circuit 402 ₁ to 402 _m.

FIG. 27 shows an example of the configuration of the common buffer type switch in this embodiment in detail. Here, those having the same numbers as those in FIG. 2 are the same as or correspond to those in FIG. 152 is an example of a buffer control circuit in the common buffer type switch 92. 182 _{1 to} 182
_m is an address queue; 49 ₁ to 49 _m are queue monitors for monitoring the address queues 182 _{1 to} 182 _m ;
50 ₁ to 50 _m is the cell presence notifying means for outputting a storage state of the output line by the cell. 51 ₁ to 51 _m is an output enable signal line for providing output permission for the cell in the shared buffer type switch 92. 192 is a read buffer selection circuit.
FIG. 28 is a diagram illustrating in detail one configuration example of the output side selection circuit 402 in the present embodiment. The switching timing detection circuit 442 generates a switching signal 45 from the switching instruction signal 42 and the switching permission signal 52, and
Switch.

Next, the operation will be described. First, the operation of the common buffer type switch will be described. The common buffer type switch operates basically in the same manner as described in the first embodiment. The difference is, output enable signal line 51 _1-51 address read from the address queue 182 ₁ ~182 _m for switch output lines output permission is not given by _m is stopped, that the cell is not output And the queue monitor monitors the address queue,
It is that this result is output by the cell presence notifying means 50 ₁ to 50 _m. The congestion determination circuit 20 operates in the same manner as described in the first embodiment.

[0209] An example in which the cell switch 532x is initially the active system will be described below. In this case, the inlet side selector 47 _1-47 in _n switch input lines 3 ₁ to 3 _n
Is output to the cell switch 532x. The output enable signal lines 51x _{1 to} 51x are connected to the cell switches 532x.
x output permission is given by _m, and outputs the cell to the switch output line 4x ₁ ~4x _m. Outgoing side selection circuit 402
₁ to 402 _m in the switch output lines 4x ₁ ~4x _m are selected, the cell switch output lines 4x ₁ ~4x _m is outputted to the outgoing line 2 ₁ to 2 _n. When the common buffer type switch 92x is congested, the congestion determination output line 31x output from the congestion determination circuit 20x outputs an OR signal.
Congestion of the shared buffer type switch 92x is notified to the cell save circuit 22 ₁ through 22 _n via a circuit 41, the cell is stored in the cell save circuit in the same operation as described in Example 1. By the way, when the cell switch 532y is a working system, cells arriving in the incoming lines ₁ 1 ~1 _n is the cell switch 5
32y, the common buffer type switch 92y is congested, and the congestion determination output line 31y is connected to the common buffer type switch 92y via the OR circuit 41.
Congestion is notified to the cell save circuit 22 ₁ through 22 _n.

[0210] Here, it is assumed that an instruction has been input by the switching instruction signal 42 to change the active system to the cell switch 532y. Then, the input-side selectors 47 _{1 to} 47 _n output the cell to the cell switch 532y, and the cell switch 53
No output is made to 2x. The output permission signal line 51y
_{1 ~51y m} prohibits output of the cell, the cell switch 53
The cell input to 2y is a common buffer type switch 92y.
Accumulates inside. On the other hand, the cell switch 532x keeps outputting the cells stored therein. The queue monitor 49 ₁ with for example the output of the cell to the switch output line 4x ₁ ends the shared buffer switch 92x
Control circuit by the cell presence notifying unit 50x ₁ this 48
Tell Giving the switching permission by the switching permission signal line to the control circuit 48 in the exit-side selection circuit 402 _1, also shared buffer type switch 9 by the output enable signal line 51 y ₁
To enable the output of the cell to the switch output line 4y ₁ to 2y. By the outgoing side selection circuit 402 ₁ in the switching permission was received from the control circuit 48, since the switches to select the switch output line 4y _1, cell switch output line 4y ₁ is output to the output line 2 _1. Such operations, when performed for all the outgoing lines outgoing 2 ₁ to 2 m, the switching system is terminated. This enables instantaneous interruption switching of the cell switch. When the cell switch 532y is in the active system, the opposite operation is performed at the time of switching.

Embodiment 20 FIG. Next, this embodiment will be described with reference to the drawings. FIG. 29 is a block diagram showing the configuration of the cell switching device according to this embodiment. In this figure, the same numbers as those in FIG. 26 indicate the same or corresponding parts. In the nineteenth embodiment, the congestion determination circuit is provided inside the cell switch, and the OR of the congestion determination output lines output from each cell switch is obtained by the OR circuit. In this embodiment, the congestion determination circuit 201 is provided outside the cell switch. Yes, the switch internal monitors 21x and 21y output from the cell switches 533x and 533y are connected. The congestion determination output line 31 output from the congestion determination circuit is connected to the cell save circuit.

Next, the operation will be described. The operation of the common buffer type switch 92 is the same as that described in the third embodiment. The congestion determination circuit includes a switch internal monitor 21x,
21y is connected, but the larger number is used for congestion determination. The procedure of the congestion determination is the same as that described in the first embodiment. For example, when the cell switch 533x is used in the active system, when the common buffer type switch 92x is turned off, the switch internal monitor 2
Congestion determination circuit 201 for increasing the number of cells storing 1x
Tell The congestion determination circuit makes a congestion determination based on the number of cells, and the congestion determination output line 31 transmits the congestion of the common buffer type switch 92x to the cell save circuit. The operation of the cell save circuit is the same as that described in the first embodiment. Further, the switching operation is performed in the same manner as in the nineteenth embodiment, so that instantaneous interruption switching can be performed.

Embodiment 21 FIG. Next, this embodiment will be described with reference to the drawings. FIG. 30 is a block diagram showing the configuration of the cell switching device according to this embodiment. In this figure, the same numbers as those in FIG. 26 indicate the same or corresponding parts. In FIG. 30, the cell save circuits 224x _{1 to} 224x _n and 224x
y _{1 ~224y n} is cell switch 532X, provided on 532y corresponding, congestion judgment output line 31x of each cell switch output, 31y each cell save circuit 224x ₁ ~224x _n and 224y ₁ ~224y
_Entered in _n . Cell save circuit 224x ₁ ~224x _n
Are each composed of saving buffer 23x ₁ ~23x _n and retraction buffer control 244x ₁ ~244x _n is. Cell save circuit 224y ₁ ~224y _n is similar. 55x
_{1 ~55x n,} 55y _{1 ~55y n} is an evacuation circuit cell presence notifying means. Entry side selector 47 ₁ to 47 _n are provided in the stage before the cell save circuit. Reference numeral 484 denotes a control circuit.

Next, the operation will be described. Inlet selector 47 ₁
To 47 _n , output side selection circuit 402 _{1 to} 402 m Are the same as those described in the nineteenth embodiment.
The operations of x and 532y are the same as those described in the nineteenth embodiment. Cell save circuit 224x ₁ ~224x _n and 224
y ₁ ~224y _n is the substantially the same operation as in Example 19, save circuit cell presence notification unit 55x ₁ to 5 for notifying whether the cell in the saving buffer is stored in the external
5x _n, has a 55y ₁ ~55y _n. Now, assuming that the cell switch 532x is the active system, the input lines ₁₁ to
The cells input to 1 _n are input to the cell save circuits 224 x _{1 to} 224 x _n by the input side selectors 47 _{1 to} 47 _n . Common buffer type switch 9 of cell switch 532x
If 2x is congested, the cells input to the cell evacuation circuit wait temporarily in the cell evacuation circuit; otherwise, the switch input line 3x ₁ of the cell switch 532x.
It is output to the ~3x _n. The control circuit 484 is given the output permission by the output permission signal 51x ₁ ~51x _m in cell switch 532X, cell switch 532X outputs distributes the cells by destination switch output lines 4x ₁ ~4x _m. Exit side cell selection circuit 402 ₁ to 402 _m in the switch output lines 4x ₁ ~4x _m are selected, respectively, outgoing line 2
Is output to ₁ to 2 _m.

Next, from this state, the cell switch 532y
The switching operation will be described by taking as an example a case where an instruction by the switching instruction signal 42 is input so as to switch to the active system. Incoming selectors 47 _{1 to} 47 _n have incoming lines 1 ₁ to 1
_The cells input to _n are stored in cell saving circuits 224y _{1 to} 224
switch to enter the y _n. Cell save circuit 224
y ₁ ~224y _n operations cell save circuit 224 x ₁ to 2
Is the same as the 24x _n. The cell switch 532y temporarily stores the input cells in a buffer memory in the common buffer type switch 92y until output permission is given from the control circuit 484.

On the other hand, as long as there is a valid cell in the common buffer type switch 92x, the cell switch 532x outputs this. Then the control circuit 484, that there is no cell to cell save circuit 224x in _{1 ~224x n} confirmed by alert save circuit cell presence notification unit 55x ₁ ~55x _n, and, for example, the cells to the switch output line 4x ₁ When the output is notified by the cell presence notifying unit 50x ₁ the completion, giving the switching permission by the switching permission signal lines 52 ₁ to egress selection circuit 402 _1, also shared buffer type switch by the output enable signal line 51 y ₁ to enable the output of the cell to the switch output line 4y ₁ to 92y. Egress selection circuit 402 ₁ is to output the transmitted switching permission by the switching permission signal line 52x ₁ the cell selects the switch output line 4y ₁ to OUT line 2 _1. When system switching is performed for all switch output lines, the switching ends. This enables instantaneous interruption switching. When the active system is switched from the cell switch 532y to 532x, the opposite operation is performed.

Embodiment 22 FIG. In the nineteenth and twentieth embodiments, the switching permission signal from the control circuit is used to generate the switching signal 45 in the output side selection circuit. May be used. For example, as shown in the common buffer type switch 95 of FIG. 31, header change circuits 541 to 5 that change the header in response to the notification from the cell presence / absence notification unit.
4m is provided, and when there is no cell to output for a certain switch output line, a predetermined specific bit in the header area is set to "1". When the output side selection circuit receives this cell, it determines that all the cells have been output for the switch output line, and selects the switch output line of the opposite system. This enables instantaneous interruption switching.

Embodiment 23 FIG. In the twenty-second embodiment, the output selection circuit determines the end of cell output using the header area of the cell. However, this determination may be made using idle cells. That is, after the switching is instructed by the system switching instruction signal, it may be determined that all the cells destined for the switch output line to which the idle cell has been output have been output. This enables instantaneous interruption switching.

Embodiment 24 FIG. Examples 19, 20, 21, 2
In the embodiments 2 and 23, the control circuit is provided outside the cell switch, but may be provided inside the cell switch. FIG. 32 shows an example. In FIG. 32, the same numbers as those in FIG.
It indicates that they are the same or corresponding parts. 5
36x and 536y are cell switches which are common buffer type switches 92x and 92y and control circuits 486x and 48, respectively.
6y. Also, 406 _{1 to} 406 _m
Is an output side selection circuit. The operations of the common buffer type switch, the cell save circuit, the input side selector, and the congestion determination circuit are the same as those described in the fourth embodiment. Regarding the operation at the time of switching, the active system is switched from the cell switch 536x to the cell switch 5
The case of switching to 36y will be described as an example. When there is an instruction from the switching instruction signal 42 to set the cell switch 536y to the active system, the input side selectors 47 _{1 to} 47 _n
Cell switch 53 a cell switch input lines 3 ₁ to 3 _n is
Switch to input to 6y. Cell switch 536
The control circuit 486y in y is a common buffer type switch 92.
prohibits the cell output by the output enable signal line 51y ₁ ~51y _m against y, the shared buffer type switch 92y
Are stored in the common buffer switch 92y.

[0220] and, for example, cell presence or absence notification means 50x ₁
Control circuitry that shared buffer switch 92x has finished output of the cell to the switch output lines 4x ₁ by 486
y, the control circuit 486y outputs the output permission signal line 51
Allow the output of the cell to the switch output line 4y ₁ to shared buffer switch 92y by y _1, also permits the switch to switch output line 4y ₁ by the switching permission signal line 52y ₁ to egress selection circuit 406 _1. When such an operation is performed for all switch output lines, the switching is completed. When switching from the cell switch 536y to the cell switch 536x, the control circuit 486
The opposite operation is performed by the control of x. Thus, instantaneous interruption switching can be performed.

Embodiment 25 FIG. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 33 is a block diagram showing the configuration of the cell switching device according to this embodiment. In this figure, the same numbers as those in FIGS. 19 and 30 indicate the same or corresponding parts. Cell save circuit similar to FIG. 30 in FIG. 33 is 224x ₁ ~224x _n, 224y ₁ ~224y
_n is provided corresponding to the cell switches 53x and 53y, and the congestion determination output lines 31x and 31y output from the respective cell switches are respectively connected to the cell evacuation circuit 2
24x is inputted to the _{1 ~224x n} and 224y ₁ ~224y _n. In _{addition, 55x 1 ~55x n, 55y 1} ~55y
_n is an evacuation circuit cell presence notification unit, 407 _1-40
7 _m is an output side selection circuit.

Next, the operation will be described. Cell switch 53
The operations of x and 53y are the same as those described in the first embodiment.
Cell save circuit 224x ₁ ~224x _n and 224Y ₁
～224Y _n are the same as those described in Example 5. Now, it is assumed that the cell switch 53x is operating as an active system. Incoming lines ₁ 1 to 1 respectively arriving cell _n cell save circuit 224x ₁ ~224x _n, 224y ₁ ~22
Is input to both 4y _n. Cell save circuit 224x ₁ ~
Cell input to the cell switch 53x from 224 x _n are exchanged by the cell switches 53x, switch output lines 4x ₁
It is output to the ~4x _m. Cell evacuation circuits 224y _{1 to} 22
Switch output lines in the same manner cell input to 4y _n 4
It is output to y ₁ ~4y _m. Since now the cell switch 53x is working system, cells of the exit side selection circuit 407 ₁ ~407 _m in the switch output lines 4x ₁ ~4x _n is is selected, outputted respectively to the output line 2 ₁ to 2 _m.

In this state, it is assumed that an instruction to set the cell switch 53y to the active system is received from the switching instruction signal. In the exit side selection circuits 407 _{1 to} 407 _m , all the save circuit cell presence / absence notification means 55x _{1 to} 55x _n , 55y _{1 to} 55y
_n indicates that no cells are stored in the cell evacuation circuit, and at the timing when an idle cell is output to both of the switch output lines respectively connected to the output side selection circuits 407 _{1 to} 407 _m. Switch output line 4y _1-
Switch to select a cell in 4y _n. If the evacuation circuit cell presence / absence notifying means notifies that no cells are stored in the cell evacuation circuit, and the output side detects an idle cell on both of the switch output lines, the cell is stored in the cell evacuation circuit. This indicates that there is no cell and no cell exists in the common buffer type switch for the outgoing line. Therefore, even if switching is performed at that timing, no cell duplication or loss occurs. When the cell to the cell save circuit 224x ₁ ~224x _n and 224y ₁ ~224y _n not accumulated, the switch input lines 3x ₁ ~
Since the 3x _n and 3y ₁ ~3y _n cells are inputted similarly, for the reasons described in Example 17, both the switch output lines connected respectively to the outlet side selection circuit 407 ₁ ~407 _m If switching is performed in the output-side selection circuit at the timing when the idle cell is output, cell loss or duplication does not occur. When the active system is switched from the cell switch 53y to the cell switch 53x, the opposite operation is performed. Thus, instantaneous interruption switching can be performed.

Embodiment 26 FIG. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 34 is a block diagram showing the configuration of the cell switching device according to this embodiment. In this figure, the same numbers as those in FIG. 33 indicate the same or corresponding parts. 228x in FIG. 34 ₁ ~228x _n, 228
y ₁ ~228y _n each cell switch 53x, 53
This is a cell save circuit provided for y. The cell save circuits 228x _{1 to} 228x _n are respectively provided with save buffers 23x
_{1 ~23x n} and saving buffer control 248x ₁ ~248x
Consists of _n . Cell save circuit 228y ₁ ~228y _n
Has a similar configuration. 58x ₁ ~58x _n, 58y ₁ ~
58y _n each cell retraction circuit 228x ₁ ~228x
_n, a 228y ₁ ~228y _n is the number of cells in the save buffer notifying means for outputting, 56 ₁ ~ 56 _n is the notification from the corresponding retracted buffer cell number notifying means are stored in the cell save circuit based on This is a circuit for comparing the number of cells in the save buffer. 57 _{1 to} 57 _n are output lines for comparing the number of cells in the save buffer output from the circuit for comparing the number of cells in the save buffer. 59 the output of which is input to the outlet side selection circuit 408 ₁ ~408 _m an AND circuit connected to the cell number comparison output lines 56 ₁ ~ 56 _n within save buffer.

Next, the operation will be described. Cell switch 53
The operations of x and 53y are the same as those described in the first embodiment.
Cell save circuit 224x ₁ ~224x _n and 224Y ₁
～224Y _n cell save circuit 22 ₁ as described in Example 1
The substantially same operation as the 22 _n is the number of cells in the saving buffer notifying unit 58x ₁ ~58x _n, is that it has a 58y ₁ ~58y _n different. The number-of-cells-in-save-buffer comparing circuits 56 _{1 to} 56 _n receive the notification of the number of cells in the save-buffer-cell notifying unit of the corresponding cell save circuit, compare the numbers of cells in the save buffer, and store the results in the save buffer. output compared to the output line 57 ₁ to 57 _n number of cells. The logical product is obtained by the AND circuit 59, and the output side selection circuit 40
8 _{1 to} 408 _n . Of course, this AND circuit may have a configuration included in each of the output side selection circuits 408 _{1 to} 408 _n .

Now, it is assumed that the cell switch 53x is operating as an active system. Incoming lines ₁ 1 to 1 respectively arriving cell _n cell save circuit 228x ₁ ~228x _n, 2
It is input to both the 28y ₁ ~228y _n. The cell input from the cell save circuit 228x ₁ ~228x _n in the cell switch 53x is replaced by the cell switch 53x, is output to the switch output line 4x ₁ ~4x _m. Cell evacuation circuit 2
Even cell inputted to 28y ₁ ~228y _n in the same manner is outputted to the switch output line 4y ₁ ~4y _m. Since the cell switch 53x is currently in use, the output side selection circuit 408
₁ ～408 _m in the switch output lines 4x ₁ ~4x _n of cells is selected, outputted respectively to the output line 2 ₁ to 2 _m.

In this state, it is assumed that an instruction to set the cell switch 53y to the active system is received from the switching instruction signal. The exit-side selection circuit 408 ₁ ~408 _m, all the cell numbers compared output lines 57 ₁ to 57 _n save buffer means a cell equal, and are respectively connected to the outlet side selection circuit 408 ₁ ~408 _m idle cells in both switch output lines are switches to select a cell switch output line 4y ₁ ~4y _n respectively output timing. When the number of cells stored in the evacuation buffer in each group of the cell evacuation circuits corresponding to the group with the subscript x and the group with the subscript y is the same, since the cell is monkey similarly input to the input line 3x ₁ ~3x _n and 3y ₁ ~3y _n,
For the reason described in the seventeenth embodiment, the output side selection circuit 408 ₁
If switching is performed in the output-side selection circuit at the timing when idle cells are output to both of the switch output lines connected to ４０408 _m , no cell loss or duplication occurs. The opposite operation is performed when the active system is switched from the cell switch 53y to 53x. Thus, instantaneous interruption switching can be performed.

Embodiment 27 FIG. Example 17 to Example 2
In the sixth embodiment, the case where the cell save circuit shown in the first embodiment is used has been described.
6 may be used. Similarly, in the seventeenth to twenty-sixth embodiments, the case where the common buffer type switch shown in the first embodiment is used has been described. However, the common buffer type switch described in the second embodiment is used. No problem. In the embodiments 17 to 26, the case where the cell switch is duplicated has been described. However, the case where the cell switch is tripled or quadrupled may be used.

[0229]

[0230]

[0231]

[0232]

[0233]

As described above, according to the present invention, the cell
In a configuration where switches are multiplexed, the cell switch
By providing a cell evacuation circuit at the previous stage,
Cell replacement that is unlikely to occur even if
An exchange device can be obtained. According to the invention,
The congestion state can be determined for each cell switch, and the congestion state can be transmitted by the OR circuit.

Also, according to the present invention, the cell switch
In a multiplexed configuration, the cell
The provision of the evacuation circuit allows the cell switch
Cell switching equipment that does not easily cause cell discard even if
Obtainable. Further, according to the present invention, a congestion state can be determined for a plurality of cell switches using one congestion determination circuit.

Further, according to the present invention, even when an input-side selector is provided in a stage preceding a plurality of cell switches, it is possible to obtain a cell switching device capable of instantaneously switching without a control circuit.

[0236]

[0237]

[0238]

Further, according to the present invention, it is possible to obtain a cell switching device having a cell save circuit even in a multiplexing system having a configuration having an input selector at a stage preceding a cell switch.

[0240]

[0241]

[0242]

[0243]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a cell switching device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing details of a common buffer type switch 9 in FIG. 1 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 3 is a diagram showing a method of counting the number of stored cells according to an embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure of a congestion determination circuit 20 in the cell switching device according to one embodiment of the present invention.

FIG. 5 is a diagram showing an input state of a cell according to an embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure of a cell evacuation circuit 22 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 7 is a diagram showing an operation of a save buffer according to one embodiment of the present invention;

FIG. 8 is a diagram showing an implementation of a cell switching device according to an embodiment of the present invention.

FIG. 9 is a block diagram showing details of a common buffer type switch 9 in FIG. 1 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 10 is a flowchart showing a procedure of a congestion determination circuit 20 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 11 is a flowchart showing a procedure of a congestion determination circuit 20 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 12 is a block diagram showing details of a congestion determination circuit 20 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 13 is a flowchart showing a procedure of the congestion determination circuit 20 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 14 is a block diagram showing a cell switching device according to one embodiment of the present invention.

FIG. 15 is a flowchart showing a procedure of a cell evacuation circuit 22 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 16 is a block diagram showing a cell switching device according to one embodiment of the present invention.

FIG. 17 is a flowchart showing a procedure of a cell evacuation circuit 22 in the cell switching apparatus according to one embodiment of the present invention.

FIG. 18 is a block diagram showing a cell switching device according to one embodiment of the present invention.

FIG. 19 is a diagram showing an implementation of a cell switching device according to an embodiment of the present invention.

FIG. 20 is a block diagram illustrating a configuration example of a cell switching device according to an embodiment of the present invention.

FIG. 21 is a block diagram illustrating a configuration example of an output-side selection circuit according to an embodiment of the present invention.

FIG. 22 is a diagram for explaining non-stop switching in a cell switching apparatus according to an embodiment of the present invention.

FIG. 23 is a diagram illustrating a non-stop switching in a cell switching apparatus according to an embodiment of the present invention;

FIG. 24 is a diagram showing an implementation of a cell switching device according to an embodiment of the present invention.

FIG. 25 is a block diagram illustrating a configuration example of a cell switching device according to an embodiment of the present invention.

FIG. 26 is a block diagram illustrating a configuration example of a cell switching device according to an embodiment of the present invention.

FIG. 27 is a block diagram illustrating a configuration example of a common buffer type switch in the cell switching device.

FIG. 28 is a block diagram showing a configuration example of an egress selection circuit in the cell switching device.

FIG. 29 is a block diagram illustrating a configuration example of a cell switching device according to an embodiment of the present invention.

FIG. 30 is a block diagram illustrating a configuration example of a cell switching device according to an embodiment of the present invention.

FIG. 31 is a block diagram illustrating a configuration example of a common buffer type switch in the cell switching device.

FIG. 32 is a block diagram showing one embodiment of a cell switching device according to one embodiment of the present invention.

FIG. 33 is a block diagram showing one embodiment of a cell switching device according to one embodiment of the present invention.

FIG. 34 is a block diagram showing one embodiment of a cell switching device according to one embodiment of the present invention.

FIG. 35 is a block diagram showing a conventional cell switching device.

FIG. 36 is a block diagram showing a conventional ATM switch.

FIG. 37 is a configuration diagram of a conventional input control unit.

FIG. 38 is a diagram illustrating a conventional technique.

FIG. 39 is a diagram illustrating a conventional technique.

FIG. 40 is a block diagram showing a configuration of a conventional cell switching device.

FIG. 41 is a diagram illustrating a configuration example of a selector of a conventional cell switching device.

FIG. 42 is a timing chart showing the timing of input and output signals of a conventional cell switching apparatus.

FIG. 43 is another timing chart showing the timing of input and output signals of the conventional cell switching apparatus.

FIG. 44 is another timing chart showing the timing of the output signal of the conventional cell switching apparatus.

FIG. 45 is a block diagram illustrating a configuration of a conventional cell switching device.

FIG. 46 is a diagram for explaining movement of cells in a buffer at the time of switching of the conventional cell switching device.

[Explanation of symbols]

1 ₁ to 1 _n input line, 2 ₁ to 2 _m output line, 3 _{1 to} 3 _n switch input line, 4 ₁ to 4 _m switch output line, 7 cell multiplexing circuit, 8 cell separation circuit, 9, 92, 95 common buffer Type switch, 9a Common buffer type switch, 9b
Common buffer type switch, 10 header processing circuit, 1
0 ₁ to 10 _n header processing circuit, 11 common buffer memory, 11 _{1 to} 11 _p common buffer memory, 12 free address management circuit, 12 _{1 to} 12 _p free address management circuit, 13 incoming cross point switch, 14 outgoing side Cross point switch, 15, 152 Buffer control circuit, 15a Buffer control circuit, 15b Buffer control circuit, 16 Write buffer selection circuit, 16a
Write buffer selection circuit, 16b Write buffer selection circuit, 17 address exchange circuit, 18 ₁ to 18
_m , 182 ₁ -182 _m address queue, 19,1
92 read buffer selection circuit, 19a read buffer selection circuit, 19b read buffer selection circuit, 2
0,201 Congestion determination circuit, 21 switch internal monitor, 21a switch internal monitor, 21b switch internal monitor, 22 _{1 to} 22 _n , 221 _{1 to} 221 _n , 2
22 _{1 to} 222 _n , 224 _{1 to} 224 _n , 228 ₁ to 2
28 _n cell save circuit, 23 ₁ ~ 23 _n save _{buffer, 24 1 ~24 n, 241 1} ~241 n, 242 1 ~
242 _n , 244 _{1 to} 244 _n , 248 _{1 to} 248 _n
Save buffer control, 25 _{1 to} 25 _n save input selector, 26 _{1 to} 26 _n save output selector, 27 ₁ to 2
7 _n bypass link, 28 _{1 to} 28 _n priority cell discriminating circuit, 29 _{1 to} 29 _n control cell multiplexing circuit, 30 _{1 to} 3
0 _n control cell separation circuit, 31 congestion judgment output line,
32 history storage pool, 33 history operation circuit, 34 comparison circuit, 40 ₁ to 40 _m , 402 ₁ to 402 _m , 406
_{1 to} 406 _m , 407 _{1 to} 407 _m , 408 _{1 to} 408
_m output side selection circuit, 41 OR circuit, 42 switching instruction signal, 43 selector, 44, 442 switching timing detection circuit, 45 switching signal, 46 OR circuit, 47 _{1 to} 47 _n input side selector, 48, 486 control circuit, 49 ₁ to 49 _m queue monitor circuit, 50 ₁ to
50 _m cell presence / absence notifying means, 51 _{1 to} 51 _m output permission signal line, 52 _{1 to} 52 _m switching permission signal line, 53,
531, 532, 533, 536 cell switch, 54
_{1 to} 54 _m header change circuit, 55 _{1 to} 55 _n evacuation circuit cell presence / absence notification means, 56 _{1 to} 56 _n evacuation buffer cell number comparison circuit, 57 _{1 to} 57 _n evacuation buffer cell number comparison output line, 58 ₁ to 58 _n means for notifying the number of cells in the evacuation buffer, 59 AND circuit.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hirotoshi Yamada 5-1-1, Ofuna, Kamakura-shi Mitsubishi Electric Corp. Communication Systems Laboratory (72) Inventor Isshin Oshima 5-1-1, Ofuna, Kamakura-shi Mitsubishi (56) References JP-A-8-8921 (JP, A) JP-A-3-117137 (JP, A) JP-A-63-102527 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H04L 12/56

Claims (4)

(57) [Claims] 1. A plurality of input lines for inputting a cell comprising a data portion and a header portion including destination information thereof , and (b) outputting a cell in accordance with the destination information specified in the header portion of the cell. a plurality of outgoing line that includes a plurality of cell switch output to (c) includes a buffer memory, and stored in the buffer memory by entering the cell, the outgoing line designated the stored cell in its header portion, ( d) a congestion determining means for monitoring a cell reserved state of the buffer memory of the plurality of cell switches and determining a congestion state ; and (e) corresponding to each of the incoming lines between the incoming line and the plurality of cell switches. and provided, wherein a cell saving means for temporarily storing cells arriving before entry line on the basis of the congestion state determined by the congestion determining means, said congestion determining means, said plurality of cells Provided corresponding to switches, each Sells
Multiple congestion times to determine switch congestion status
And the outputs from the plurality of congestion determination circuits.
And an OR circuit for outputting to the cell evacuation means . 2. (a) A data part and its destination information
A plurality of incoming lines for inputting a cell comprising a header part ; and (b) according to destination information specified in a header part of the cell.
A plurality of outgoing lines from which cells are output, and (c) a buffer memory.
Memory cell, and the stored cell is designated by its header.
A plurality of cell switches for outputting to a predetermined outgoing line; and (d) cells of a buffer memory of the plurality of cell switches.
Monitoring the hold status and judging the congestion status
A constant section, fill front between the plurality of cell switch to the previous entry line (e)
Provided for each of the lines,
Arrive at the incoming line based on the congestion status determined
Cell evacuation means for temporarily storing the selected cells, wherein the congestion determination means monitors congestion states of the plurality of cell switches, and
The congestion status of multiple cell switches is determined and the
One congestion judgment that outputs the result to the cell evacuation means
A cell switching device comprising a circuit. 3. The cell switching device further comprises a cell evacuation unit.
Input the cell output from the
Input selector and switch to the cell switch selected by the input selector.
A control circuit for controlling the switching.
3. The cell switching device according to claim 1 or 2. 4. A data part and a header part including destination information thereof.
And a plurality of incoming lines for inputting cells comprising
A plurality of outgoing lines to be input from any of the incoming lines.
The cell that has been set according to the destination information
A cell switching device for outputting to the input line for temporarily storing the input cell.
And a save buffer in which cells are actually stored.
To manage the writing and reading of cells to the save buffer.
Common to cell save circuit with save buffer control and common buffer type switch that actually replaces cells
Determines whether the buffer type switch is in the congestion state.
A first cell switch having a congestion determination circuit; and a second cell switch having the same configuration as the first cell switch.
And the cells read out from the cell evacuation circuit in the first cell.
Input to the cell switch and the second cell switch
And entry side selector which can be switched, output the previous congestion judgment circuit of the first cell switch
The logic of the output of the congestion determination circuit of the second cell switch
OR circuit for taking a sum and inputting the sum to the cell save circuit
And the first cell switch provided in correspondence with the outgoing line.
Select one of the cells output by the second cell switch
An output-side selection circuit for outputting to the outgoing line;
And the second cell switch also outputs a cell corresponding to the outgoing line.
And a control circuit for applying a force permission, when the switch request of the cell switch occurs, first
Turn off the cell switch that inputs cells with the input selector.
From the cell switch where cells are no longer input.
The other cell switch starts from the output line where the output of the
The cell output starts, and the corresponding output selection circuit
Switch to select that cell
Enables instantaneous interruption switching of cell switch to be changed
Cell exchange equipment.