JP3097549B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode: Used for communication.
The present invention relates to a technique for improving the throughput of an ATM switch. The present invention relates to a technique for guaranteeing the bandwidth of bandwidth-guaranteed traffic in an ATM communication network in which bandwidth-guaranteed traffic and best-effort traffic coexist.

[0002]

2. Description of the Related Art Traffic input to a high-speed output buffer type ATM switch is limited to only CBR (Constant Bit Rate) and VBR (Variable Bit Rate) traffic, and is used in a switch using a traffic descriptor previously declared by a user. In an environment where the required bandwidth can be allocated in the network, the admission control (CA) is performed based on the traffic descriptor of the connection.
C: Call Admission Control), etc., the bandwidth is guaranteed by regulating the traffic volume at the output port of the ATM switch, so if the capacity of the ATM switch is greater than the total output line speed, Cell loss can be prevented.

However, in recent years, ABR (Available Bit)
A service class called a best effort class, such as a rate (U.R. Rate) or an UBR (Unspecified Bit Rate), has been spotlighted. The traffic of these best-effort classes does not regulate the traffic volume by CAC unlike CBR and VBR, and may cause deterioration of the quality of CBR and VBR.

[0004] The ABR class is a service class in which the allocated bandwidth flexibly changes according to the traffic situation. A user can receive a large bandwidth when the used bandwidth of the CBR class or the VBR class is small. In addition, there is a restriction that when the used band of the CBR class or the VBR class is large, only a small band can be allocated. However, communication costs are set at a low price. Since the changing band information is notified to the transmitting terminal in advance, as long as the transmitting terminal adheres to the notified band, the cell is not discarded during transfer in principle.

[0005] In the UBR class, a constant cell loss rate is guaranteed according to traffic conditions within a predetermined time.
The peak cell rate is not always guaranteed. However, communication costs are set at a low price. UB
In the R class, there is a possibility that cell loss during transfer occurs at a certain rate.

Therefore, in order to protect the CBR class or the VBR class in the ATM switch, a buffer is usually divided into a CBR class or a VBR class and a buffer for the best effort class, and if there is a cell in the buffer for the CBR class or the VBR class, Control is performed such that cells are transferred preferentially, and cells in the buffer for the best effort class are transferred only when no cell exists in the buffer for the CBR class or the VBR class.

In the case of data communication using the UBR class, if even one cell is discarded in the network, the receiving terminal determines that the packet including the cell is an invalid cell. The EPD (Early Packet Discard) method in which all cells constituting a new packet arriving at the buffer during congestion are forcibly discarded at the buffer entrance because there is a problem that the entire network is discarded or retransmitted and the effective throughput of the network is significantly reduced. [A. Romanow: "Packet Discard Strategies for Co."
ntrolling ATM Congestion ", ATM Forum / 94-0107, 1994]
And so on.

For example, when EPD control is performed during congestion using an AAL (ATM Adaptation Layer) 5, an ATM-user-to-user (AU) indicating an end-of-packet of an AAL packet is used.
U) An end-of-packet (EOP) cell and the next EOP for each VCI using the parameter and the VC identifier in the cell header.
The cell is regarded as the same packet, and if the packet is currently being transferred, the cell is written to the buffer as it is. If the packet is not being transferred, the cell is determined to be the head cell of the packet and the operation of discarding the cell until the EOP cell arrives is performed. This discarding procedure is repeated until the congestion state is resolved.

[0009]

SUMMARY OF THE INVENTION
If the switch is of a small scale of about 4 to 10 Gb / s, a switch can be constituted by a single-stage buffer.
The PD control does not significantly affect the hardware scale, but a large-scale ATM switch of 10 Gb / s or more becomes a multistage switch network. FIG. 14 is a configuration diagram of a conventional high-speed output buffer type multi-stage switch. The output side of each of the unit switches SW _{1 to} SW _m performs full priority control and E
PD control is required, and the impact on the hardware scale increases.

[0010] Figure 15 is a diagram showing the cell discard bandwidth-guaranteed traffic in a multi-stage switch was made by the unit switch SW ₁ to SW ₄ of the last stage in strict priority control and EPD control as in FIG. 15 Alone does not control the amount of traffic in the best-effort class of the core switch C, so that the bandwidth guarantee class is adversely affected by the core switch C, or the effective amount is lost due to the loss of cells in the middle of the packets of the best-effort class. A decrease in throughput is inevitable. For this reason, the core switch C also requires strict priority control.

However, since the core switch C performs switching in units of large bundles, high speed operation is required.
In such a situation, it is difficult to perform the full priority control and the EPD control.

The present invention has been made in view of such a background, and an object of the present invention is to provide an ATM switch capable of applying strict priority control and EPD control to a large-scale core switch. An object of the present invention is to provide an ATM switch capable of improving throughput. SUMMARY OF THE INVENTION It is an object of the present invention to provide an ATM switch capable of guaranteeing the bandwidth of bandwidth-guaranteed traffic in an ATM communication network in which bandwidth-guaranteed traffic and best-effort traffic coexist.

[0013]

The queue length of a buffer of a core switch is observed, and if the queue length exceeds a preset threshold, it is determined that link congestion between the core switch and the unit switch has occurred, The first cell to be read carries the link congestion information and notifies the subsequent cell.

Further, the queue length of the buffer for each best effort class of the unit switch is observed, and when the queue length exceeds a preset threshold, it is determined that the output port is congested, and the bandwidth guarantee of the unit switch is performed. Regardless of either the class buffer or the best effort class buffer, the output cell congestion information is put on the head cell read from the buffer and the congestion is notified to the output line corresponding unit.

When the output line corresponding unit is notified of the congestion,
A cell is generated, and the generated cell is put on the reverse link to notify all input line corresponding units of congestion. Each input line corresponding unit that has received the notification of congestion refers to the table, detects from the beginning to the end of the packet addressed to the congested link or the output line, and discards the cell.

That is, the present invention relates to an ATM switch, an input line corresponding unit for accommodating an input line, a switch unit provided with a queuing buffer, and distributing an output cell of the input line corresponding unit to a desired route. And an output line corresponding unit that is provided for each output route of the unit and accommodates an output line. A feature of the present invention is that the switch unit includes means for monitoring the queue length of the buffer, and the output line corresponding unit includes an RM having congestion information based on output information of the monitoring means.
There is provided a means for generating a cell and a means for transmitting the RM cell to the input line corresponding unit.

Thus, the congestion that occurs in the high-speed switch unit can be controlled by the low-speed input line corresponding unit and the low-speed input line corresponding unit at the entrance and exit.

Preferably, the ATM switch is provided bidirectionally, and the RM cell addressed to the input line corresponding unit from the output line corresponding unit is transmitted via the ATM switch on the opposite side.

The switch unit includes one core switch that receives the output of the input line corresponding unit, and a plurality of unit switches connected to the output of the core switch. The means for monitoring the queue length includes: The unit switch monitor for monitoring the number of cells stored in the buffer of the unit switch, and a circuit for giving a congestion bit to an output cell according to the monitoring result of the unit switch monitor may be provided.

Further, the means for monitoring the queue length includes a core switch monitor for monitoring the number of cells stored in the buffer of the core switch, and a congestion bit in the output cell according to the monitoring result of the core switch monitor. May be further provided with a circuit for providing

Alternatively, the switch unit includes one core switch for receiving the output of the input line corresponding unit, and a plurality of unit switches connected to the output of the core switch, and monitors the queue length. Comprises a unit switch monitor for monitoring the number of cells stored in the buffer of the unit switch, and a circuit for transmitting the monitoring result of the unit switch monitor to the means for generating the RM cell. Can also.

Further, the means for monitoring the queue length includes a core switch monitor for monitoring the number of cells stored in the buffer of the core switch, and a means for generating the RM cell based on the monitoring result of the core switch monitor. And a circuit for transmitting the data to the device.

Thus, the monitoring result can be transmitted directly to the means for generating the RM cell, so that the circuit for giving the congestion bit to the output cell can be omitted.

Further, the means for monitoring the queue length of the unit switch or the core switch may include a circuit for directly transmitting the monitoring result to the input line corresponding unit without using the RM cell.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

[0026]

【Example】

(First Embodiment) The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an ATM switch according to a first embodiment of the present invention.

The present invention relates to an ATM switch, which is characterized by an input line corresponding section IN _i (i = 1, 2,..., MN) accommodating an input line, and queuing buffers 3, 5, 6. a switch unit 10 for distributing the output cells of the input line corresponding unit iN _i to the desired route includes a, and an output line unit OUT _i output lines provided in the output path for each of the switch portion 10 is accommodated ATM switch provided.

Here, a feature of the present invention is that the switch unit 10 includes a core switch monitor M1 and a unit switch monitor M2 as means for monitoring the queue lengths of the buffers 3 and 5, and an output line corresponding unit. OUT
_i means for generating an RM cell carrying congestion information based on the output information of the core switch monitor M1 and unit switch monitor M2; means for transmitting the RM cell to the input line corresponding unit IN _i ; Is provided in the backward RM cell generation circuit 8.

This ATM switch is provided bidirectionally,
Although RM cell from the output line corresponding unit OUT _i addressed to the input line corresponding unit IN _i is transmitted via the ATM switch on the opposite side, shown only one-way for clarity of explanation here.

The switch unit 10 includes an input line corresponding unit IN _i
And a unit switch SW _j (j connected to m outputs of the core switch C).
= 1, 2,..., M).
Monitor M1 monitors the queue length of the buffer 3 provided in the core switch, the unit switch monitor M2 monitors the queue length of the buffer 5 provided in the unit switches SW _j, congestion in the output cells in accordance with the monitoring result Congestion bit assignment circuits 4 and 14 as circuits for assigning bits
It has.

The buffer 5 is a buffer for storing cells of the best effort class, and the buffer 6 is a buffer for storing cells of the band guarantee class. The congestion monitoring is performed in a buffer 5 in which cells of the best effort class are stored.
Only done with. The monitoring result is stored in buffer 5 or 6
Congestion bit determination circuit 7 of the output line corresponding unit OUT _i by congestion bit is given by the congestion bit applying circuit 14 even cell outputted from either buffer
Will be notified.

The switching operation of the ATM switch according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram for explaining the header conversion table. The cell transmitted from the user is the input line corresponding part IN _{i of the} ATM switch.
, The header conversion circuit 2 searches the header conversion table shown in FIG. 2 based on the VPI / VCI value written in the header of the cell, converts the VPI / VCI value, and converts the VPI / VCI into the cell header. Write routing information such as a / VCI value and a routing tag bit. At the same time, as shown in the header conversion table of FIG. 2, the header conversion circuit 2 determines whether the service category of the cell is the band guarantee type or the best effort type at the time of searching this table, and determines the service category field of the cell header portion of each cell. The service category identifier is written in. Thereafter, the cell is sent to the purpose output port is switched in the core switches C and the unit switches SW _j based on the routing bits written in the cell header, bandwidth guarantee based on the cell header of the service category identifier by the selector 9 at its output stage The cells stored separately in the class buffer 6 and the best effort class buffer 5 and stored in the buffer 6 are preferentially transferred to the transmission path.

Next, the congestion control of the ATM switch according to the first embodiment of the present invention will be described. AT of the first embodiment of the present invention
The M switch is a core switch C that can become a congestion point when excessive traffic of best effort type flows in.
And a buffer 3 and congestion avoidance capabilities of the buffer 5 and 6 of the unit switches SW _j. FIG. 3 is a diagram showing congestion points.

Next, the core switch C according to the first embodiment of the present invention will be described.
The congestion avoidance control of the buffer 3 will be described. FIG. 4 shows a congestion control flow in the buffer 3 of the core switch C. FIG. 5 shows the configuration of the in-switch cell header information. R
FIG. 6 shows the configuration of the M cell. FIG. 7 shows a congestion management table. FIG. 8 shows a packet management table. Links between the aims outgoing line of best-effort traffic is increased to accommodate the particular unit switches SW _j where that traffic core switch C and the unit switches SW _j entering the core switch C falls into a congestion.

The monitor M1 provided in the buffer 3 constantly monitors the queue length (S1). If the observed queue length exceeds a preset threshold α (S2), the buffer 3 can discard cells. determines that there sex, sets the congestion information of the link to the top link congestion notification field cell header of cells in the buffer 3 as in FIG. 5 (S3), and sends the cell to the subsequent unit switches SW _j . When the unit switch SW _j congestion bit decision circuit 7 is further transmitted to the output line corresponding unit OUT _j is switched cell detects link congestion by the written information in the link congestion notification field (S4), reverse R
Sending link congestion information the congestion link number in the link information field of the RM cell as M cell generation circuit 8 shown in FIG. 6 writes, all put an RM cell in the direction opposite to the line of the input-side line interface IN _i (S5). Header conversion circuit of the input line corresponding unit IN _i to link congestion information is notified 2 sets the link congestion information to the congestion management table of FIG. 7 (S6).

Thus, all the input line corresponding sections IN
_i will have a congestion management table with common congestion information. Then, the header conversion circuit 2 when a new cell arrives at the input line corresponding unit IN _i determines the service category of the cell before header conversion, the service category of the cell is best effort, fallen into the congestion from the routing information When aiming for a link that is present, the EOP determination circuit 1 is operated. At this time, the EOP determination circuit 1 simultaneously searches the packet management table of the cell shown in FIG. 8 and determines, for each VC, whether this cell is a cell forming a packet being transferred or a cell forming an untransferred packet. If the cell constitutes an untransmitted packet, it is determined to be the first cell of the packet,
The cell is discarded until the last AAL5 EOP cell arrives. This discarding procedure is repeated until the congestion is resolved. Thus each input line corresponding unit IN _i in the can since the EPD control link congestion is avoided with respect to a best effort cell that aims to congestion link (S7).

When the link congestion is avoided, the queue length of the buffer 3 of the core switch C connected to the link is reduced. Therefore, when the monitor M1 monitoring the queue length detects that the queue length of the buffer 3 becomes equal to or less than the threshold value β. determines that the congestion control release (S8), and sends to set the cell header of the link information link congestion removal number in the field of cell at the beginning of the buffer 3 to the unit switch SW _j of the rear stage (S
9). When the congestion bit determination circuit 7 detects this congestion release signal (S10), the reverse direction RM cell generation circuit 8 puts the link congestion release number on the RM cell and sets each input line corresponding unit IN.
_i (S11). By each input line corresponding unit IN _i which receives the RM cell unlink congestion field in the congestion management table (S12), thereafter, E for the cell addressed the link arriving at the input line corresponding unit IN _i
The PD control is released.

Next, a buffer 6 for bandwidth guaranteed class unit switches SW _j of the ATM switch of the first embodiment of the present invention
And congestion control in the buffer 5 for the best effort class will be described. Figure 9 is a diagram showing a flow of a congestion control in the buffer 5 and 6 of the unit switches SW _j. When the number of best-effort cells aiming at a specific output line increases, the output line becomes congested, and the queue length of the buffer 5 placed before the output line increases (S21). When the queue length increases beyond a predetermined threshold α, the monitor M2 monitoring the queue length determines that the output line has become congested (S22), and outputs the output line congestion in the cell header area of the cell at the head of the buffer 5 or 6. sets the congestion is sent to the output line corresponding unit OUT _j field (S2
3).

[0039] When the congestion of the buffer 5 is detected by receiving the cell congestion bit determination circuit 7 of the output line corresponding unit OUT _j (S24), and generates a RM cell by backward RM cell generation circuit 8 RM The congested output line number information is written in the output port information field of the cell, and the information is put on the line in the reverse direction, and all the input side line corresponding sections IN are written.
_The output line congestion is sent to _i (S25).

[0040] V congestion management table in the header conversion circuit 2 receives this RM cell in each input line corresponding unit IN _i
The congestion bit is set in the line information field corresponding to the PI / VCI value (S26). Then, this cell when the new cell to the input side line corresponding unit IN _i arrives header conversion circuit 2 is to look at the same time routing information VPI / VCI conversion at the cell header conversion has fallen into the congestion in best-effort cell output When aiming at a port, the EOP determination circuit 1 is operated. At this time, the EOP determination circuit 1 searches the packet information table of the cell, determines for each VC whether this cell is a cell constituting a packet being transferred or a cell constituting an untransferred packet, Is determined as the head cell of the packet, and the cell is discarded until the AAL5 EOP cell constituting the packet arrives. This discarding procedure is repeated until the congestion is resolved. Thus each input line corresponding unit IN _j congestion is avoided since the EPD control for best effort cell that aims to congestion output line (S2
7).

When the congestion is avoided, the queue length of the buffer 5 is reduced.
When the monitor M2 detects that the queue length of the buffer 5 becomes equal to or smaller than the threshold value β, the monitor M2 determines that the point is the congestion control release point (S2).
8), sets the output port information field of the cell header of the cell at the head of the buffer 5 or 6 sends to the output line corresponding unit OUT _j (S29). In the congestion bit decision circuit 7 detects the congestion release signal (S30), backward RM cell generation circuit 8 is sent toward each input line corresponding unit IN _i put the output line congestion removal number RM cell (S
31). Each input line corresponding unit IN _i which receives the RM cell resets the output line congestion field in the congestion management table. Thus thereafter, so that the EPD control is canceled for a cell arriving at the input line corresponding unit IN _i (S
32).

[0042] However, the core switches C buffer 3 and the output and if the input line corresponding unit IN _i to link congestion information to the congestion in both buffers 5 of the unit switches SW _j of the output stage which is linked to it happening line Two pieces of congestion information are notified, and a link congestion bit and an output line congestion bit are set in the congestion management table of the header conversion circuit 2. In this case, the control procedure of the EOP determination circuit 1 has the congestion bit set. EPD control is performed on the best-effort cell destined for the output line, and then EPD control is performed on the cell destined for the congested link.

Second Embodiment ATM of Second Embodiment of the Present Invention
The switch will be described with reference to FIGS. FIG. 10 is an overall configuration diagram of an ATM switch according to a second embodiment of the present invention. FIG. 11 is a diagram showing a congestion management table according to the second embodiment of this invention. The switching operation of the ATM switch according to the second embodiment of the present invention is the same as that of the first embodiment of the present invention, and the description is omitted. The present invention In a second embodiment, as shown in FIG. 10, the link between the unit switches SW _j of core switches C and the output stage, a monitor of the buffer 3 of the core switches C on the assumption that most cell loss does not occur M1 and eliminating the congestion bit applying circuit 4 from the core switches C, as shown in FIG. 11 constitute a ATM switch without the link congestion field in the congestion management table of the input line corresponding unit iN _i, congestion control procedure according to the present invention This is the same as a series of operations except the link congestion control procedure in the first embodiment.

(Third Embodiment) ATM of Third Embodiment of the Present Invention
The switch will be described with reference to FIG. FIG. 12 is an overall configuration diagram of an ATM switch according to a third embodiment of the present invention. The switching operation of the ATM switch according to the third embodiment of the present invention is as follows.
The description is omitted because it is the same as the first embodiment of the present invention. The ATM switch of the present invention the third embodiment, the congestion information in the buffer 5 for best effort class of buffer 3 and the unit switches SW _j of according to the present invention the first embodiment and the same procedure but the core switches C depending on the cell First, the core switch monitor M1 of the buffer 3 of the core switch C and the unit switch S
W output line corresponding unit unit switches monitor M2 of the buffer 5 of the _j connected by signal lines to the backward RM cell generation circuit 8 OUT _i, and notifies the congestion information by the signal line.

As a result, the number of wirings is increased as compared with the first embodiment of the present invention, but the congestion bit assigning circuits 4 and 14 can be omitted, so that the configuration of the apparatus can be simplified.

(Fourth Embodiment) ATM of Fourth Embodiment of the Present Invention
The switch will be described with reference to FIG. FIG. 13 is an overall configuration diagram of an ATM switch according to a fourth embodiment of the present invention. In the fourth embodiment of the present invention, the core switch monitor M1 is omitted as in the second embodiment of the present invention, the queue length is monitored only by the unit switch monitor M2, and the congestion is monitored as in the third embodiment of the present invention. eliminating the bit imparting circuit 14, connected by a signal line backward RM cell generation circuit 8 of output line corresponding unit OUT _i unit switches monitor M2, and notifies the congestion information by the signal line.

As a result, it is possible to adopt a configuration in which the advantages of the second embodiment and the third embodiment of the present invention are adopted.

The monitoring results of the monitors M1 and / or M2 are directly transmitted to the input circuit corresponding section I without using the RM cell.
It can be configured to notify the N _i.

[0049]

As described above, according to the present invention,
Full priority control and EPD control can be applied to a large-scale core switch. Further, the throughput can be improved, and the bandwidth of the bandwidth-guaranteed traffic can be guaranteed in the ATM communication network in which the bandwidth-guaranteed traffic and the best-effort traffic coexist.

That is, since EPD control is performed on the best-effort traffic at the time of congestion in which a cell loss occurs, there is an advantage that invalid traffic in the network due to invalid cell retransmission due to dropped packets can be reduced. The core switch only needs means for providing link congestion information by observing the queue length of the buffer, so that the switch can be configured with a simple configuration regardless of the switch scale. In addition, EPD control in the input line corresponding unit has an advantage that it can be configured only by providing a simple circuit to the header conversion unit. Since the best-effort traffic flowing into the switch is restricted at the input side, the bandwidth guaranteed traffic is Communication quality can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ATM switch according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a header conversion table.

FIG. 3 is a diagram showing congestion points.

FIG. 4 is a diagram showing a congestion control flow in a buffer of a core switch.

FIG. 5 is a diagram showing a configuration of in-switch cell header information.

FIG. 6 is a diagram showing a configuration of an RM cell.

FIG. 7 is a diagram showing a congestion management table.

FIG. 8 shows a packet management table.

FIG. 9 is a diagram showing a flow of congestion control in a buffer for a bandwidth guarantee class and a buffer for a best effort class in a unit switch.

FIG. 10 is an overall configuration diagram of an ATM switch according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a congestion management table according to the second embodiment of the present invention.

FIG. 12 is an overall configuration diagram of an ATM switch according to a third embodiment of the present invention.

FIG. 13 is an overall configuration diagram of an ATM switch according to a fourth embodiment of the present invention.

FIG. 14 is a configuration diagram of a conventional high-speed output buffer type multi-stage switch.

FIG. 15 is a diagram showing cell discarding of bandwidth-guaranteed traffic in a multistage switch.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 EOP judgment circuit 2 Header conversion circuit 3, 5, 6 Buffer 4, 14 Congestion bit assignment circuit 7 Congestion bit judgment circuit 8 Reverse RM cell generation circuit 10 Switch part C core switch IN _i input line corresponding part M1 core switch monitor M2 Unit switch / monitor OUT _i Output line corresponding part SW _j Unit switch

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-8-8932 (JP, A) JP-A-6-105351 (JP, A) JP-A-3-1755843 (JP, A) JP-A 8- 18569 (JP, A) JP-A-8-8926 (JP, A) JP-A-6-30033 (JP, A) JP-A-4-145744 (JP, A) (58) Fields investigated (Int. ^7, DB name) H04L 12/56 H04L 12/28 H04Q 3/00 H04Q 3/52

Claims (6)

(57) [Claims] 1. An input line corresponding unit for receiving an input line,
It has a queuing buffer and the output
Switch that distributes the switch to the desired route and this switch.
Output provided for each output route of the switch
With a line handling unitATM switch is provided in both directions
And  A means for monitoring the queue length of the buffer in the switch unit.
A step, wherein the output line corresponding section has the output information of the monitoring means.
For generating RM cell with congestion information based on it
And transmits the RM cell to the input line corresponding unit.
With means, R from the output line corresponding unit to the input line corresponding unit
M cell is transmitted via ATM on opposite side Specially
ATMCommunication network. 2. An input line corresponding unit accommodating an input line,
An ATM switch having a queuing buffer and a switch unit for distributing output cells of the input line corresponding unit to a desired route, and an output line corresponding unit provided for each output route of the switch unit and accommodating an output line. In the above, the switch unit may include means for monitoring the queue length of the buffer, and the output line corresponding unit may generate an RM cell having congestion information based on output information of the monitoring means, Means for transmitting a cell to the input line corresponding unit, the switch unit comprising: one core switch for receiving an output of the input line corresponding unit; and a plurality of unit switches connected to the output of the core switch. Wherein the means for monitoring the queue length is stored in a buffer that stores cells of a service class in which the bandwidth of the unit switch is not guaranteed. And the unit switch monitor which monitors the number of cells was, A TM switch you characterized by comprising a circuit for applying the congestion bit in the output cells in accordance with the monitoring result of the unit switch monitor. Wherein means for monitoring the queue length, the co
And core switch monitor which monitors a number of cells stored in the buffer of the A switch, ATM of claim 2 further comprising a circuit for applying the congestion bit in the output cell in accordance with the monitoring result of the core Switch Monitoring switch. 4. An input line corresponding unit accommodating an input line,
An ATM switch having a queuing buffer and a switch unit for distributing output cells of the input line corresponding unit to a desired route, and an output line corresponding unit provided for each output route of the switch unit and accommodating an output line. In the above, the switch unit may include means for monitoring the queue length of the buffer, and the output line corresponding unit may generate an RM cell having congestion information based on output information of the monitoring means, Means for transmitting a cell to the input line corresponding unit, the switch unit comprising: one core switch for receiving an output of the input line corresponding unit; and a plurality of unit switches connected to the output of the core switch. Wherein the means for monitoring the queue length is stored in a buffer that stores cells of a service class in which the bandwidth of the unit switch is not guaranteed. A unit switch monitor for monitoring the number of cells, and a monitoring result of the unit switch monitor for the RM.
JP further comprising a circuit for transmitting to the means for generating a cell
ATM switch to the butterflies. 5. A means for monitoring the queue length, the co
Co to monitor the number of cells stored in the buffer of the A switch
5. The ATM switch according to claim 4 , further comprising: an a- switch monitor; and a circuit for transmitting a monitoring result of the core switch monitor to a means for generating the RM cell. 6. A means for monitoring the queue length, the single
Cell of the class of service that the band is not guaranteed of position switch
Queue length of the buffer that accumulates data exceeds the first value (α)
Then, it is determined that the state is congested, the queue length is the first value
Less than the second value (β) and less than the first value
To determine that the congestion state has not been resolved while
An ATM switch according to any one of claims 2 to 5 , including a stage .