JP2598583B2 - Cell flow control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path for transmitting an information sequence in units of cells (a multiplexed virtual channel) or a transmission line (a further multiplexed path) in time division multiplex digital transmission. The present invention relates to a cell flow control method in a delay circuit that matches the transmission delay of a working path or a working transmission line with a protection path or a protection transmission line when instantaneous interruption switching is performed.

[0002] Non-instantaneous switching of a path or a transmission line is performed by switching back after restoration of the transmission line, relocating and switching back a transmission line or a section that is hindered by construction of a node, and switching when transmission quality of the transmission line deteriorates. This is performed in transmission path switching, switching back, and the like. In the following description, the instantaneous switching of the path is described, but the instantaneous switching of the transmission path is similarly described.

[0003]

2. Description of the Related Art A cell is a virtual channel (hereinafter, referred to as a virtual channel).
It is called “VC”. ) And an identifier VPI for identifying a virtual path (hereinafter referred to as “VP”).
This is a fixed-length (53-byte) packet having (virtual path identifier) in the header area. Note that real cell flows of the same VCI constitute a VC, and real cell flows of the same VPI constitute a VP.

FIG. 6 is a diagram showing an example of the configuration of a path for performing instantaneous interruption switching. Note that this configuration example performs parallel transmission.
This is for the case of performing instantaneous interruption switching on the receiving side. In the figure, on the receiving side, a path changeover switch 61 is switched from an active path 62 having a large transmission delay to a protection path 6 having a small transmission delay.
In the case where the switching is performed without interruption at 3, the delay circuit 64 for temporarily storing cells on the backup path 63 side is necessary to absorb the transmission delay difference between them. That is, when the path changeover switch 61 performs the instantaneous interruption switching from the working path 62 to the protection path 63, the cells stored in the delay circuit 64 are sequentially read to prevent the cells from being lost at the time of switching and to prevent the arrival of the cells. You can guarantee the order. The transmission delay difference to be absorbed by the delay circuit 64 may reach 3000 cell times.

[0005] The delay circuit 64 is placed in a device on the transmission side or the reception side in the path switching sections A and B, but the figure shows a state where it is placed on the reception side. Further, the delay circuit 64
Is configured to accumulate only real cells that need to be subjected to delay processing, and remove all empty cells (idle cells, cells having no information, and cells that can be discarded) having no meaning in delay processing. An empty cell on the transmission path includes a bit string indicating an empty cell, but an empty cell in the device is a non-signal section.

FIG. 7 is a diagram showing a change over time in the cell flow rate at point A before path switching. In the figure, the cell flow in the path is composed of real cells and empty cells. When the real cell occupancy per unit time is high, the cell flow rate (real cells) increases, and when the real cell occupancy rate is low, the cell flow decreases. When the instantaneous interruption switching is performed at the time a, the transmission delay difference is absorbed by reading the cell flow stored in the delay circuit 64 in the time section up to the time b. That is, before the time a, the cell flow via the working path 62 is changed to the path changeover switch 6.
Pass point B via 1. After time a, the cell flow passing through the backup path 63 passes through the point B via the delay circuit 64 and the path switch 61.

As described above, in the conventional method, the delay circuit 64 is used to absorb the transmission delay difference when switching from the working path 62 having a large transmission delay to the protection path 63 having a small transmission delay without instantaneous interruption. , And time compression is performed by removing empty cells. Therefore, after switching to the backup path 63 by the path switch 61,
Only the real cells are continuously read from the delay circuit 64. As a result, as shown in FIG. 8, the cell flow rate observed at the point B at the time of path switching is the time a at the point A.
Since the real cells that have passed from the time point t to the time point b are read at a stretch, the actual cells temporarily increase.

FIG. 10 is a block diagram showing a configuration example of a conventional delay circuit. In the figure, the conventional delay circuit is FI
FO (First In-First Out Memory) 80
Has been realized. Write address generation circuit 81
Generates a write address in response to a cell write control signal 91. The memory 82 writes the input cell 92 to the area indicated by the write address output from the write address generation circuit 81. The writing is performed on the real cells only in the order of arrival, and the empty cells are removed. Further, the read address generation circuit 83 generates a read address according to the cell read control signal 93. The memory 82 sequentially reads out the cells in which the data has been written first according to the read address output from the read address generation circuit 83 and outputs the read cells as output cells 94. Each circuit operates according to the clock 95, and outputs an empty signal 96 when all the cells are read from the memory 82.

[0009]

However, in the conventional cell flow control method using the above-described delay circuit to absorb the transmission delay difference, the stored real cells are continuously read out, so that the cells are provided for each VC. Exchange or VC that processes
It has been unavoidable that the speed of the VC temporarily increases at the receiving terminal connected by the above. Therefore, sometimes the cell exchange processing in the exchange or the cell reception processing by the receiving terminal cannot catch up.

On the other hand, in an asynchronous transfer mode (ATM) transmission network for transmitting information in units of cells, the amount of cells (VC rate) output from a transmitting terminal.
Are defined as an average rate and a peak rate by the number of cells transmitted at a fixed time at the transmission rate of each terminal and the minimum cell interval. In the conventional cell flow control method, the average speed and the peak speed are greatly increased.

In particular, in a time zone where the VC is multiplexed (or a transmission line on which the path is further multiplexed) and the usage rate is low, the instantaneous interruption switching is performed in the direction of a small transmission delay. In such a case, the cell of the transmission delay difference is released from the delay circuit in a short time, so that the time compression effect of the cell flow becomes very large. That is, the average speed and the peak speed of the VC sharply increase, and the above-mentioned problems become remarkable.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cell flow control method capable of minimizing an increase in the average speed and the peak speed of a VC even when the instantaneous switching is performed in a direction in which the transmission delay is small. .

[0013]

According to the first aspect of the present invention, a cell stream consisting of real cells and empty cells constituting a path or a transmission line arriving at a delay circuit has an integer Nth cell. If it is an empty cell, the empty cell section is removed, and the cell flow from which the empty cell is removed is used as the output of the delay circuit.

According to a second aspect of the present invention, an empty cell arriving first after every integer N-th cell with respect to a cell stream composed of real cells and empty cells constituting a path or a transmission line arriving at a delay circuit. It is characterized in that the cell section is removed, and the cell flow from which the empty cell is removed is used as the output of the delay circuit.

According to a third aspect of the present invention, a cell stream consisting of real cells and empty cells constituting a path or a transmission line arriving at a delay circuit is provided for every Nth integer and a predetermined number of cells following it. Are empty cells, at least one of the empty cell sections is removed , and the cell flow from which the empty cells have been removed is used as the output of the delay circuit.

[0016]

FIG. 1 is a block diagram showing a basic configuration of control means and a delay circuit for realizing the method of the present invention.

In the figure, the delay circuit is the same as the conventional FI.
It is composed of FO80. The FIFO 80 includes a write address generation circuit 81, a memory 82, and a read address generation circuit 83, and a cell write control signal 91,
Only the actual cells are stored in accordance with the input cell 92, the cell read control signal 93, and the clock 95, and the output cell 94 and the empty signal 96 are output.

According to the first aspect of the present invention, if the Nth cell is an empty cell, the control means 10 removes the empty cell section by the cell write control signal 91 indicating the presence or absence of a real cell arriving at the FIFO 80. Further, by controlling on / off of the cell read control signal 93 according to the state of the actual cell and the remaining empty cells, it is possible to moderately suppress the increase in the cell flow rate. That is, since the time compression of the cell flow is eased, the increase in the average speed and the peak speed can be reduced. In this case, the increase in the cell flow rate of the output cell 94 is 1 / N or less of the cell flow rate of the input cell 92.

According to the second aspect of the present invention, the control means 10 removes an empty cell section that arrives first after every Nth cell, so that an increase in the cell flow rate can be similarly suppressed appropriately. According to a third aspect of the present invention, the control means 1
When 0 is the Nth cell and a predetermined number of cells following it are empty cells, by removing at least one of the empty cell sections, the time compression of the region where the cell flow rate is large is eased to increase the peak speed. Can be suppressed.

Here, at the point B shown in FIG. 6, the time change of the cell flow rate after the path switching by the method of the present invention is shown in FIG.
Shown in

As shown in FIG. 9, empty cells are appropriately inserted and replaced with a time-compressed cell flow over a long period of time, so that a sharp rise in the cell flow rate can be avoided even after path switching.

[0022]

FIG. 2 is a block diagram showing an embodiment of the control means for realizing the method according to the first aspect of the present invention. In the figure, a FIFO 80 having a write address generation circuit 81, a memory 82 and a read address generation circuit 83, which is similar to the conventional configuration, receives a cell write control signal 91, an input cell 92, a cell read control signal 93 and a clock 95, and outputs Cell 94 and empty signal 9
6 is output.

A feature of the present invention is that, in this embodiment, the cell write control signal 91 and the empty signal 9
6, a cell clock 21, a time compression operation designating signal 22, and a cell read designating signal 2 indicating a cell division.
3 and a control means 10 for controlling the cell read control signal 93. The control means 10 includes a period counter 11, a gate circuit 12, a FIFO 13, and control circuits 14 and 15. Here, the cell clock 21 indicates a cell partition (period of cell length) extracted from an input cell stream composed of real cells or empty cells by a cell synchronization circuit or the like on the input side of the transmission device including the delay circuit. Signal.

The period counter 11 takes in the cell clock 21 and outputs a period pulse 24 at every period of an integer N times the cell clock 21. The gate circuit 12 outputs the time compression operation designating signal 2
When the cell write control signal 2 is ON, the cell write control signal 91 is turned off when the cell write control signal 91 is "0" indicating that the cell is an empty cell section at the position of the periodic pulse 24, and is turned on otherwise. I do. The FIFO 13 operating in synchronization with the cell clock 21 receives the write control signal 2
A write address generating circuit 16 for generating a write address corresponding to 5 and a cell write control signal as serial data in a region corresponding to the write address (“1” for a real cell, “0” for an empty cell) A) a memory 17 for storing a memory 91; and a read address generating circuit 18 for outputting a read address to the memory 17, and a cell read from the memory 17 in accordance with the read address.
An empty signal 27 is output when the read control bit string 26 runs out.

The control circuit 14 is turned on in response to the cell readout designation signal 23 input when the empty signal 27 is not given, and is turned on when the empty signal 27 is given or the cell readout designation signal 23 is not given. The read control signal 28 which is turned off is output. FI
The read address generation circuit 18 of the FO 13 stores the read address in the memory 1 according to the read control signal 28.
7 is output. When the empty signal 96 is not supplied from the FIFO 80, the control circuit 15
3, the cell read control bit read from the memory 17
The cell read control signal 93 is turned on when the data string 26 is "1" and turned off when the empty signal 96 is supplied or the cell read control bit string 26 is "0".

In such a configuration, the FIF
Only the actual cells are stored in the memory 82 of O80. However, when the time compression operation designating signal 22 is on and the cell readout designating signal 23 is off, the control means 10 controls the cell write control signal given as serial data. Of the cells 91, the array of real cells and empty cells from which empty cell sections arriving at the periodic position specified by the cycle counter 11 have been removed is "1".
And a bit string of “0”. Next, after recording the cell write control signal 91 of the transmission delay difference, by turning on the cell readout designation signal 23, the control circuit 14 turns on the readout control signal 28 until the empty signal 27 is given from the FIFO 13, FIFO
Cell from the memory 17 of the 13 were removed predetermined air cell sections
The readout control bit string 26 is output. Control circuit 1
In step 5, on / off control of a cell read control signal 93 applied to the read address generation circuit 83 of the FIFO 80 is performed in accordance with "1" and "0" indicating the presence or absence of a real cell in the cell read control bit string 26 . Therefore, the FIFO
From the memory 82 of 80, real cells and empty cells from which only empty cells arriving at the cycle position specified by the cycle counter 11 have been removed are output as output cells 94.

In this embodiment, when writing serial data (cell write control signal 91) indicating whether or not a real cell has arrived in the FIFO 13, data in an empty cell section at a predetermined periodic position is removed and recorded. The time is compressed by sequentially reading them out.
On the write side to O13, the serial data (cell write control signal 91) indicating whether or not a real cell has arrived is recorded as it is, and when reading it, an empty cell section is skipped periodically (read at a predetermined periodic position). When the serial data is "0", the next data is read from the FIFO 13).

Here, the principle of performing time compression by the above-described operation will be described with reference to FIG. FIG.
(a) shows the original cell flow of the path multiplexing the two virtual channels represented by VCa and VCb arriving at the delay circuit (FIFO 80). Solid arrows indicate real cells, and dashed arrows indicate empty cells. FIG. 3B shows a state where the empty cell section is removed when every Nth cell in the original cell flow is an empty cell. Here, although the empty cell corresponding to the periodic position 1 is removed and time compression is performed, the time compression is not performed at the periodic position 2 since a real cell arrives. That is, in the conventional configuration, all the empty cells are removed, and only the actual cells continuously increase at the time of reading, the cell flow rate increases at a time, and the average speed and the peak speed greatly increase. Since only the empty cell at the position is removed, the increase in the cell flow rate is appropriately suppressed, and the increase in the average speed and the peak speed can be moderated. Also, by setting the empty cell removal interval N sufficiently large, the increase in the cell flow rate at the output of the delay circuit can be suppressed to an extremely small value. For example, N = 100
Then, the increase in the cell flow rate can be suppressed to 1% or less. However, the time required to release all the real cells of the transmission delay difference accumulated in the delay circuit is 100 times or more as compared with the conventional method of continuously reading the real cells.
According to the above-described principle, in addition to the method of recording whether or not a real cell has arrived as a bit string of "0" and "1", the empty cell except for the real cell and every Nth empty cell is directly stored in the FIFO 80. Can be realized by writing the data.

Further, when every Nth cell and a predetermined number of cells following it are empty cells, if the cell flow from which one empty cell is removed is used as the output of the delay circuit, an area with a large cell flow rate can be obtained. In this case, removal of empty cells is reduced, and an increase in peak speed can be effectively suppressed (the invention according to claim 3). FIG. 4 is a block diagram showing an embodiment of the control means for realizing the method according to the second aspect of the present invention.

In this embodiment, the cell write control signal 9 is replaced with the gate circuit 12 of the embodiment shown in FIG.
1, a control circuit 31 for inputting a cell clock 21, a time compression operation designating signal 22 and a periodic pulse 24 and outputting a write control signal 41 is provided. The other components are the same as those of the embodiment shown in FIG. . That is, the control circuit 3
1 is OFF when the time compression operation designating signal 22 is ON and the cell write control signal 91 first becomes “0” indicating that it is an empty cell section from the time when the periodic pulse 24 is input. , And outputs a write control signal 41 which is turned on in other cases. Other operations are the same as those of the embodiment shown in FIG.

Here, the principle of time compression in this embodiment will be described with reference to FIG. FIG. 5 (a) shows the original cell flow of a path multiplexing two virtual channels represented by VCa and VCb arriving at the delay circuit (FIFO 80). Solid arrows indicate real cells, and dashed arrows indicate empty cells. FIG. 5B shows a state in which the empty cell section that first arrives after every Nth cell in the original cell flow has been removed. Here, the first empty cell after the Nth cell position 1 and the first empty cell after the next Nth cell position 2 are removed and time compression is performed. As described above, in the present invention, only the empty cell that arrives first after every Nth cell is removed, so that the increase in the cell flow rate is appropriately suppressed, and the increase in the average speed and the peak speed can be moderated. Also, by setting the empty cell removal interval N sufficiently large, the increase in the cell flow rate at the output of the delay circuit can be suppressed to an extremely small value.

A fixed window is provided in the vicinity of each Nth cell position in the original cell flow, and if there is no empty cell in the window, the removal of the empty cell is stopped in the vicinity of the cell position to thereby reduce the peak. An increase in speed can be effectively suppressed.

[0033]

As described above, according to the present invention, the cell flow obtained by periodically removing empty cells from the cell flow input to the delay circuit is used as the output of the delay circuit. On the other hand, the increase in the cell flow rate per unit time of the delay circuit output can be reduced. Therefore, it is possible to minimize the increase in the average speed and the peak speed of the VC when switching the path or the transmission path. Moreover,
Since the original cell flow is time-compressed for a long time, it is possible to obtain the same effect of compressing the transmission delay difference as in the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration example of a control unit and a delay circuit for realizing a method of the present invention .

FIG. 2 is a block diagram showing a configuration of an embodiment of the invention described in claim 1;

FIG. 3 is a diagram for explaining the principle of time compression according to the first aspect of the present invention;

FIG. 4 is a block diagram showing a configuration of an embodiment of the invention described in claim 2;

FIG. 5 is a diagram for explaining the principle of time compression according to the second aspect of the present invention;

FIG. 6 is a diagram illustrating an example of the configuration of a path that performs non-stop switching.

FIG. 7 is a diagram showing a change over time in a cell flow rate at a point A before path switching.

FIG. 8 is a diagram showing a time change of a cell flow rate at a point B after the path switching.

FIG. 9 is a diagram showing a time change of a cell flow rate at a point B after path switching according to the method of the present invention.

FIG. 10 is a block diagram illustrating a configuration example of a conventional delay circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 control means 11 cycle counter 12 gate circuit 13 FIFO 14, 15 control circuit 16 write address generation circuit 17 memory 18 read address generation circuit 31 control circuit 61 path switch 62 active path 63 backup path 64 delay circuit 80 FIFO 81 write address Generator 82 Memory 83 Read address generator

Continuation of front page (56) References JP-A-1-270427 (JP, A) JP-A-1-286645 (JP, A) JP-A-2-67849 (JP, A) JP-A-3-216043 (JP) JP-A-4-361443 (JP, A) JP-A-4-361442 (JP, A) JP-A-4-369140 (JP, A)

Claims (3)

(57) [Claims] 1. An active system for transmitting an information sequence in units of cells.
Backup path with smaller transmission delay than path or working transmission path
Alternatively, it is provided in the protection transmission line and the working path or the working transmission
Path or transmission path from the path to the protection path or protection transmission path
A cell flow control method for a delay circuit that stores and discharges cells to absorb a transmission delay difference between paths or transmission paths when switching is performed , wherein a real cell constituting a path or a transmission path arriving at the delay circuit is provided. And a cell stream comprising an empty cell, wherein, if every Nth integer cell is an empty cell, the empty cell section is removed, and the cell stream from which the empty cell is removed is used as the output of the delay circuit. Flow control method. 2. An active system for transmitting an information sequence in units of cells.
Backup path with smaller transmission delay than path or working transmission path
Alternatively, it is provided in the protection transmission line and the working path or the working transmission
Path or transmission path from the path to the protection path or protection transmission path
A cell flow control method for a delay circuit that stores and discharges cells to absorb a transmission delay difference between paths or transmission paths when switching is performed , wherein a real cell constituting a path or a transmission path arriving at the delay circuit is provided. And a cell stream comprising empty cells, wherein an empty cell section that arrives first after every Nth integer cell is removed, and the cell stream from which the empty cells have been removed is used as an output of the delay circuit. Control method. 3. An active system for transmitting an information sequence in units of cells.
Backup path with smaller transmission delay than path or working transmission path
Alternatively, it is provided in the protection transmission line and the working path or the working transmission
Path or transmission path from the path to the protection path or protection transmission path
A cell flow control method for a delay circuit that stores and discharges cells to absorb a transmission delay difference between paths or transmission paths when switching is performed , wherein a real cell constituting a path or a transmission path arriving at the delay circuit is provided. When at least one cell every integer Nth and a predetermined number of cells following it are empty cells, at least one empty cell section is removed.
A cell flow from which empty cells have been removed as an output of the delay circuit.