JPH02303246A - Cell switch - Google Patents

Abstract

PURPOSE:To obtain a cell switch not causing cell abort at the input of a cell to an output buffer by using buffer full information representing whether or not the output buffer has an area capable of storing a newly inputted cell and selecting the cell outputted from an input buffer. CONSTITUTION:An output cell selection means 24 analyzes the inputted cell store information and detects blocking generated when a cell including the path information in the cell store information is inputted to a nonblocking type switch means 13. In order to avoid the detected blocking, from which input buffer a cell is outputted is decided and whether or not a cell output is permitted to each input buffer is noticed. When a cell is not newly stored in the output buffer, the output selection means 24 does not permit the cell output to the input buffer.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a hardware packet switch, and in particular to an ATM that performs information communication using fixed-length short packets called cells. This invention relates to cell switches used in communication systems.

(Prior art) In recent years, STM (Synchronous Trans
In place of ['erMode], the communication terminal uses the information transmission capability of the communication network when necessary.ATM (AsyMode)
Interest and expectations for ncbronous Transl'ar Mode) are increasing.

ATM transmits information using fixed-length short packets called cells, and each communication terminal passes cells to the communication network as needed.In other words, the communication terminal uses the information transmission capacity of the communication network when necessary. This is a transmission mode characterized by the following.

Because of the above-mentioned characteristics, ATMs can provide communication terminals with any information transmission capability that they require;
Since the communication terminal can pass only significant information to the communication network, there is an advantage that communication efficiency can be improved.

For this reason, ATM has replaced STM with voice, data,
It is attracting attention as a basic technology for constructing a communication network that can centrally handle videos, etc., that is, a B-I SDN network.

In order to configure an ATV communication network, it is necessary to realize a function of outputting cells delivered from a plurality of input communication channels to a desired output communication channel according to the route information, that is, a cell switch. At this time, since the communication terminal uses the information transmission capacity of the communication network when necessary, multiple cells simultaneously go to the same output communication path, that is, blocking occurs.

When blocking occurs, one of the cells causing blocking is transferred to the output channel, and the remaining cells are temporarily stored in a buffer to avoid the problem.

Although various methods can be considered to avoid this blocking, the blocking avoidance method greatly affects the performance of the switch, and it is desired to develop a cell switch to which an efficient blocking avoidance method is applied.

Among the cell switches that have been proposed in the past, the present inventor published the Institute of Electronics, Information and Communication Engineers Technical Research Report, Information Network,
A cell switch that belongs to a class called the centralized collision avoidance type input buffer system reported in ``A Comparative Study of ATM Switch Architecture'' (January 27, 1989) is a cell switch that A buffer for collision avoidance, that is, an input buffer, is provided at the input section, and cell collision detection is performed intensively at the output section of the switching element, and blocking avoidance is achieved by feeding back cell collision information to the input buffer. be. This method can keep the operating speed required for the buffer lower than the output buffer method or common buffer method, so it is an easy method to configure a wideband cell switch that accommodates input/output communication paths of 150 Mbps or more. It is. Furthermore, priority control based on route information, that is, simple FIFO (PlrsL IN First Out
) Transfer efficiency and buffer usage efficiency can be improved by performing an operation of selecting and outputting as many cells that do not cause blocking from among the cells stored in the buffer of the input section as possible, rather than controlling.

Another method that has traditionally been proposed to avoid blocking is to improve the operating speed inside the cell switch.
This is a method in which cells are switched within the switch faster than cells are transferred on the input/output communication path. When this method is adopted, it is necessary to provide a buffer, ie, an output buffer, at the output section of the cell switch.

However, if the operating speed inside the cell switch is improved in the cell switch using the centralized collision avoidance type input buffer method that has been proposed in the past, input exceeding the capacity of the output buffer will occur and the output buffer will be overloaded. Cell discard occurs during cell input. According to subsequent research by the present inventor, in a switch using a centralized collision avoidance type input buffer system, when the operating speed inside the cell switch is improved, the main cause of deterioration in the performance of the cell switch is the increase in the output buffer to the output buffer. It turned out that the cell was discarded when the cell was input.

(Problems to be Solved by the Invention) As described above, in a cell switch using a centralized collision avoidance type input buffer method, the main causes of deterioration in the performance of the cell switch when the operating speed inside the cell switch is improved are as follows. This is cell discard at the time of cell input to the output buffer.

The present invention has been made in view of the above points, and its purpose is to provide a cell switch using a centralized collision avoidance type input buffer system, which improves the operating speed inside the cell switch, and which improves the internal operation speed of the cell switch. To provide a cell switch that does not discard cells when cells are input.

[Structure of the invention]

(Means for Solving the Problems) The present invention, which has been made to achieve the above object, receives cells delivered from a plurality of input communication channels and accommodates them according to the route information of the cells received from the input communication channels. A cell switch that selects one of the plurality of output communication paths that are connected to the input communication path and outputs the cells received from the input communication path to the selected output communication path is provided corresponding to the input communication path, and outputs the cells received from the input communication path to the selected output communication path. A non-blocking type that includes a plurality of input buffers that temporarily store cells to be delivered, and a non-blocking type that receives cells from the input buffers and transfers the cells faster than the cell transfer speed on the input/output communication path according to the route information held by the received cells. a switch means, and a plurality of switch means, which are provided corresponding to the output communication path, receive cells from the non-blocking switch means, temporarily store the cells, and output the cells to the corresponding output communication path when the corresponding output communication path is capable of transferring cells. an output buffer, cell route information stored in each of the input buffers,
As a cell that inputs buffer full information of each output buffer and outputs it from each input buffer to an output communication path, there is no collision with other cells at the output section of the non-blocking switch means, and the route information of the cell is output cell selection means for selecting a cell that is determined to have storage capacity in the destination output buffer according to the method of the present invention.

(Operation) According to the present invention, the output cell selection means collects the cell accumulation information in the input buffer, the cell collision information at the output section of the non-blocking switch means created by the output cell selection means, and the output buffer Cells to be output from the input buffer are selected using buffer full information indicating whether the input buffer has an area that can store the input cells, which improves the internal operation speed of the cell switch. In a buffer type cell switch, no cells are discarded when cells are input to the output buffer.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a cell switch 1 with 8 inputs and 8 outputs, which is an embodiment of the present invention.

In the same figure, elements 3 to 10 are provided corresponding to input communication channels, and input buffers that temporarily store cells delivered from the input communication channel, and 13 receives cells from the input buffers, and indicates the route of the received cells. Non-blocking switch means 15 to 22, which transfer cells faster than the cell transfer speed on the input/output communication path according to information, are provided corresponding to the output communication path, and receive cells from the non-blocking switch means 13, temporarily store them, and then process them. Element 24 is an output buffer for outputting cells when the output communication path is capable of transferring cells, and element 24 is connected to each of the input buffers 3 to 1.
0 cell accumulation information, cell collision information at the output section of the non-blocking switch 13, and each output buffer 1.
This is output cell selection means for selecting cells to be output from the input buffer based on the buffer full information of 5 to 22.

Next, the operation of the cell switch 1 according to the embodiment of the present invention having such a configuration will be described in detail.

In the cell switch 1 of this embodiment, the output cell selection means 24
Cell switching is performed by repeating the collision avoidance phase, which is mainly performed by the non-blocking switch means, and the cell transfer phase, which is mainly performed by the non-blocking switch means.

That is, cells delivered through the input communication path are first stored in each buffer 3 to 10 provided corresponding to each input communication path.

A collision avoidance phase is performed before outputting cells from the input buffer during a certain cell transfer phase.

The collision avoidance phase is a phase in which cells to be output from the high-power buffer are determined in advance so that blocking of cells at the input section of the output buffer does not occur, and is executed as follows.

First, from among the cells accumulated in each input buffer, one cell that is a candidate for output is selected according to a predetermined method using priority control based on route information, which will be described later. Thereafter, the cell storage information including at least route information, which is information specifying the output communication path of the selected cell, is output to the output cell selection means 24.

The output cell selection means 24 analyzes the inputted cell storage information, detects blocking that occurs when a cell whose route information is included in the cell storage information is input to the non-blocking switch means 13, and In order to avoid blocking, it is determined which input buffer should output the cell, and each input buffer is notified whether or not to allow cell output. Here, the output selection means 24 further receives from each output buffer buffer full information indicating whether or not the output buffer has an area where new cells can be stored, and if the output buffer cannot store new cells, The input buffer that is attempting to output cells to the output buffer is not permitted to output cells.

After the collision avoidance phase ends, a cell transfer phase is executed. The cell transfer phase is a phase in which a cell output from an input buffer is transferred to an output buffer corresponding to a desired output communication path according to the route information of the cell, and is executed as follows.

The input buffer that is permitted to output cells outputs the cell selected as a candidate for the cell to be output to the non-blocking switch means 13. The non-blocking switch means 13 transfers the cell to an output buffer corresponding to a desired output communication channel according to the received cell route information. In the cell switch 1 of this embodiment, the time required to execute the cell transfer phase is shorter than the time required to transfer cells on the input/output communication path.

Each output buffer outputs cells when the output buffer is accumulating cells and when the output communication path corresponding to the output buffer is capable of transferring cells.

In the embodiment of the present invention described above, the part that mainly executes the collision avoidance phase and the part that mainly executes the cell transfer 7A are configured to be different, so that during the execution of the cell transfer phase, , executes a collision avoidance phase and selects a cell to be output from the input buffer in the next cell transfer phase. That is, the collision avoidance phase and the cell transfer phase are executed as a vibe line. By executing the collision avoidance phase and the cell transfer phase in a vibrating manner in this way, it becomes possible to execute the next cell transfer phase immediately after the end of one cell transfer phase, and efficient cell switching is achieved. realizable.

Furthermore, priority control based on route information is performed by repeating the collision avoidance phase multiple times during the time required to execute one cell transfer phase.Priority control based on route information is performed by following the following algorithm. do.

In the first collision avoidance phase, the oldest cell among the cells stored in each input buffer is selected as an output cell candidate, and cell storage information including the route information of the cell is selected. is passed from each input buffer to the output cell selection means to execute a collision avoidance phase, and then, in the n-th collision avoidance phase, the n-1th
The input buffer whose output is allowed in the collision avoidance phase up to 1st time creates cell storage information including the route information of the cell whose output is allowed, and For input buffers whose output is not permitted, among the cells stored in the input buffer, the nth oldest cell stored in the input buffer is selected as the cell that contains the route information of the cell as a candidate for the output cell. The collision avoidance phase is executed by repeating the process of creating accumulated information and having the output cell selection means receive the cell accumulated information generated in each input buffer a predetermined number of times.

FIG. 2 is a diagram showing the configuration of the non-blocking switch means 13 in this embodiment. As shown in the figure,
The non-blocking switching means 13 is realized by a non-blocking multi-stage self-routing network known as a Batcher-Omega network.

As is well known, the bit string shown in Figure 4,
In other words, the cell is non-blocking as a bit string in which an empty cell indicator bit indicating whether the bit string contains a cell or not and an output port address, which is a bit string specifying the output communication path to which the cell is directed, are added in front of the cell bit string. type switch means 13. As is well known, in this case, if there are no cells going to the same output communication path, the Batcher-Omega network forming the non-blocking switch means 13 becomes a non-blocking cell switch.

Here, the batcher network has a function of sorting the input cells according to the size relationship of the output port addresses of the input cells, and the omega network sorts the input cells to the output port specified by the output port address. It has a routing function to guide you. In addition, although the strategy information of cells input to each input buffer and the output port address are normally different bit strings, their correspondence is determined at the time of call setup performed by the communication system to start communication. , the input buffer stores a conversion table between route information and output port address, and when the input buffer receives a cell, it learns the output port address of the cell from the route information of the received cell and converts the output port address to the output port address. The address is attached to the received cell and stored.

In the cell transfer phase, in the cell bit format shown in FIG. 4, an empty cell indicating bit is added to the head of the bit string in case there is a large buffer that does not have cells to be output. The empty cell display bit becomes 0 when the following bit string contains a cell, and becomes 1 when it does not. In this case, sorting in the batcher network is performed including the empty cell indication bit, and routing in the omega network is performed with the empty cell indication bit being 0.
The path taken by a bit string whose empty cell indication bit is 1 is not affected by the path taken by a bit string whose empty cell indication bit is 1.

The unit switch 26 of the batcher network shown in FIG. 2 has a straight state shown in FIG. 9 and a cross state shown in FIG. 10 as connection states, and operates as shown in FIG. 11. That is, at the start of the cell transfer phase, the unit switch 26 is set to the straight state shown in FIG. 9, and each bit of the two bit strings is sequentially input to the unit switch. The unit switch 26 compares the two input bits while outputting them. When these bits differ for the first time, the bit string containing 1 is switched to the unit switch 26 in FIG.
In the direction of the arrow shown above, the cross state or straight state is selected as the state of the unit switch 26 so that the bit string containing 0 is output in the opposite direction to the direction of the arrow.

Further, the unit switch 28 of the omega network shown in FIG. 2 operates as shown in FIG. 12.

That is, each bit of the two bit strings is sequentially input to each unit switch 28, and each unit switch 28 switches to a cross state or a straight state according to the truth table shown in FIG. 13 depending on the state of the first two bits of the input bit string. Select a state. According to the selected state, the first bit and the third and subsequent bits of the input bit string are output in order, that is, the second bit is deleted and output.

FIG. 3 is a diagram showing the configuration of the output cell selection means 24 in this embodiment. Next, the collision avoidance phase executed using the output cell selection means 24 will be explained in detail using the same figure. The collision avoidance phase is comprised of an output permission determination phase and an output permission notification phase following the output permission determination phase.

The output permission determination phase is executed as follows.

The output cell selection means 24 receives cell accumulation information having the structure shown in FIG. 5 from each input buffer at the start of the output permission determination phase. The Q1 switches 26 of the batcher network in the output cell selection means 24 are all set to the straight state. When the valid bit of cell storage information is 0, it indicates that the input buffer that outputs the cell storage information has a cell candidate to be output, and when it is 1, it indicates that it does not have a cell candidate to output. are shown respectively.

The cell storage information input to the output cell selection means 24 is first processed in a batcher network from the valid bit and output port address at the head of the cell storage information, and also from the plurality of cells that cause blocking when blocking occurs. Sorting is performed according to priority control information used to select one cell to output. Here, the unit switch 26 of the batcher network within the output cell selection means 24 is
Since the same unit switch as the unit switch 26 of the batcher network constituting the non-blocking switch means 13 can be used, the same unit switch 26 can also be used in this embodiment.
It is configured using

The sorted cell storage information is input to a collision detection circuit, and blocking detection is performed.

The collision detection circuit has a configuration in which comparison means 30 are connected in cascade. Each comparison means 30 notifies the output port address of the received cell storage information to the comparison means below it, and also compares the output port address notified from the comparison means above it with its own output port address. do. If they match, blocking will occur, so the cell will not be output from the input buffer that outputs the cell storage information, and this will change the valid bit of the input cell storage information from 0 to 1. This is achieved through change. In addition, if the output port address notified from the comparison means above itself is different from the output port address owned by the user, the cell selected as a candidate to be output from the input buffer that outputs the cell accumulation information is output. In this case, the effective bit is not changed.

Note that the valid bit is 1 at the time of input to the comparing means 30.
The cell accumulation information is collected at the bottom of the collision detection circuit by the action of the batcher network, but in this case, the input buffer that outputs the cell accumulation information does not have any cells to output, so of course No output permission is granted.

In addition, the order in which the cell accumulation information is input to the collision detection circuit is the valid bit, output port address, and priority control information as shown in Figure 5, so the individual inputs are input at the start of the collision avoidance phase. By providing unique priority control information to the buffer, the selection of the cell storage information input to the collision detection circuit that should be permitted from among the plurality of cell storage information that causes blocking can be made based on the priority control information. It is determined. In the embodiment shown in FIG. 3, the one with the smallest value of the priority control information is selected from among the ones that are causing blocking. Furthermore, in this embodiment, by changing the priority control information given to each input buffer for each collision avoidance phase, the probability of cells being output from each input buffer is made fair.

After blocking detection is performed by the collision detection circuit, the cell storage information is passed through the inverse Banyan network and the Banyan network to the loopback circuit 3 provided for each output buffer.
2 is input. The cell accumulation information output from the collision detection circuit has the structure shown in FIG. In the Banyan network, routing is performed using the output port address in the cell storage information.

The inverse Banyan network is a self-routing multi-stage network established to avoid blocking within the Banyan network connected next to the inverse Banyan network. The cell storage information is routed while referring to the intermediate boat address added to the intermediate boat address. Here, the unit switches 28 constituting the Banyan network and the inverse Banyan network constitute an omega network of non-blocking switching means.
The same switch 28 can be used, and is also used in this embodiment. Furthermore, cell storage information with a valid bit of 1 does not disturb the path of cell storage information with a valid bit of 0.

Note that the intermediate boat address is created as follows.

That is, when each comparison means 30 of the collision detection circuit compares output port addresses and outputs cell accumulation information, the valid bits are set to 0 and numbers are assigned in order from the top. This number is expressed as a binary number, and a bit string with the bit order reversed is used as an intermediate boat address. For example, each comparison means 30 has an adder, the addition result of the adder is displayed on the comparison means below it, and one of the two inputs of the adder is the addition result displayed by the comparison means above. This can be done by inverting the valid bits for the other input. Here, one of the inputs of the comparison means located at the top is O, and the other is an inverted valid bit.

In the loopback circuit 32, as shown in FIG. 7, there is a cell storage 1*? consisting of valid bits and input port addresses, from which intermediate boat addresses and output port addresses have been deleted by the inverse Banyan network and Banyan network. ! is input.

The folding circuit 32 reflects buffer full information indicating whether or not each output buffer can newly accumulate cells on the input cell accumulation information.

Specifically, the folding circuit 32 that receives the cell accumulation information whose valid bit is 0 refers to the buffer full information of the output buffer provided corresponding to the folding circuit,
If the buffer is full, that is, there is no area for storing new cells, the valid bit of the received cell storage information is changed to 1.

Thereafter, each loopback circuit 32 passes the received cell storage information via the path 101 to the large power buffer to which the loopback circuit is connected. This completes the output permission determination phase.

After the output permission determination phase, an output permission notification phase is executed.

The output permission notification phase is started by inputting the cell accumulation information received by the input buffer at the end of the output permission determination phase to the batcher network in the output cell selection means 24. The batcher network sorts the input cell storage information based on the valid bits of the input cell storage information and the input port address, which is information that specifies the input buffer that outputs the cell storage information, and sends the input cell storage information to a collision detection circuit. input into each comparison means 30.

Each comparison means 3 of the collision detection circuit inputted with cell accumulation information
In step 0, the same operation as performed on the valid bit and output port address in the output permission determination phase is performed on the valid bit and input port address of the received cell storage information, and further, in the output permission determination phase. Similarly, an intermediate boat address is created, and the cell storage information is rewritten as shown in FIG. 8 and input to the inverse Banyan network and Banyan network. Here, in the - times collision avoidance phase, one high-power buffer always outputs only one cell accumulation information, so that in the output permission notification phase, blocking is not detected by the collision detection circuit.

In the inverse Banyan network and the Banyan network, input cell storage information is routed using the valid bits, intermediate boat address, and input port address of the cell storage information, and is passed to the return circuit 32.

The return circuit 32 passes the passed cell accumulation information to the connected input buffer. At this time, the cell storage information contains only valid bits. This ends the output permission notification phase. Each input buffer has
Whether output is permitted for a candidate cell to be output is reflected in the valid bit of the received cell storage information.

That is, if the valid bit of the cell storage information is 0, output is permitted, and if the valid bit is 1, either there is no candidate cell to output, or output is not permitted. It corresponds to that.

The input buffer that receives the cell storage information whose valid bit is 1 outputs its permitted output candidate cells in the next cell transfer phase as described above.

As is clear from what has been described above, in this embodiment, when giving output permission to each input buffer, information about the storage margin of the output buffer is also considered, so when cells are input to the output buffer, , no cells are discarded due to the full state of the buffer.

The embodiments of the present invention are not limited to those described above, and various other embodiments are possible.

For example, it is not always necessary to execute the collision avoidance phase and the cell transfer phase in a pipelined manner, and it is not necessarily necessary to perform priority control based on route information.

Even in these cases, the unique effects of the present invention can be equally achieved.

〔Effect of the invention〕

As described above, according to the present invention, the output cell selection means stores cell accumulation information in the input buffer, cell collision information at the output section of the non-blocking switch, and cells newly received by the output buffer. Cells to be output from the input buffer are selected using buffer full information that indicates whether or not there is available space, which improves the internal operation speed of the cell switch. In a cell switch using a collision avoidance buffer system, no cells are discarded when inputting cells to an output buffer, and a high-performance cell switch can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cell switch according to an embodiment of the present invention, FIG. 2 is a block diagram of a non-blocking switch according to an embodiment of the present invention, and FIG. 3 is an output cell selection diagram according to an embodiment of the present invention. fM configuration diagram of the means FIGS. 4 to 8 are diagrams showing the bit format of cells handled inside the cell switch which is an embodiment of the present invention, FIGS. 9 and 10,
11 and 12 are diagrams explaining the operation of the unit switch used in one embodiment of the present invention, FIG. 13 is a diagram explaining the operation of the unit switch of the Omega network, the Inverse Banyan network, and the Banyan network, It is. 1...Cell switch 3.4, 5.6, 7, 8゜9.10...Input buffer 13...Non-blocking switch means 15, 1
6. 17. 18. 19°20.21.22...
Output buffer 24...Output cell selection means 26.28...Unit switch 30...Comparison circuit 32...Folding circuit fee B patent attorney Hidetoshi Miyoshi Effective shaft input °−) 7) 'Response Figure 7 Figure 1-48

Claims (1)

[Claims] Cells delivered from a plurality of input communication channels are received, one of the plurality of output communication channels accommodated is selected according to the route information of the cell received from the input communication channel, and the input communication A cell switch that outputs cells received from a channel to the selected output communication channel, the cell switch comprising: a plurality of input buffers provided corresponding to input communication channels and temporarily storing cells delivered from the corresponding input communication channels; non-blocking switch means that receives a cell from the input buffer and transfers the cell faster than the cell transfer rate on the input/output communication path according to the route information of the received cell; a plurality of output buffers that receive cells from a switching means, temporarily store them, and output the cells to a corresponding output communication path when the corresponding output communication path is capable of transferring the cells; Directional information and
As a cell that inputs buffer full information of each output buffer and outputs it from each input buffer to an output communication path, there is no collision with other cells at the output section of the non-blocking switch means, and the route information of the cell is 1. A cell switch comprising: output cell selection means for selecting a cell determined to have storage capacity in an output buffer at a destination.