JP2895508B2 - Cell switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a hardware-based packet switch, and particularly to an ATM that performs information communication using fixed-length short packets called cells. The present invention relates to a cell switch used in a communication system.

(Prior art) This is a transmission mode used in the existing telephone network in recent years. A communication terminal is required instead of STM (Sycnhronous Transfer Mode), which secures the information transmission capacity required for communication at the time of call setup. ATM that uses the information transmission capacity of the communication network when
(Asynchronous Atransfer Mode) and interest are growing.

ATM transmits information using fixed-length short packets called cells, and each communication terminal hands over cells to the communication network as needed, that is, the communication terminal uses the information transmission capacity of the communication network when needed. Transmission mode.

Due to the above-mentioned features, the ATM can provide the communication terminal with any information transmission capability required by the communication terminal,
Since the communication terminal can pass only significant information to the communication network, there is an advantage that communication efficiency can be improved.

For this reason, ATM is a communication network that can handle voice, data, moving images, etc. in a unified manner instead of STM, that is, B
-It has been spotlighted as a basic technology for constructing ISDN networks.

In order to configure an ATM communication network, it is necessary to realize a function of outputting cells delivered from a plurality of input communication channels to a desired output communication channel according to the route information, that is, a cell switch. At this time, since the communication terminal uses the information transmission capability of the communication network when necessary, a plurality of cells are simultaneously directed to the same output communication path, that is, blocking occurs. If blocking occurs, transfer one of the blocking cells to the output channel,
The remaining cells are avoided by temporarily storing them in a buffer. Various methods are conceivable for the blocking avoidance method. The blocking avoidance method greatly affects the performance of the switch, and it is desired to develop a cell switch to which an efficient blocking avoidance method is applied.

Among the cell switches that have been proposed in the past, the present inventor reported in IEICE Technical Report, Information Network, IN88-119, "Comparison of ATM Switch Architecture" (January 27, 1989) Cell switch belonging to the class called the concentrated collision avoidance type input buffer method
A buffer for avoiding collision, that is, an input buffer, is provided at the input of the switching element that performs cell switching, cell collision detection is performed centrally at the output of the switching element, and cell collision information is fed back to the input buffer. This is a method of avoiding blocking. This method is
Since the operation speed required for the buffer can be suppressed lower than the output buffer method and the common buffer method,
This is a method that can easily configure a wideband cell switch accommodating an input / output communication path of 150 Mbps or more. Furthermore, priority control based on route information, that is, simple FIFO (First IN First Ou)
t) By performing not the control but the operation of selecting and outputting as many cells that do not cause blocking from the cells stored in the buffer of the input unit as possible, the transfer efficiency and the buffer use efficiency can be improved.

Another method conventionally proposed as a method of avoiding blocking is to increase the operation speed inside the cell switch and perform cell switching inside the switch earlier than cells are transferred on the input / output communication path. . When this method is adopted, it is necessary to provide a buffer, that is, an output buffer at the output section of the cell switch.

However, in the conventionally proposed cell switch of the concentrated collision avoidance type input / output buffer method, when the operation speed inside the cell switch is improved, an input exceeding the capacity of the output buffer is performed, and the output buffer is transferred to the output buffer. When a cell is input, cell discard occurs. According to a subsequent study by the present inventors, in the switch of the concentrated collision avoidance type input buffer type, when the operation speed inside the cell switch is increased, the main cause of the performance degradation of the cell switch is that the output buffer is connected to the output buffer. It was found that the cell was discarded at the time of cell input.

(Problems to be Solved by the Invention) As described above, in the cell switch of the concentrated collision avoidance type input buffer system, when the operation speed inside the cell switch is improved, the main cause of lowering the performance of the cell switch is as follows. This is cell discarding when cells are input to the output buffer.

The present invention has been made in view of the above points, and an object of the present invention is to provide a concentrated collision avoidance type input buffer type cell switch in which the operation speed inside the cell switch is improved, and An object of the present invention is to provide a cell switch that does not cause cell discarding at the time of cell input.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, a cell switch according to the present invention is provided corresponding to each of a plurality of input communication paths,
A plurality of input buffers for storing ATM cells transmitted from these input communication paths, connected to these input buffers, and receiving, from the plurality of input buffers, the stored ATM cells from which transfer is permitted among the plurality of input buffers; A configuration in which a plurality of received ATM cells are transferred to at least one of a plurality of output communication paths in the same phase and at a speed higher than a cell transfer rate on the output communication path in accordance with route information of the ATM cells. And the ATM cell connected to the switch means and transferred at a speed higher than the cell transfer rate on the output communication path, and stores the ATM cell on the output communication path in the corresponding output communication path. A plurality of output buffers for outputting the ATM cells at a transfer rate; and a plurality of input buffers connected between the plurality of output buffers and the plurality of input buffers. From each of the plurality of output buffers, information indicating the ATM cell holding state of the output buffer is input in the same phase, and the route information of one of the ATM cells stored in the input buffer is input from each of them. Based on the input route information and the information indicating the holding status, the ATM cell is transferred by the switch means without collision with other ATM cells, and corresponds to the output communication path to which the ATM cell is to be transferred. Output cell selection means for notifying each input buffer whether or not transfer of the ATM cell by the switch means is permitted when it is determined that the output buffer has sufficient storage capacity. It is characterized by the following.

(Operation) According to the present invention, the switch means converts the ATM cells of the plurality of input buffers into the same phase (for example, the cell transfer phase).
The output cell selecting means inputs the ATM cell route information in the plurality of input buffers and the ATM cell holding information in the plurality of output buffers in the same phase (for example, the output permission decision phase). Based on this information, if there is no collision of ATM cells and there is room for storage in the output buffer, cell transfer by the switch means is permitted, so that cell discarding at the time of cell input to the output buffer is avoided. At the same time, the operation speed inside the switch can be improved, that is, high throughput can be achieved.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an 8-input / 8-output cell switch 1 according to an embodiment of the present invention. In the figure, elements 3 to 10 are provided corresponding to the input communication path,
An input buffer 13 for temporarily storing cells delivered from the input channel, receives the cells from the input buffer, and transfers the cells faster than the cell transfer rate on the input / output channel according to the route information of the received cells. The non-blocking type switch means, elements 15 to 22, are provided corresponding to the output communication path, receive the cells from the non-blocking type switch means 13, temporarily store the cells, and output the cells when the corresponding output communication path can transfer the cells. Buffer, element
24 is the cell accumulation information of each of the input buffers 3 to 10;
Output cell selection means for selecting a cell to be output from an input buffer based on cell collision information at the output unit of the non-blocking type switch 13 and information indicating an ATM cell holding state such as buffer full information of each of the output buffers 15 to 22. ,.

Next, the operation of the cell switch 1 having such a configuration according to the embodiment of the present invention will be described in detail.

In the cell switch 1 of this embodiment, the output cell selecting means 24
The cell switching is performed by repeating the collision avoidance phase mainly performed by the non-blocking type switch means and the cell transfer phase mainly performed by the non-blocking type switch means.

That is, the cells delivered on the input communication path are first temporarily stored in the buffers 3 to 10 provided corresponding to the respective input communication paths.

In a certain cell transfer phase, a collision avoidance phase is executed before outputting a cell from the input buffer.

The collision avoidance phase is a phase in which cells output from the input buffer are determined in advance so that cell blocking does not occur at the input portion of the output buffer, and is executed as follows.

First, one of the cells stored in each input buffer is selected as a cell to be output according to a predetermined method using priority control based on route information described later. afterwards,
The cell storage information including at least the route information which is the information for specifying the output communication channel of the selected cell is output to the output cell selection means 24.

The output cell selection unit 24 analyzes the input cell storage information, detects blocking that occurs when a cell including the path information of the cell storage information is input to the non-blocking type switch unit 13, and detects the detected In order to avoid blocking, it is determined from which input buffer the cell should be output, and each input buffer is notified of whether the output of the cell is permitted or not. Here, the output cell selection means 24 further receives buffer full information from each output buffer indicating whether or not the output buffer has an area where a new cell can be stored, and if the output buffer cannot store a new cell. It is assumed that cell output is not permitted to an input buffer that is to output cells to the output buffer.

After the end of the collision avoidance phase, a cell transfer phase is executed. The cell transfer phase is a phase of transferring a cell output from the input buffer to an output buffer corresponding to a desired output communication path according to the route information of the cell,
It is performed as follows.

The input buffer permitted to output the cell outputs the cell selected as the above-described cell candidate to be output to the non-blocking switch unit 13. The non-blocking type switch means 13 transfers the cell to an output buffer corresponding to a desired output communication path according to the received path information of the cell. In the cell switch 1 of the present embodiment, the time required to execute the cell transfer phase is shorter than the time required for cell transfer on the input / output communication path.

Each output buffer outputs a cell when the output buffer stores the cell and the output communication path corresponding to the output buffer can transfer the cell.

In the embodiment of the present invention described above, the part that mainly executes the collision avoidance phase and the part that mainly executes the cell transfer phase are configured to be different, so during the execution of the cell transfer phase, Execute the collision avoidance phase,
A cell output from the input buffer in the next cell transfer phase is selected. That is, the collision avoidance phase and the cell transfer phase are executed in a pipelined manner. In this way, by executing the collision avoidance phase and the cell transfer phase in a pipelined manner, the next cell transfer phase can be executed immediately after the end of a certain cell transfer phase, and efficient cell switching can be performed. realizable.

Furthermore, by repeating the collision avoidance phase a plurality of times during the time required to execute one cell transfer phase, the priority control based on the route information is executed according to the following algorithm.

In the first collision avoidance phase, the cell accumulation information including the route information of the cell is selected as a cell candidate for outputting the cell accumulated from the oldest of the cells accumulated in each input buffer. Are passed from the respective input buffers to the output cell selecting means to execute the collision avoidance phase. Then, in the n-th collision avoidance phase, the n-th
The input buffer whose output is permitted in the first collision avoidance phase creates cell accumulation information including the route information of the cell whose output is permitted, and the output is permitted in the (n-1) th collision avoidance phase. The input buffer that has not been stored is used as cell candidates for outputting cells stored in the n-th oldest cell among the cells stored in the input buffer, as cell candidates. The collision avoidance phase is executed by repeating the process of generating the received cell storage information generated in each input buffer by the output cell selecting means a predetermined number of times.

FIG. 2 is a diagram showing the configuration of the non-blocking type switch means 13 in this embodiment. As shown in the figure,
The non-blocking type switch means 13 is realized by a non-blocking multi-stage self-routing network known as a batcher omega network.

As is well known, a bit string as shown in FIG. 4, that is, an empty cell indication bit indicating whether or not the bit string includes a cell before the bit string of the cell, and an output communication path to which the cell is directed, The cell is given to the non-blocking type switch means 13 as a bit string to which an output port address which is a bit string to be specified is added. As is well known, in this case, if there is no cell going to the same output communication path, the batcher omega network constituting the non-blocking type switch means 13 is a non-blocking cell switch.
Here, the batcher network has a function of sorting the input cells according to the magnitude relation of the output port addresses of the input cells, and the omega network transfers the input cells to the output port specified by the output port address. Has a routing function to guide. Also, the route information and output port address of the cell input to each input buffer are usually different bit strings, but the correspondence is determined at the time of call setup executed in the communication system to start communication. The input buffer stores a conversion table between the route information and the output port address. When the input buffer receives a cell, it knows the output port address of the cell from the route information of the received cell, and The port address is attached to the received cell and stored.

In the cell transfer phase, an empty cell indication bit is added to the head of the bit sequence in the cell bit format shown in FIG. 4 for the case where there is an input buffer having no cell to be output. The empty cell indication bit is 0 when the following bit string includes a cell, and 1 when the bit string does not include a cell. In this case, sorting in the batcher network is performed so as to include empty cell indication bits, and in the omega network, the route to the bit string in which the empty cell indication bit is 0 is directed to an empty cell indication bit of 1
Is not affected by the path of the bit string.

The unit switch 26 of the batcher network shown in FIG. 2 is in a connected state between a straight state shown in FIG. 9 and a cross state shown in FIG. 10, and operates as shown in FIG. That is, at the start of the cell transfer phase, the unit switch 26 is set to the straight state shown in FIG. 9, and each bit of the two bit strings is sequentially input to the unit switch. The unit switch 26 compares the input two bits while outputting the two bits.
When these bits are different for the first time, the bit string containing 1 is output in the direction of the arrow indicated on the unit switch 26 in FIG. 11 and the bit string containing 0 is output in the opposite direction to the arrow. Then, a cross state or a straight state is selected as the state of the unit switch 26.

The unit switch 28 of the omega network shown in FIG. 2 operates as shown in FIG.

That is, each bit of the two bit strings is sequentially input to each unit switch 28, and each unit switch 28 crosses or straightens according to the state of the first two bits of the input bit string according to the truth table shown in FIG. Select a state. According to the selected state, the first bit and the third and subsequent bits of the input bit string are sequentially output, that is, the second bit is deleted and output.

FIG. 3 is a diagram showing the configuration of the output cell selecting means 24 in the present embodiment. Next, the collision avoidance phase executed by using the output cell selection means 24 will be described in detail with reference to FIG. The collision avoidance phase includes an output permission determination phase and an output permission notification phase subsequent to the output permission determination phase.

 The output permission determination phase is executed as follows.

The output cell selection means 24 receives the cell storage information having the configuration shown in FIG. 5 from each input buffer at the start of the output permission determination phase. The unit switches 26 of the batcher network in the output cell selection means 24 are all set to the straight state. When the valid bit of the cell accumulation information is 0, it indicates that the input buffer that has output the cell accumulation information has a cell candidate to output, and when it is 1, it does not have a cell candidate to output. Each is shown.

The cell storage information input to the output cell selection means 24 is firstly read from a valid bit and an output port address at the head of the cell storage information in the batcher network, and from a plurality of cells that cause blocking when blocking occurs. Sorting is performed according to priority control information used to select one cell to be output. Here, as the unit switch 26 of the batcher network in the output cell selection unit 24, the same unit switch as the unit switch 26 of the buffer network constituting the non-blocking type switch unit 13 can be used. It is configured using the same unit switch 26.

The sorted cell storage information is input to the collision detection circuit, and blocking detection is performed. The collision detection circuit has a configuration in which comparison means 30 are connected in cascade.
Each comparing means 30 notifies the output port address of the received cell accumulation information to its own comparing means, and compares the output port address notified from its own comparing means with its own output port address. I do. if,
If they match, blocking will occur. Therefore, it is assumed that no cell is output from the input buffer that has output the cell storage information, and this is changed by changing the valid bit of the input cell storage information from 0 to 1. This is achieved by: If the output port address notified from the comparing means on the own device is different from the own output port address, the cell selected as a candidate to be output from the input buffer which has output the cell accumulation information is output. In this case, the valid bit is not changed.

The valid bit is set to 1 at the time of input to the comparing means 30.
Is stored at the bottom of the collision detection circuit by the action of the batcher network. In this case, since the input buffer that outputs the cell storage information has no cells to output, No output permission is given.

The order in which the cell storage information is input to the collision detection circuit is, as shown in FIG. 5, a valid bit, an output port address, and priority control information. By giving the unique priority control information to the buffer, the selection of the cell accumulation information input to the collision detection circuit that should be permitted from the plurality of cell accumulation information that causes blocking is determined by the priority control information. It is determined. In the embodiment shown in FIG. 3, the one with the smallest value of the priority control information is selected from those in which blocking has occurred. In the present embodiment, the priority control information given to each input buffer is changed for each collision avoidance phase, so that the probability that cells are output from each input buffer is made fair.

After blocking is detected by the collision detection circuit,
Cell storage information is passed through an inverse banyan network and a banyan network, and a folding circuit provided for each output buffer.
Entered in 32. The cell storage information output from the collision detection circuit has the configuration shown in FIG. In the banyan network, routing is performed based on the output port address in the cell storage information. The inverse banyan network is a self-routing multistage network provided to avoid the occurrence of blocking inside the banyan network connected next to the inverse banyan network. The cell storage information is routed with reference to the intermediate port address added to the cell. Here, the unit switch 28 constituting the banyan network and the inverse banyan network can be the same as the unit switch 28 constituting the omega network of the non-blocking type switch means, and the same switch is used in this embodiment. Also, the cell storage information whose valid bit is 1 does not disturb the path of the cell storage information whose valid bit is 0.

 The intermediate port address is created as follows.

That is, when the comparison means 30 of the collision detection circuit compares the output port addresses and outputs the cell accumulation information, the numbers which output the effective bits as 0 are numbered sequentially from the top. This number is represented by a binary number, and a bit sequence in which the bit order is reversed is set as an intermediate port address. This numbering means, for example, that each comparison means 30 has an adder, the addition result of the adder is displayed on its own comparison means, and one of the two inputs of the adder is displayed by the upper comparison means. , And the other input is made by inverting a valid bit. Here, one of the inputs to the uppermost comparison means is 0, and the other is an inversion of valid bits.

As shown in FIG. 7, the cell storage information including the valid bits and the input port address, the intermediate port address and the output port address of which are deleted by the inverse banyan network and the banyan network, is input to the return circuit 32.

In the loopback circuit 32, buffer full information indicating whether or not each output buffer can newly store cells is reflected in the input cell storage information. More specifically, a loopback circuit that receives cell storage information whose valid bit is 0
32 refers to buffer full information of an output buffer provided corresponding to the loopback circuit, and if the buffer is full, that is, if there is no area for newly storing cells, the received cell storage information Change the valid bit to 1.

After that, each folding circuit 32 passes the received cell accumulation information via the path 101 to the input buffer to which the folding circuit is connected. Thus, the output permission determination phase ends.

After the output permission determination phase, an output permission notification phase is executed.

The output permission notifying phase is started by inputting the cell storage information received by the input buffer to the batcher network in the output cell selecting means 24 at the end of the output permission determining phase. In the batcher network, the input cell storage information is sorted by a valid bit of the input cell storage information and an input port address that is information for specifying an input buffer that has output the cell storage information, and a collision detection circuit is provided. Is input to each comparing means 30.

Each comparing means of the collision detection circuit to which the cell storage information is inputted
At 30, the same operation as that performed on the valid bit and the output port address in the output permission determination phase is performed on the valid bit and the input port address of the received cell storage information. Similarly, an intermediate port address is created, and the cell storage information is rewritten and input to the inverse banyan network and banyan network as shown in FIG. Here, in one collision avoidance phase, since one input buffer always outputs only one cell accumulation information, no blocking is detected by the collision detection circuit in the output permission notification phase.

In the inverse banyan network and the banyan network, the input cell storage information is routed using the effective bit, the intermediate port address, and the input port address of the cell storage information, and is passed to the return circuit 32.

The loopback circuit 32 transfers the passed cell accumulation information to the connected input buffer. At this time, the cell storage information has only valid bits. This ends the output permission notification phase. Each input buffer has
Whether or not the output of the candidate cell to be output is permitted is reflected in the valid bit of the received cell accumulation information. That is, if the valid bit of the cell storage information is 0
If so, the output is permitted, and if the valid bit is 1, it means that there is no candidate cell to output or that the output is not permitted.

The input buffer that has input the cell accumulation information whose valid bit is 1 outputs the permitted output candidate cell in the next cell transfer phase as described above.

As is apparent from the above description, in the present embodiment, when giving output permission to each input buffer, information about the storage margin of the output buffer is also taken into consideration, so that when inputting cells to the output buffer, However, cell discard due to the full state of the buffer does not occur.

The embodiments of the present invention are not limited to those described above, and various other embodiments are possible.

For example, it is not always necessary to pipeline and execute the collision avoidance phase and the cell transfer phase, and it is not always necessary to perform priority control based on route information.

Even in these cases, the inherent effects of the present invention are equally realized.

〔The invention's effect〕

As described above, according to the present invention, cells from a plurality of input buffers are exchanged in the same phase,
By preventing overflow of cells in the output buffer, the throughput of the switch can be improved, and the cell loss rate can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a cell switch according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a non-blocking type switch according to an embodiment of the present invention, and FIG. FIGS. 4 to 8 are diagrams showing the bit format of a cell handled inside the cell switch according to an embodiment of the present invention. FIGS.
11 and 12 are diagrams illustrating the operation of the unit switch used in one embodiment of the present invention, and FIG. 13 is a diagram illustrating the operation of the unit switch of the omega network, the inverse banyan network, and the banyan network. is there. 1 ... Cell switch 3,4,5,6,7,8,9,10 ... Input buffer 13 ... Non-blocking type switch means 15,16,17,18,19,20,21,22 ... Output buffer 24 ... Output cell Selection means 26, 28 ... Unit switch 30 ... Comparison circuit 32 ... Return circuit

Claims (2)

(57) [Claims] A plurality of input buffers for storing ATM cells transmitted from the input communication paths; and a plurality of input buffers connected to the input buffers for storing the ATM cells transmitted from the input communication paths. Among the ATM cells, the transfer permitted is received from a plurality of input buffers, and the received plurality of ATM cells are directed to at least one of a plurality of output communication paths in accordance with the route information of the ATM cells in the same phase, And switch means configured to transfer at a rate higher than the cell transfer rate on the output communication path; and ATM cells connected to the switch means and transferred at a rate higher than the cell transfer rate on the output communication path. A plurality of output buffers for outputting the ATM cells at a cell transfer rate on the output communication path to a corresponding output communication path; It is connected between the plurality of input buffers and holds the path information of one of the ATM cells stored in the input buffer from each of the plurality of input buffers, and stores the ATM cell of the output buffer from each of the plurality of output buffers. Information indicating the status is input in the same phase, respectively, based on the input route information and the information indicating the holding status, the ATM cell is transferred by the switch means without collision with other ATM cells, and When it is determined that the output buffer corresponding to the output communication path to which the ATM cell is to be transferred has a storage margin, it is determined that the transfer of the ATM cell by the switch unit is permitted, and whether or not the transfer is permitted is determined. A cell switch comprising output cell selection means for notifying each input buffer. 2. The cell switch according to claim 1, wherein the information indicating the ATM cell holding status is buffer full information.